From 11606e96f1e3fea2b8b02ab744aaf1b7cacd590f Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Sun, 4 Jul 2021 18:17:06 -0400
Subject: [PATCH] ICacheCntrl now reacts differently to InstrPageFaultF vs
 ITLBWriteF

---
 wally-pipelined/src/cache/ICacheCntrl.sv | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv
index 748b3f5e5..ee58ed6f4 100644
--- a/wally-pipelined/src/cache/ICacheCntrl.sv
+++ b/wally-pipelined/src/cache/ICacheCntrl.sv
@@ -115,8 +115,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
   localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address?
   localparam STATE_TLB_MISS = 'h13;
   localparam STATE_TLB_MISS_DONE = 'h14;
-  
-  
+  localparam STATE_INSTR_PAGE_FAULT = 'h15;
+
   
   localparam AHBByteLength = `XLEN / 8;
   localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
@@ -370,13 +370,20 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
         NextState = STATE_READY;
       end
       STATE_TLB_MISS: begin
-        if (ITLBWriteF | WalkerInstrPageFaultF) begin
+        if (WalkerInstrPageFaultF) begin
+          NextState = STATE_INSTR_PAGE_FAULT;
+          ICacheStallF = 1'b0;
+        end else if (ITLBWriteF) begin
           NextState = STATE_TLB_MISS_DONE;
         end else begin
           NextState = STATE_TLB_MISS;
         end
       end
-      STATE_TLB_MISS_DONE : begin
+      STATE_TLB_MISS_DONE: begin
+        NextState = STATE_READY;
+      end
+      STATE_INSTR_PAGE_FAULT: begin
+        ICacheStallF = 1'b0;
         NextState = STATE_READY;
       end
       default: begin