Added parity and stop bit tests to UART

pipelined/src/uncore/uartPC16550D.sv

@@ -328,9 +328,9 @@ module uartPC16550D(
         rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0;
       end else if (rxstate == UART_DONE) begin
         RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
-        if (rxoverrunerr) $warning("UART RX Overrun Error\n");
+        if (rxoverrunerr) $warning("UART RX Overrun Err\n");
-        if (rxparityerr) $warning("UART RX Parity Error\n");
+        if (rxparityerr) $warning("UART RX Parity Err\n");
-        if (rxframingerr) $warning("UART RX Framing Error\n");
+        if (rxframingerr) $warning("UART RX Framing Err\n");
         if (fifoenabled) begin
           rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
           rxfifohead <= #1 rxfifohead + 1;

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output

@@ -16,6 +16,12 @@
 0000007F
 00000101 # Transmit 8 bits
 ffffff80
+00000101 # Odd parity
+00000079
+00000101 # Even parity
+0000006A
+00000101 # Extra stop bit
+0000005B
 00000002 # Transmission interrupt tests
 00000401 # Interrupt generated by finished transmission
 00000004
@@ -62,7 +68,7 @@ ffffffC1 # Threshold = 8
 ffffffC1 # Threshold = 14
 0000C101
 0000C401
-0000C201
+0000C101
 00000061 # FIFO has data, no overrun
 00000006 # wait for interrupt
 ffffffA3 # FIFO overrun error

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -1072,9 +1072,9 @@ uart_data_wait:
     li t3, 0x10000002 // IIR
     li a4, 0x61
 uart_read_LSR_IIR:
-    lb t4, 0(t3) // save IIR before potential clear
+    lb t4, 0(t3) // save IIR before reading LSR mgith clear it
-    lb t5, 0(t2)
+    lb t5, 0(t2) // read LSR
-    andi t6, t5, 0x61  // only care if all transmissions are done
+    andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
     bne a4, t6, uart_read_LSR_IIR
 
 uart_data_ready:

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S

@@ -71,14 +71,14 @@ test_cases:
 
 .4byte UART_IER, 0x00, read08_test
 .4byte UART_IIR, 0x01, read08_test # IIR resets to 1
-# .4byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3
+# .4byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3 to help Linux boot
 .4byte UART_MCR, 0x00, read08_test
 .4byte UART_LSR, 0x60, read08_test # LSR resets with transmit status bits set
 .4byte UART_MSR, 0x00, read04_test
 
 # =========== Basic read-write ===========
 
-.4byte UART_LCR, 0x00, write08_test # set LCR to reset value *** remove if UART resets to correct value
+.4byte UART_LCR, 0x00, write08_test # set LCR to initial value
 .4byte UART_MCR, 0x10, write08_test # put UART into loopback for MSR test
 .4byte UART_LSR, 0x60, read08_test
 .4byte UART_THR, 0x00, write08_test # write value to UART
@@ -112,11 +112,33 @@ test_cases:
 
 # Transmit 8 bits
 
-.4byte UART_LCR, 0x03, write08_test # set LCR to transmit seven bits
+.4byte UART_LCR, 0x03, write08_test # set LCR to transmit eight bits
 .4byte UART_THR, 0x80, write08_test # write value to UART
 .4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
 .4byte UART_RBR, 0x80, read08_test  # read full written value + sign extension
 
+# Check function with odd parity
+
+.4byte UART_LCR, 0x0B, write08_test # set LCR to transmit 8 bits + odd partiy
+.4byte UART_THR, 0x79, write08_test # write value to UART
+.4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
+.4byte UART_RBR, 0x79, read08_test  # read full written value
+
+# Check function with even parity
+
+.4byte UART_LCR, 0x1B, write08_test # set LCR to transmit 8 bits + even parity
+.4byte UART_THR, 0x6A, write08_test # write value to UART
+.4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
+.4byte UART_RBR, 0x6A, read08_test  # read full written value
+
+# Check function with extra stop bit
+
+.4byte UART_LCR, 0x07, write08_test # set LCR to transmit 8 bits + extra stop
+.4byte UART_THR, 0x5B, write08_test # write value to UART
+.4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
+.4byte UART_RBR, 0x5B, read08_test  # read full written value
+.4byte UART_LCR, 0x03, write08_test # set LCR to transmit 8 bits + no extra stop bit
+
 # =========== Transmit-related interrupts ===========
 
 .4byte UART_IER, 0x07, write08_test     # enable data available, buffer empty, and line status interrupts
@@ -126,7 +148,7 @@ test_cases:
 .4byte UART_THR, 0x01, write08_test     # write 1 to transmitter buffer
 .4byte UART_IIR, 0x04, read08_test      # data interrupt should still be high
 .4byte 0x0, 0x06, uart_lsr_intr_wait    # wait for transmission to complete, IIR should throw error due to overrun error.
-.4byte UART_LSR, 0x63, read08_test      # read overrun error from LSR
+.4byte UART_LSR, 0x23, read08_test      # read overrun error from LSR
 .4byte UART_IIR, 0x04, read08_test      # check that LSR interrupt was cleared
 .4byte UART_RBR, 0x01, read08_test      # read previous value from UART
 
@@ -216,7 +238,7 @@ test_cases:
 .4byte 0x0, 0xC401, uart_data_wait  # Interrupt due to trigger threshold reached
 .4byte UART_THR, 0x0E, write08_test # Write 14 to transmit register
 .4byte UART_THR, 0x0F, write08_test # Write 15 to transmit register
-.4byte 0x0, 0xC201, uart_data_wait
+.4byte 0x0, 0xC101, uart_data_wait
 .4byte UART_LSR, 0x61, read08_test      # FIFO contains data, no overrun error
 .4byte UART_THR, 0x10, write08_test     # Write 16 to transmit register, filling RX shift register
 .4byte UART_THR, 0x11, write08_test     # Write 17 to transmit register, destroying contents held in shift register