diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 608bf4668..a12e5cda8 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -245,7 +245,7 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM @@ -255,93 +255,93 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadDataBlockWayMaskedM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadDataBlockWayMaskedM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadDataBlockWayMaskedM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadDataBlockWayMaskedM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/BlockReplacementBits -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/ReplacementBits +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadDataBlockWayMaskedM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadDataBlockWayMaskedM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadDataBlockWayMaskedM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadDataBlockWayMaskedM} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/BlockReplacementBits +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/ReplacementBits add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay @@ -356,14 +356,15 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/FetchCount +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation @@ -489,7 +490,7 @@ add wave -noupdate /testbench/dut/hart/ExceptionM add wave -noupdate /testbench/dut/hart/PendingInterruptM add wave -noupdate /testbench/dut/hart/TrapM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 6} {32245 ns} 0} {{Cursor 2} {32581 ns} 0} {{Cursor 3} {25666 ns} 0} {{Cursor 4} {2334 ns} 0} +WaveRestoreCursors {{Cursor 6} {32245 ns} 0} {{Cursor 2} {32581 ns} 0} {{Cursor 3} {25666 ns} 0} {{Cursor 4} {2221 ns} 0} quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -505,4 +506,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2287 ns} {2569 ns} +WaveRestoreZoom {1280 ns} {3534 ns} diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index cb0375281..228163632 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -135,51 +135,6 @@ module dcache logic LRUWriteEn; - typedef enum {STATE_READY, - - STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, - STATE_MISS_EVICT_DIRTY, - STATE_MISS_WRITE_CACHE_BLOCK, - STATE_MISS_READ_WORD, - STATE_MISS_READ_WORD_DELAY, - STATE_MISS_WRITE_WORD, - - STATE_PTW_READY, - STATE_PTW_READ_MISS_FETCH_WDV, - STATE_PTW_READ_MISS_FETCH_DONE, - STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_READ_MISS_EVICT_DIRTY, - STATE_PTW_READ_MISS_READ_WORD, - STATE_PTW_READ_MISS_READ_WORD_DELAY, - STATE_PTW_ACCESS_AFTER_WALK, - - STATE_UNCACHED_WRITE, - STATE_UNCACHED_WRITE_DONE, - STATE_UNCACHED_READ, - STATE_UNCACHED_READ_DONE, - - STATE_PTW_FAULT_READY, - STATE_PTW_FAULT_CPU_BUSY, - STATE_PTW_FAULT_MISS_FETCH_WDV, - STATE_PTW_FAULT_MISS_FETCH_DONE, - STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK, - STATE_PTW_FAULT_MISS_READ_WORD, - STATE_PTW_FAULT_MISS_READ_WORD_DELAY, - STATE_PTW_FAULT_MISS_WRITE_WORD, - STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY, - STATE_PTW_FAULT_MISS_EVICT_DIRTY, - - STATE_PTW_FAULT_UNCACHED_WRITE, - STATE_PTW_FAULT_UNCACHED_WRITE_DONE, - STATE_PTW_FAULT_UNCACHED_READ, - STATE_PTW_FAULT_UNCACHED_READ_DONE, - - STATE_CPU_BUSY, - STATE_CPU_BUSY_FINISH_AMO} statetype; - - statetype CurrState, NextState; - // data path mux3 #(INDEXLEN) @@ -334,7 +289,6 @@ module dcache localparam FetchCountThreshold = WORDSPERLINE - 1; - assign AnyCPUReqM = |MemRWM | (|AtomicM); assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]); flopenr #(LOGWPL) @@ -351,660 +305,44 @@ module dcache // control path *** eventually move to own module. - always_ff @(posedge clk, posedge reset) - if (reset) CurrState <= #1 STATE_READY; - else CurrState <= #1 NextState; - + dcachefsm dcachefsm(.clk, + .reset, + .MemRWM, + .AtomicM, + .ExceptionM, + .PendingInterruptM, + .StallWtoDCache, + .DTLBMissM, + .ITLBMissF, + .CacheableM, + .DTLBWriteM, + .ITLBWriteF, + .WalkerInstrPageFaultF, + .SelPTW, + .WalkerPageFaultM, + .AHBAck, // from ahb + .CacheHit, + .FetchCountFlag, + .VictimDirty, + .DCacheStall, + .CommittedM, + .DCacheMiss, + .DCacheAccess, + .MemAfterIWalkDone, + .AHBRead, + .AHBWrite, + .SelAdrM, + .CntEn, + .SetValid, + .ClearValid, + .SetDirty, + .ClearDirty, + .SRAMWordWriteEnableM, + .SRAMBlockWriteEnableM, + .CntReset, + .SelUncached, + .SelEvict, + .LRUWriteEn); - // next state logic and some state ouputs. - always_comb begin - DCacheStall = 1'b0; - SelAdrM = 2'b00; - PreCntEn = 1'b0; - SetValid = 1'b0; - ClearValid = 1'b0; - SetDirty = 1'b0; - ClearDirty = 1'b0; - SRAMWordWriteEnableM = 1'b0; - SRAMBlockWriteEnableM = 1'b0; - CntReset = 1'b0; - AHBRead = 1'b0; - AHBWrite = 1'b0; - CommittedM = 1'b0; - SelUncached = 1'b0; - SelEvict = 1'b0; - DCacheAccess = 1'b0; - DCacheMiss = 1'b0; - LRUWriteEn = 1'b0; - MemAfterIWalkDone = 1'b0; - - case (CurrState) - STATE_READY: begin - // TLB Miss - if((AnyCPUReqM & DTLBMissM) | ITLBMissF) begin - // the LSU arbiter has not yet selected the PTW. - // The CPU needs to be stalled until that happens. - // If we set DCacheStall for 1 cycle before going to - // PTW ready the CPU will stall. - // The page table walker asserts it's control 1 cycle - // after the TLBs miss. - CommittedM = 1'b1; - DCacheStall = 1'b1; - NextState = STATE_PTW_READY; - end - // amo hit - else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - SelAdrM = 2'b01; - DCacheStall = 1'b0; - - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY_FINISH_AMO; - SelAdrM = 2'b01; - end - else begin - SRAMWordWriteEnableM = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_READY; - end - end - // read hit valid cached - else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - DCacheStall = 1'b0; - DCacheAccess = 1'b1; - LRUWriteEn = 1'b1; - - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - // write hit valid cached - else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin - SelAdrM = 2'b01; - DCacheStall = 1'b0; - SRAMWordWriteEnableM = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - // read or write miss valid cached - else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_MISS_FETCH_WDV; - CntReset = 1'b1; - DCacheStall = 1'b1; - DCacheAccess = 1'b1; - DCacheMiss = 1'b1; - end - // uncached write - else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin - NextState = STATE_UNCACHED_WRITE; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBWrite = 1'b1; - end - // uncached read - else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin - NextState = STATE_UNCACHED_READ; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBRead = 1'b1; - end - // fault - else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin - NextState = STATE_READY; - end - else NextState = STATE_READY; - end - - STATE_MISS_FETCH_WDV: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBRead = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - - if (FetchCountFlag & AHBAck) begin - NextState = STATE_MISS_FETCH_DONE; - end else begin - NextState = STATE_MISS_FETCH_WDV; - end - end - - STATE_MISS_FETCH_DONE: begin - DCacheStall = 1'b1; - SelAdrM = 2'b01; - CntReset = 1'b1; - CommittedM = 1'b1; - if(VictimDirty) begin - NextState = STATE_MISS_EVICT_DIRTY; - end else begin - NextState = STATE_MISS_WRITE_CACHE_BLOCK; - end - end - - STATE_MISS_WRITE_CACHE_BLOCK: begin - SRAMBlockWriteEnableM = 1'b1; - DCacheStall = 1'b1; - NextState = STATE_MISS_READ_WORD; - SelAdrM = 2'b01; - SetValid = 1'b1; - ClearDirty = 1'b1; - CommittedM = 1'b1; - //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write - end - - STATE_MISS_READ_WORD: begin - SelAdrM = 2'b01; - DCacheStall = 1'b1; - CommittedM = 1'b1; - if (MemRWM[0]) begin // handles stores and amo write. - NextState = STATE_MISS_WRITE_WORD; - end else begin - NextState = STATE_MISS_READ_WORD_DELAY; - // delay state is required as the read signal MemRWM[1] is still high when we - // return to the ready state because the cache is stalling the cpu. - end - end - - STATE_MISS_READ_WORD_DELAY: begin - //SelAdrM = 2'b01; - CommittedM = 1'b1; - if(&MemRWM & AtomicM[1]) begin // amo write - SelAdrM = 2'b01; - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY_FINISH_AMO; - end - else begin - SRAMWordWriteEnableM = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_READY; - end - end else begin - LRUWriteEn = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - end - - STATE_MISS_WRITE_WORD: begin - SRAMWordWriteEnableM = 1'b1; - SetDirty = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - LRUWriteEn = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - - STATE_MISS_EVICT_DIRTY: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBWrite = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - SelEvict = 1'b1; - if( FetchCountFlag & AHBAck) begin - NextState = STATE_MISS_WRITE_CACHE_BLOCK; - end else begin - NextState = STATE_MISS_EVICT_DIRTY; - end - end - - STATE_PTW_READY: begin - // now all output connect to PTW instead of CPU. - CommittedM = 1'b1; - - // In this branch we remove stall and go back to ready. There is no request for memory from the - // datapath or the walker had a fault. - // types 3b, 4a, 4b, and 7c. - if ((DTLBMissM & WalkerPageFaultM) | // 3b - (ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b - (DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c - NextState = STATE_READY; - DCacheStall = 1'b0; - end - // in this branch we go back to ready, but there is a memory operation from - // the datapath so we MUST stall and replay the operation. - // types 3a and 5a - else if ((DTLBMissM & DTLBWriteM) | // 3a - (ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a - NextState = STATE_READY; - DCacheStall = 1'b1; - SelAdrM = 2'b10; - end - - // like 5a we want to stall and go to the ready state, but we also have to save - // the WalkerInstrPageFaultF so it is held until the end of the memory operation - // from the datapath. - // types 5b - else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b - NextState = STATE_PTW_FAULT_READY; - DCacheStall = 1'b1; - SelAdrM = 2'b10; - end - - // in this branch we stay in ptw_ready because we are doing an itlb walk - // after a dtlb walk. - // types 7a and 7b. - else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin - NextState = STATE_PTW_READY; - DCacheStall = 1'b0; - - // read hit valid cached - end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin - NextState = STATE_PTW_READY; - DCacheStall = 1'b0; - LRUWriteEn = 1'b1; - end - - // read miss valid cached - else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin - NextState = STATE_PTW_READ_MISS_FETCH_WDV; - CntReset = 1'b1; - DCacheStall = 1'b1; - end - - else begin - NextState = STATE_PTW_READY; - DCacheStall = 1'b0; - end - end - - STATE_PTW_READ_MISS_FETCH_WDV: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBRead = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - - if (FetchCountFlag & AHBAck) begin - NextState = STATE_PTW_READ_MISS_FETCH_DONE; - end else begin - NextState = STATE_PTW_READ_MISS_FETCH_WDV; - end - end - - STATE_PTW_READ_MISS_FETCH_DONE: begin - DCacheStall = 1'b1; - SelAdrM = 2'b01; - CntReset = 1'b1; - CommittedM = 1'b1; - CntReset = 1'b1; - if(VictimDirty) begin - NextState = STATE_PTW_READ_MISS_EVICT_DIRTY; - end else begin - NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK; - end - end - - STATE_PTW_READ_MISS_EVICT_DIRTY: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBWrite = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - SelEvict = 1'b1; - if(FetchCountFlag & AHBAck) begin - NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK; - end else begin - NextState = STATE_PTW_READ_MISS_EVICT_DIRTY; - end - end - - - STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin - SRAMBlockWriteEnableM = 1'b1; - DCacheStall = 1'b1; - NextState = STATE_PTW_READ_MISS_READ_WORD; - SelAdrM = 2'b01; - SetValid = 1'b1; - ClearDirty = 1'b1; - CommittedM = 1'b1; - //LRUWriteEn = 1'b1; - end - - STATE_PTW_READ_MISS_READ_WORD: begin - SelAdrM = 2'b01; - DCacheStall = 1'b1; - CommittedM = 1'b1; - NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY; - end - - STATE_PTW_READ_MISS_READ_WORD_DELAY: begin - SelAdrM = 2'b01; - NextState = STATE_PTW_READY; - CommittedM = 1'b1; - end - - STATE_PTW_ACCESS_AFTER_WALK: begin - DCacheStall = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_READY; - end - - STATE_CPU_BUSY: begin - CommittedM = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - - STATE_CPU_BUSY_FINISH_AMO: begin - CommittedM = 1'b1; - SelAdrM = 2'b01; - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY_FINISH_AMO; - end - else begin - SRAMWordWriteEnableM = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_READY; - end - end - - STATE_UNCACHED_WRITE : begin - DCacheStall = 1'b1; - AHBWrite = 1'b1; - CommittedM = 1'b1; - if(AHBAck) begin - NextState = STATE_UNCACHED_WRITE_DONE; - end else begin - NextState = STATE_UNCACHED_WRITE; - end - end - - STATE_UNCACHED_READ : begin - DCacheStall = 1'b1; - AHBRead = 1'b1; - CommittedM = 1'b1; - if(AHBAck) begin - NextState = STATE_UNCACHED_READ_DONE; - end else begin - NextState = STATE_UNCACHED_READ; - end - end - - STATE_UNCACHED_WRITE_DONE: begin - CommittedM = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - - STATE_UNCACHED_READ_DONE: begin - CommittedM = 1'b1; - SelUncached = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - - - // itlb => instruction page fault states with memory request. - STATE_PTW_FAULT_READY: begin - // read hit valid cached - if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin - DCacheStall = 1'b0; - DCacheAccess = 1'b1; - LRUWriteEn = 1'b1; - - if(StallWtoDCache) begin - NextState = STATE_PTW_FAULT_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - - // write hit valid cached - else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin - SelAdrM = 2'b01; - DCacheStall = 1'b0; - SRAMWordWriteEnableM = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - - if(StallWtoDCache) begin - NextState = STATE_PTW_FAULT_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - // read or write miss valid cached - else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin - NextState = STATE_PTW_FAULT_MISS_FETCH_WDV; - CntReset = 1'b1; - DCacheStall = 1'b1; - DCacheAccess = 1'b1; - DCacheMiss = 1'b1; - end - // uncached write - else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin - NextState = STATE_PTW_FAULT_UNCACHED_WRITE; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBWrite = 1'b1; - end - // uncached read - else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin - NextState = STATE_PTW_FAULT_UNCACHED_READ; - CntReset = 1'b1; - DCacheStall = 1'b1; - AHBRead = 1'b1; - end - // fault - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - - STATE_PTW_FAULT_CPU_BUSY: begin - CommittedM = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_PTW_FAULT_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - - STATE_PTW_FAULT_MISS_FETCH_WDV: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBRead = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - - if (FetchCountFlag & AHBAck) begin - NextState = STATE_PTW_FAULT_MISS_FETCH_DONE; - end else begin - NextState = STATE_PTW_FAULT_MISS_FETCH_WDV; - end - end - - STATE_PTW_FAULT_MISS_FETCH_DONE: begin - DCacheStall = 1'b1; - SelAdrM = 2'b01; - CntReset = 1'b1; - CommittedM = 1'b1; - if(VictimDirty) begin - NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY; - end else begin - NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK; - end - end - - STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK: begin - SRAMBlockWriteEnableM = 1'b1; - DCacheStall = 1'b1; - NextState = STATE_PTW_FAULT_MISS_READ_WORD; - SelAdrM = 2'b01; - SetValid = 1'b1; - ClearDirty = 1'b1; - CommittedM = 1'b1; - //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write - end - - STATE_PTW_FAULT_MISS_READ_WORD: begin - SelAdrM = 2'b01; - DCacheStall = 1'b1; - CommittedM = 1'b1; - if (MemRWM[1]) begin - NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY; - // delay state is required as the read signal MemRWM[1] is still high when we - // return to the ready state because the cache is stalling the cpu. - end else begin - NextState = STATE_PTW_FAULT_MISS_WRITE_WORD; - end - end - - STATE_PTW_FAULT_MISS_READ_WORD_DELAY: begin - CommittedM = 1'b1; - LRUWriteEn = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_PTW_FAULT_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - - STATE_PTW_FAULT_MISS_WRITE_WORD: begin - SRAMWordWriteEnableM = 1'b1; - SetDirty = 1'b1; - SelAdrM = 2'b01; - DCacheStall = 1'b1; - CommittedM = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY; - end - - STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY: begin - CommittedM = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_PTW_FAULT_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - - STATE_PTW_FAULT_MISS_EVICT_DIRTY: begin - DCacheStall = 1'b1; - PreCntEn = 1'b1; - AHBWrite = 1'b1; - SelAdrM = 2'b01; - CommittedM = 1'b1; - SelEvict = 1'b1; - if(FetchCountFlag & AHBAck) begin - NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK; - end else begin - NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY; - end - end - - - STATE_PTW_FAULT_UNCACHED_WRITE : begin - DCacheStall = 1'b1; - AHBWrite = 1'b1; - CommittedM = 1'b1; - if(AHBAck) begin - NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE; - end else begin - NextState = STATE_PTW_FAULT_UNCACHED_WRITE; - end - end - - STATE_PTW_FAULT_UNCACHED_READ : begin - DCacheStall = 1'b1; - AHBRead = 1'b1; - CommittedM = 1'b1; - if(AHBAck) begin - NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE; - end else begin - NextState = STATE_PTW_FAULT_UNCACHED_READ; - end - end - - STATE_PTW_FAULT_UNCACHED_WRITE_DONE: begin - CommittedM = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_PTW_FAULT_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - - STATE_PTW_FAULT_UNCACHED_READ_DONE: begin - CommittedM = 1'b1; - SelUncached = 1'b1; - if(StallWtoDCache) begin - NextState = STATE_PTW_FAULT_CPU_BUSY; - SelAdrM = 2'b01; - end - else begin - MemAfterIWalkDone = 1'b1; - NextState = STATE_READY; - end - end - - default: begin - end - endcase - end - - assign CntEn = PreCntEn & AHBAck; endmodule // dcache