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Additional cleanup.

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This commit is contained in:
Rose Thompson 2023-11-28 23:28:50 -06:00
parent 4149ae6c11
commit d29b2b95f7
1 changed files with 2 additions and 7 deletions
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9
src/lsu/align.sv
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@ -62,7 +62,6 @@ module align import cvw::*; #(parameter cvw_t P) (
statetype CurrState, NextState; statetype CurrState, NextState;
logic ValidSpillM; logic ValidSpillM;
logic SpillM;
logic SelSpillM; logic SelSpillM;
logic SpillSaveM; logic SpillSaveM;
logic [P.LLEN-1:0] ReadDataWordFirstHalfM; logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
@ -74,7 +73,6 @@ module align import cvw::*; #(parameter cvw_t P) (
logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM; logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
logic [$clog2(LLENINBYTES)+2:0] ShiftAmount; logic [$clog2(LLENINBYTES)+2:0] ShiftAmount;
logic ValidAccess;
logic PotentialSpillM; logic PotentialSpillM;
/* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHEXPAND */
@ -92,8 +90,6 @@ module align import cvw::*; #(parameter cvw_t P) (
// 2) offset // 2) offset
// 3) access location within the cacheline // 3) access location within the cacheline
assign ValidAccess = (|MemRWM);
// compute misalignement // compute misalignement
always_comb begin always_comb begin
case (Funct3M[1:0]) case (Funct3M[1:0])
@ -111,10 +107,9 @@ module align import cvw::*; #(parameter cvw_t P) (
default: PotentialSpillM = '0; default: PotentialSpillM = '0;
endcase endcase
end end
assign MisalignedM = ValidAccess & (AccessByteOffsetM != '0); assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != '0);
assign SpillM = MisalignedM & PotentialSpillM;
assign ValidSpillM = SpillM & ~CacheBusHPWTStall; // Don't take the spill if there is a stall assign ValidSpillM = MisalignedM & PotentialSpillM & ~CacheBusHPWTStall; // Don't take the spill if there is a stall
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset | FlushM) CurrState <= #1 STATE_READY; if (reset | FlushM) CurrState <= #1 STATE_READY;