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Remove imem from testbenches

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This commit is contained in:
Thomas Fleming 2021-04-14 20:20:34 -04:00
parent ccff1e6c99
commit d281ecd067
6 changed files with 4 additions and 9 deletions
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5
wally-pipelined/src/wally/wallypipelinedsoc.sv
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@ -72,6 +72,9 @@ module wallypipelinedsoc (
// instantiate processor and memories
wallypipelinedhart hart(.*);
imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
// *** Temporary driving of access fault to low until PMA checker is complete
assign InstrAccessFaultF = '0;
// instructions now come from uncore memory. This line can be removed at any time.
// imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
uncore uncore(.HWDATAIN(HWDATA), .*);
endmodule

2
wally-pipelined/testbench/testbench-busybear.sv
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@ -99,8 +99,6 @@ module testbench_busybear();
initial begin
$readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.uncore.bootdtim.RAM, 'h1000 >> 3);
$readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.uncore.dtim.RAM);
$readmemh("/courses/e190ax/busybear_boot_new/bootmem.txt", dut.imem.bootram, 'h1000 >> 3);
$readmemh("/courses/e190ax/busybear_boot_new/ram.txt", dut.imem.RAM);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
end

1
wally-pipelined/testbench/testbench-coremark.sv
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@ -78,7 +78,6 @@ module testbench();
totalerrors = 0;
// read test vectors into memory
memfilename = tests[0];
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=18710; j < 65535; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0;

1
wally-pipelined/testbench/testbench-coremark_bare.sv
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@ -80,7 +80,6 @@ module testbench();
totalerrors = 0;
// read test vectors into memory
memfilename = tests[0];
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
for(j=268437702; j < 268566528; j = j+1)
dut.uncore.dtim.RAM[j] = 64'b0;

2
wally-pipelined/testbench/testbench-imperas.sv
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@ -450,7 +450,6 @@ module testbench();
end
// read test vectors into memory
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
@ -525,7 +524,6 @@ module testbench();
end
else begin
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
$display("Read memfile %s", memfilename);
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};

2
wally-pipelined/testbench/testbench-privileged.sv
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@ -116,7 +116,6 @@ module testbench();
end
// read test vectors into memory
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
@ -191,7 +190,6 @@ module testbench();
end
else begin
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
$readmemh(memfilename, dut.imem.RAM);
$readmemh(memfilename, dut.uncore.dtim.RAM);
$display("Read memfile %s", memfilename);
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};