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fdivsqrtpreproc shift simplification
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@ -57,7 +57,6 @@ module fdivsqrtpreproc (
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// Intdiv signals
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// Intdiv signals
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
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logic [`DIVBLEN:0] mE;
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logic [`DIVBLEN:0] mE;
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logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
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logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
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logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
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logic [`LOGRK:0] pPrTrunc;
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logic [`LOGRK:0] pPrTrunc;
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logic [`DIVb+3:0] PreShiftX;
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logic [`DIVb+3:0] PreShiftX;
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@ -71,6 +70,7 @@ module fdivsqrtpreproc (
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logic AsE, BsE, ALTBE, NegQuotE;
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logic AsE, BsE, ALTBE, NegQuotE;
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logic [`XLEN-1:0] AE, BE;
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logic [`XLEN-1:0] AE, BE;
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logic [`XLEN-1:0] PosA, PosB;
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logic [`XLEN-1:0] PosA, PosB;
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logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
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// Extract inputs, signs, zero, depending on W64 mode if applicable
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// Extract inputs, signs, zero, depending on W64 mode if applicable
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assign signedDiv = ~Funct3E[0];
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assign signedDiv = ~Funct3E[0];
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@ -108,12 +108,12 @@ module fdivsqrtpreproc (
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/* verilator lint_off WIDTH */
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/* verilator lint_off WIDTH */
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// right shift amount to complete in discrete number of steps
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// right shift amount to complete in discrete number of steps
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assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
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assign pPlusr = `LOGR + p;
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assign pPrTrunc = pPlusr % `RK;
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assign pPrTrunc = pPlusr % `RK;
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assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN{1'b0}}, |(pPrTrunc)};
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assign pPrCeil = (pPlusr >> `LOGRK) + |pPrTrunc;
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assign nE = (pPrCeil * (`DIVBLEN+1)'(`DIVCOPIES)) - {{(`DIVBLEN){1'b0}}, 1'b1};
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assign nE = (pPrCeil * `DIVCOPIES) - 1;
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assign IntBits = (`DIVBLEN)'(`LOGR) + p - {{(`DIVBLEN){1'b0}}, 1'b1};
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assign IntBits = `LOGR + p - 1;
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assign RightShiftX = ((`DIVBLEN)'(`RK) - 1) - (IntBits % `RK);
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assign RightShiftX = `RK - 1 - IntBits % `RK;
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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// Selet integer or floating-point operands
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// Selet integer or floating-point operands
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