From d22587090bfcab76ef7572ddfc5eb0a1dc8bd105 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 22 Jul 2022 04:29:27 +0000
Subject: [PATCH] Reset MSR on read

---
 pipelined/src/uncore/uartPC16550D.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv
index 89bdc837d..5eabe60c7 100644
--- a/pipelined/src/uncore/uartPC16550D.sv
+++ b/pipelined/src/uncore/uartPC16550D.sv
@@ -206,6 +206,8 @@ module uartPC16550D(
       // Modem Status Register (8.6.8)
       if (~MEMWb & (A == 3'b110))
         MSR <= #1 Din[3:0];
+      else if (~MEMRb & (A == 3'b110)) 
+        MSR <= #1 4'b0; // Reading MSR clears the flags in MSR bits 3:0
       else begin
         MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
         MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready