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Shared haredware for aes64e
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@ -42,7 +42,7 @@ module aes32d(
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aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
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aesinvsbox inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si
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assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
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assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box
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aesinvmixcolumns mix(so, mixed); // Run so through the mixword AES function
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aesinvmixcolumns mix(so, mixed); // Run so through the mixword AES function
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mux2 #(32) rmux(mixed, so, finalround, rotin); // on final round, rotate so rather than mixed
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mux2 #(32) rmux(mixed, so, finalround, rotin); // on final round, skip mixcolumns
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rotate #(32) rot(rotin, shamt, rotout); // Rotate left by shamt (bs * 8)
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rotate #(32) rot(rotin, shamt, rotout); // Rotate left by shamt (bs * 8)
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assign result = rs1 ^ rotout; // xor with running value
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assign result = rs1 ^ rotout; // xor with running value
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endmodule
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endmodule
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@ -42,7 +42,7 @@ module aes32e(
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aessbox sbox(SboxIn, SboxOut); // Substitute
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aessbox sbox(SboxIn, SboxOut); // Substitute
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assign so = {24'h0, SboxOut}; // Pad sbox output
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assign so = {24'h0, SboxOut}; // Pad sbox output
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aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component
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aesmixcolumns mwd(so, mixed); // Mix Word using aesmixword component
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mux2 #(32) rmux(mixed, so, finalround, rotin); // on final round, rotate so rather than mixed
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mux2 #(32) rmux(mixed, so, finalround, rotin); // on final round, skip mixcolumns
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rotate #(32) mrot(rotin, shamt, rotout); // Rotate the mixcolumns output left by shamt (bs * 8)
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rotate #(32) mrot(rotin, shamt, rotout); // Rotate the mixcolumns output left by shamt (bs * 8)
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assign result = rs1 ^ rotout; // xor with running value
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assign result = rs1 ^ rotout; // xor with running value
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endmodule
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endmodule
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@ -33,20 +33,19 @@ module aes64d(
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);
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);
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logic [127:0] ShiftRowOut;
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logic [127:0] ShiftRowOut;
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logic [31:0] SboxOut0, SboxOut1;
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logic [63:0] SboxOut, MixcolOut;
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logic [31:0] MixcolOut0, MixcolOut1;
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// Apply inverse shiftrows to rs2 and rs1
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// Apply inverse shiftrows to rs2 and rs1
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aesinvshiftrow srow({rs2, rs1}, ShiftRowOut);
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aesinvshiftrow srow({rs2, rs1}, ShiftRowOut);
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// Apply full word inverse substitution to lower 2 words of shiftrow out
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// Apply full word inverse substitution to lower 2 words of shiftrow out
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aesinvsboxword invsbox0(ShiftRowOut[31:0], SboxOut0);
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aesinvsboxword invsbox0(ShiftRowOut[31:0], SboxOut[31:0]);
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aesinvsboxword invsbox1(ShiftRowOut[63:32], SboxOut1);
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aesinvsboxword invsbox1(ShiftRowOut[63:32], SboxOut[63:32]);
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// Apply inverse mixword to sbox outputs
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// Apply inverse mixword to sbox outputs
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aesinvmixcolumns invmw0(SboxOut0, MixcolOut0);
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aesinvmixcolumns invmw0(SboxOut[31:0], MixcolOut[31:0]);
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aesinvmixcolumns invmw1(SboxOut1, MixcolOut1);
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aesinvmixcolumns invmw1(SboxOut[63:32], MixcolOut[63:32]);
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// Concatenate mixed words for output
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// Final round skips mixcolumns.
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mux2 #(64) resultmux({SboxOut1, SboxOut0}, {MixcolOut1, MixcolOut0}, finalround, result);
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mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
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endmodule
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endmodule
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@ -1,10 +1,10 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// aes64esm.sv
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// aes64e.sv
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//
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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// Created: 20 February 2024
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//
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//
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// Purpose: aes64esm instruction: RV64 middle round encryption
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// Purpose: aes64esm and aes64es instruction: RV64 middle and final round AES encryption
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//
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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// https://github.com/openhwgroup/cvw
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@ -25,14 +25,15 @@
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// and limitations under the License.
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes64esm(
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module aes64e(
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input logic [63:0] rs1,
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input logic [63:0] rs1,
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input logic [63:0] rs2,
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input logic [63:0] rs2,
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output logic [63:0] DataOut
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input logic finalround,
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output logic [63:0] result
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);
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);
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logic [127:0] ShiftRowOut;
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logic [127:0] ShiftRowOut;
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logic [63:0] SboxOut;
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logic [63:0] SboxOut, MixcolOut;
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// AES shiftrow unit
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// AES shiftrow unit
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aesshiftrow srow({rs2,rs1}, ShiftRowOut);
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aesshiftrow srow({rs2,rs1}, ShiftRowOut);
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@ -42,6 +43,9 @@ module aes64esm(
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aessboxword sbox1(ShiftRowOut[63:32], SboxOut[63:32]);
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aessboxword sbox1(ShiftRowOut[63:32], SboxOut[63:32]);
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// Apply mix columns operations
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// Apply mix columns operations
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aesmixcolumns mw0(SboxOut[31:0], DataOut[31:0]);
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aesmixcolumns mw0(SboxOut[31:0], MixcolOut[31:0]);
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aesmixcolumns mw1(SboxOut[63:32], DataOut[63:32]);
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aesmixcolumns mw1(SboxOut[63:32], MixcolOut[63:32]);
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// Skip mixcolumns on last round
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mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
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endmodule
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endmodule
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@ -1,42 +0,0 @@
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///////////////////////////////////////////
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// aes64es.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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//
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// Purpose: aes64es instruction: RV64 final round encryption
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module aes64es(
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input logic [63:0] rs1,
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input logic [63:0] rs2,
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output logic [63:0] DataOut
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);
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logic [127:0] ShiftRowOut;
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// AES shiftrow unit
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aesshiftrow srow({rs2,rs1}, ShiftRowOut);
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// Apply substitution box to 2 lower words
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aessboxword sbox0(ShiftRowOut[31:0], DataOut[31:0]);
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aessboxword sbox1(ShiftRowOut[63:32], DataOut[63:32]);
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endmodule
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@ -37,8 +37,7 @@ module zknd64 #(parameter WIDTH=32) (
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logic [63:0] aes64dRes, aes64imRes, aes64ks1iRes, aes64ks2Res;
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logic [63:0] aes64dRes, aes64imRes, aes64ks1iRes, aes64ks2Res;
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// RV64
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// RV64
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// aes64ds aes64ds(.rs1(A), .rs2(B), .DataOut(aes64dsRes));
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aes64d aes64d(.rs1(A), .rs2(B), .finalround(~ZKNDSelect[0]), .result(aes64dRes)); // decode AES
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aes64d aes64d(.rs1(A), .rs2(B), .finalround(ZKNDSelect[0]), .result(aes64dRes)); // decode AES
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aes64im aes64im(.rs1(A), .DataOut(aes64imRes));
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aes64im aes64im(.rs1(A), .DataOut(aes64imRes));
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aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
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aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
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aes64ks2 aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res));
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aes64ks2 aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res));
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@ -34,14 +34,13 @@ module zkne64 #(parameter WIDTH=32) (
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output logic [WIDTH-1:0] ZKNEResult
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output logic [WIDTH-1:0] ZKNEResult
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);
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);
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logic [63:0] aes64esRes, aes64esmRes, aes64ks1iRes, aes64ks2Res;
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logic [63:0] aes64eRes, aes64ks1iRes, aes64ks2Res;
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// RV64
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// RV64
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aes64es aes64es(.rs1(A), .rs2(B), .DataOut(aes64esRes));
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aes64e aes64e(.rs1(A), .rs2(B), .finalround(~ZKNESelect[0]), .result(aes64eRes));
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aes64esm aes64esm(.rs1(A), .rs2(B), .DataOut(aes64esmRes));
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aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
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aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
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aes64ks2 aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res));
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aes64ks2 aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res));
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// 010 is a placeholder to match the select of ZKND's AES64KS1I since they share some instruction
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// 010 is a placeholder to match the select of ZKND's AES64KS1I since they share some instruction
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mux5 #(WIDTH) zknemux(aes64esRes, aes64esmRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);
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mux5 #(WIDTH) zknemux(aes64eRes, aes64eRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);
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endmodule
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endmodule
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