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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Ross Thompson 2023-06-15 14:57:23 -05:00
commit d2219023c3
98 changed files with 1848 additions and 1762 deletions
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36
Makefile
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@ -4,7 +4,11 @@
all:
make install
make regression
make testfloat
make riscof
make verify
make coverage
make benchmarks
# install copies over the Makefile.include from riscv-isa-sim
# And corrects the TARGETDIR path and the RISCV_PREFIX
@ -18,9 +22,37 @@ install:
##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
regression:
riscof:
make -C sim
testfloat:
cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
cd ${WALLY}/tests/fp; ./create_all_vectors.sh
verify:
cd ${WALLY}/sim; ./regression-wally
cd ${WALLY}/sim; ./sim-testfloat-batch all
make imperasdv
imperasdv:
iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
coverage:
cd ${WALLY}/sim; ./regresssion-wally -coverage -fp
benchmarks:
make coremark
make embench
coremark:
cd ${WALLY}/benchmarks/coremark; make; make run
embench:
cd ${WALLY}/benchmarks/embench; make; make run
clean:
make clean -C sim

6
benchmarks/coremark/Makefile
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@ -11,7 +11,11 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
ARCH := rv$(XLEN)gc
#ARCH := rv$(XLEN)gc_zba_zbb_zbc_zbs
#ARCH := rv$(XLEN)gc
ARCH := rv$(XLEN)imc_zicsr
#ARCH := rv$(XLEN)im_zicsr
#ARCH := rv$(XLEN)i_zicsr
PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \

19
bin/wally-tool-chain-install.sh
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@ -45,7 +45,7 @@ sudo mkdir -p $RISCV
# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
sudo apt update -y
sudo apt upgrade -y
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
# Other python libraries used through the book.
sudo pip3 install matplotlib scipy scikit-learn adjustText lief
@ -113,6 +113,23 @@ cd ../arch_test_target/spike/device
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
# Wally needs Verilator 5.0 or later.
# Verilator needs to be built from scratch to get the latest version
# apt-get install verilator installs version 4.028 as of 6/8/23
sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlibc zlib1g
sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error)
cd $RISCV
git clone https://github.com/verilator/verilator # Only first time
unsetenv VERILATOR_ROOT # For csh; ignore error if on bash
unset VERILATOR_ROOT # For bash
cd verilator
git pull # Make sure git repository is up-to-date
git checkout master # Use development branch (e.g. recent bug fixes)
autoconf # Create ./configure script
./configure # Configure and create Makefile
make -j NUM_THREADS # Build Verilator itself (if error, try just 'make')
sudo make install
# Sail (https://github.com/riscv/sail-riscv)
# Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which
# is an object-oriented extension of ML, which in turn is a functional programming

8
config/buildroot/config.vh
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@ -40,10 +40,16 @@ localparam IEEE754 = 0;
localparam MISA = (32'h0014112D);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv32e/config.vh
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@ -41,9 +41,14 @@ localparam MISA = (32'h00000010);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd0;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv32gc/config.vh
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@ -42,9 +42,14 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 |
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

9
config/rv32i/config.vh
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@ -40,10 +40,15 @@ localparam IEEE754 = 0;
localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam COUNTERS = 0;
localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;

7
config/rv32imc/config.vh
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@ -40,9 +40,14 @@ localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv64fpquad/config.vh
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@ -41,9 +41,14 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 1;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

7
config/rv64gc/config.vh
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@ -44,9 +44,14 @@ localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12
localparam ZICSR_SUPPORTED = 1;
localparam ZIFENCEI_SUPPORTED = 1;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 1;
localparam ZICNTR_SUPPORTED = 1;
localparam ZIHPM_SUPPORTED = 1;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 1;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 1;

9
config/rv64i/config.vh
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@ -40,10 +40,15 @@ localparam IEEE754 = 0;
localparam MISA = (32'h00000104);
localparam ZICSR_SUPPORTED = 0;
localparam ZIFENCEI_SUPPORTED = 0;
localparam COUNTERS = 12'd32;
localparam ZICOUNTERS_SUPPORTED = 0;
localparam COUNTERS = 0;
localparam ZICNTR_SUPPORTED = 0;
localparam ZIHPM_SUPPORTED = 0;
localparam ZFH_SUPPORTED = 0;
localparam SSTC_SUPPORTED = 0;
localparam ZICBOM_SUPPORTED = 0;
localparam ZICBOZ_SUPPORTED = 0;
localparam ZICBOP_SUPPORTED = 0;
localparam SVPBMT_SUPPORTED = 0;
// LSU microarchitectural Features
localparam BUS_SUPPORTED = 0;

7
config/shared/parameter-defs.vh
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@ -11,7 +11,8 @@ parameter cvw_t P = '{
ZICSR_SUPPORTED : ZICSR_SUPPORTED,
ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED,
COUNTERS : COUNTERS,
ZICOUNTERS_SUPPORTED : ZICOUNTERS_SUPPORTED,
ZICNTR_SUPPORTED : ZICNTR_SUPPORTED,
ZIHPM_SUPPORTED : ZIHPM_SUPPORTED,
ZFH_SUPPORTED : ZFH_SUPPORTED,
SSTC_SUPPORTED : SSTC_SUPPORTED,
VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
@ -19,6 +20,10 @@ parameter cvw_t P = '{
BIGENDIAN_SUPPORTED : BIGENDIAN_SUPPORTED,
SVADU_SUPPORTED : SVADU_SUPPORTED,
ZMMUL_SUPPORTED : ZMMUL_SUPPORTED,
ZICBOM_SUPPORTED : ZICBOM_SUPPORTED,
ZICBOZ_SUPPORTED : ZICBOZ_SUPPORTED,
ZICBOP_SUPPORTED : ZICBOP_SUPPORTED,
SVPBMT_SUPPORTED : SVPBMT_SUPPORTED,
BUS_SUPPORTED : BUS_SUPPORTED,
DCACHE_SUPPORTED : DCACHE_SUPPORTED,
ICACHE_SUPPORTED : ICACHE_SUPPORTED,

60
sim/FPbuild.txt Normal file
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@ -0,0 +1,60 @@
Procedure for Runnning SoftFloat/TestFloat with Wally
1.) First, compile SoftFloat and TestFloat by going to the addins
directory and finding the specific build directory (e.g.,
Linux_x86_64-GCC. Currently, we are using v3e of
SoftFloat/TestFloat. I am not sure of the order, but I always compile
SoftFloat first as I believe TestFloat uses the static library
SoftFloat creates.
2.) Once compiled both, go to the tests/fp directory and run the
create_vectors.sh Linux script. In the past, we have automated this,
but I believe this has fallen into more of a manual state lately.
3.) Then, run remove_spaces.sh which will remove spaces from the
output and put underscores between vectors (this helps differentiate
the vectors that are generated). Again, this can be combined with
Step 2.
4.) TestFloat is run from wally/cvw/sim and sim-testfloat-batch with
its respective test. The format is ./sim-testfloat-add add. All of
the tests are listed below. This can be augmented or added to for
other FP tests given by the great SoftFloat/TestFloat output.
cvtint - test integer conversion unit (fcvtint)
cvtfp - test floating-point conversion unit (fcvtfp)
cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
add - test addition
fma - test fma
mul - test mult with fma
sub - test subtraction
div - test division
sqrt - test square root
all - test everything
4a.) Each test will test all its vectors - if you want to test a
subset of the vectors (e.g., only binary16), you should modify the
cvw/testbench/tests-fp.h and comment out the tests you do not want to
test. The best way to do this is to comment out each item out with
the // comment option in SV. For example,
string f128div[] = '{
// "f128_div_rne.tv",
// "f128_div_rz.tv",
// "f128_div_ru.tv",
// "f128_div_rd.tv",
// "f128_div_rnm.tv"
};

1
src/cache/cache.sv vendored
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@ -182,6 +182,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, W
assign LineWriteData = FetchBuffer;
assign LineByteMask = '1;
end
/////////////////////////////////////////////////////////////////////////////////////////////
// Flush logic
/////////////////////////////////////////////////////////////////////////////////////////////

3
src/cache/cacheLRU.sv vendored
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@ -104,8 +104,7 @@ module cacheLRU
if (node == NUMWAYS-2) begin
assign LRUUpdate[lchild] = ~WayEncoded[r];
assign LRUUpdate[rchild] = WayEncoded[r];
end
else begin
end else begin
assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
end

10
src/cache/cacheway.sv vendored
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@ -84,8 +84,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
// nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
assign FlushWayEn = FlushWay & SelFlush;
assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
end
else begin:flushlogic // no flush operation for read-only caches.
end else begin:flushlogic // no flush operation for read-only caches.
assign SelTag = VictimWay;
assign SelNonHit = SetValid;
end
@ -135,8 +134,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
.we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
end
else begin:wordram // no byte-enable needed for i$.
end else begin:wordram // no byte-enable needed for i$.
ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
@ -175,8 +173,4 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
end
end
end else assign Dirty = 1'b0;
endmodule

5
src/cache/subcachelineread.sv vendored
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@ -43,9 +43,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
if (PADLEN > 0) begin
assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};
end else assign ReadDataLinePad = ReadDataLine;
if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};
else assign ReadDataLinePad = ReadDataLine;
genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux

3
src/ebu/controllerinput.sv
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@ -83,6 +83,3 @@ module controllerinput #(
assign HREADYOut = HREADYIn & ~Disable;
endmodule

4
src/fpu/fcmp.sv
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@ -1,4 +1,3 @@
///////////////////////////////////////////
// fcmp.sv
//
@ -62,7 +61,6 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
assign EitherNaN = XNaN|YNaN;
assign EitherSNaN = XSNaN|YSNaN;
// flags
// Min/Max - if an input is a signaling NaN set invalid flag
// LT/LE - signaling - sets invalid if NaN input
@ -123,7 +121,6 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
else NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
endcase
// Min/Max
// - outputs the min/max of X and Y
// - -0 < 0
@ -154,5 +151,4 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
// - inf = inf and -inf = -inf
// - return 0 if comparison with NaN (unordered)
assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
endmodule

6
src/fpu/fctrl.sv
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@ -232,8 +232,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
logic [1:0] FmtTmp;
assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
assign FmtD = (P.FMT == FmtTmp);
end
else if (P.FPSIZES == 3|P.FPSIZES == 4)
end else if (P.FPSIZES == 3|P.FPSIZES == 4)
assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
// Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
@ -250,12 +249,9 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int
((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
// Z - fma ops only
assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
// Final Res Sel:
// fp int
// 00 other cmp

2
src/fpu/fcvt.sv
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@ -1,4 +1,3 @@
///////////////////////////////////////////
// fcvt.sv
//
@ -222,5 +221,4 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
if(Int64) Cs = Int[P.XLEN-1]&Signed;
else Cs = Int[31]&Signed;
else Cs = Xs;
endmodule

1
src/fpu/fdivsqrt/fdivsqrtcycles.sv
View File

@ -53,6 +53,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
P.FMT: Nf = P.NF;
P.FMT1: Nf = P.NF1;
P.FMT2: Nf = P.NF2;
default: Nf = 'x; // shouldn't happen
endcase
else if (P.FPSIZES == 4)
always_comb

3
src/fpu/fhazard.sv
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@ -56,7 +56,6 @@ module fhazard(
// if the needed value is in the writeback stage
end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
// if the needed value is in the memory stage - input 2
if ((Adr2E == RdM) & FRegWriteM) begin
// if the result will be FResM (can be taken from the memory stage)
@ -64,7 +63,6 @@ module fhazard(
// if the needed value is in the writeback stage
end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
// if the needed value is in the memory stage - input 3
if ((Adr3E == RdM) & FRegWriteM) begin
// if the result will be FResM (can be taken from the memory stage)
@ -72,5 +70,4 @@ module fhazard(
// if the needed value is in the writeback stage
end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
end
endmodule

1
src/fpu/fpu.sv
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@ -262,7 +262,6 @@ module fpu import cvw::*; #(parameter cvw_t P) (
.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
// NaN Box SrcA to convert integer to requested FP size
if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
else if(P.FPSIZES == 2)

1
src/fpu/fregfile.sv
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@ -51,4 +51,3 @@ module fregfile #(parameter FLEN) (
assign #2 rd3 = rf[a3];
endmodule // regfile

1
src/fpu/fsgninj.sv
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@ -73,5 +73,4 @@ module fsgninj import cvw::*; #(parameter cvw_t P) (
endcase
assign SgnRes = {SgnBits[3], X[P.Q_LEN-2:P.D_LEN], SgnBits[2], X[P.D_LEN-2:P.S_LEN], SgnBits[1], X[P.S_LEN-2:P.H_LEN], SgnBits[0], X[P.H_LEN-2:0]};
end
endmodule

2
src/fpu/postproc/cvtshiftcalc.sv
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@ -82,7 +82,7 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) (
P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF);
P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1);
P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2);
default: ResNegNF = 1'bx;
default: ResNegNF = 'x;
endcase
end else if (P.FPSIZES == 4) begin

4
src/fpu/unpackinput.sv
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@ -107,7 +107,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
// is the exponent all 1's
assign ExpMax = Fmt ? &In[P.FLEN-2:P.NF] : &In[P.LEN1-2:P.NF1];
end else if (P.FPSIZES == 3) begin // three floating point precsions supported
// largest format | larger format | smallest format
@ -247,7 +246,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
2'b10: Sgn = In[P.H_LEN-1];
endcase
// extract the fraction
always_comb
case (Fmt)
@ -266,7 +264,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
2'b10: ExpNonZero = |In[P.H_LEN-2:P.H_NF];
endcase
// example double to single conversion:
// 1023 = 0011 1111 1111
// 127 = 0000 0111 1111 (subtract this)
@ -285,7 +282,6 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
2'b10: Exp = {In[P.H_LEN-2], {P.Q_NE-P.H_NE{~In[P.H_LEN-2]}}, In[P.H_LEN-3:P.H_NF+1], In[P.H_NF]|~ExpNonZero};
endcase
// is the exponent all 1's
always_comb
case (Fmt)

2
src/generic/adder.sv
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@ -33,5 +33,3 @@ module adder #(parameter WIDTH=8) (
assign y = a + b;
endmodule

2
src/generic/counter.sv
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@ -36,5 +36,3 @@ module counter #(parameter WIDTH=8) (
assign qnext = q + 1;
flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
endmodule

1
src/generic/neg.sv
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@ -32,4 +32,3 @@ module neg #(parameter WIDTH = 8) (
assign y = ~a + 1;
endmodule

2
src/generic/or_rows.sv
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@ -48,5 +48,3 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
/* verilator lint_on UNOPTFLAT */
end
endmodule

3
src/generic/prioritythermometer.sv
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@ -48,6 +48,3 @@ module prioritythermometer #(parameter N = 8) (
end
/* verilator lint_on UNOPTFLAT */
endmodule

2
src/ieu/ieu.sv
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@ -26,7 +26,6 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module ieu import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
// Decode stage signals
@ -118,4 +117,3 @@ module ieu import cvw::*; #(parameter cvw_t P) (
.FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
endmodule

2
src/ieu/shifter.sv
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@ -84,5 +84,3 @@ module shifter (
assign ZShift = Z >> Offset;
assign Y = ZShift[`XLEN-1:0];
endmodule

112
src/ifu/CodeAligner.py
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@ -1,112 +0,0 @@
import os
# Kevin Wan kewan@hmc.edu 10/27/2021
def read_input(filename): #1
"""Takes in a string filename and outputs the parsed verilog code by line into a list
such that each element of the list is one line of verilog code as a string."""
lineOfCode = []
input_file = open(filename, 'r')
for line in input_file:
lineOfCode.append(line)
return lineOfCode
###################################################################################
def ID_start(GiantString):#2
"""takes in the list of sv file lines, outputs the location that variable names should start"""
VarLoc = 0
VarLineNum = None
for lines in GiantString:
if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
if "[" in lines and "]" in lines:# need to account for these space
NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear.
if NowLoc>VarLoc:
VarLoc = NowLoc
VarLineNum = GiantString.index(lines) # Update this number if new record is made.
else:
NowLoc = lines.find('logic') + 7 # same as before.
if NowLoc>VarLoc:
VarLoc = NowLoc
VarLineNum = GiantString.index(lines)
#print("Furthest variable appears on line", VarLineNum + 1,VarLoc) # Disable this line after debugging.
return VarLoc
##################################################################################
def modified_logNew(GS,SOV): #3
Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it.
Out = []
for l in GS:
lines = l.replace('\t',' ')
if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds.
if "[" in lines and "]" in lines: # the line is an extended declaration.
EditLoc = lines.find("]") # Re-finds the string index number of ].
VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1 # Checks where variable declaration currently is at.
#print(VarLoc,lines[VarLoc])# VERIFIED
NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind)
Out.append(NewLine)# Verified0957 10272021
else:
EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
Out.append(NewLine1)# Verified 1005 10272021
else:
Out.append(lines)
return Out
################################################################################
def write_to_output(filename,GiantString,OW=True,Lines_editted=None): #4
"""Filename is preferrably passed from the early function calls"""
"""GiantString has all the corrected features in the code, each line is a good verilog code line"""
newname = filename
if not OW or OW =='f': #which means no overwrite (create a new file)
Decomposed=filename.split('.')
newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned.
OutFile = open(newname,'w') # This step should create a new file.
OutFile.writelines(GiantString)
OutFile.close()
print("Success! " + newname + " Now contains an aligned file!")
return newname
#################################################################################
def FindCharRel(Ln):
#returns the computer location of a character's first occurence
for num in range(len(Ln)):
if Ln[num] != " ":
return num
def Mod_Space_at(Ln,loc,diff):
#loc is the varLoc from mln, diff is varLoc - Ind
if diff > 0: # to delete
NewString = Ln[:(loc-diff)] + Ln[loc:]
if diff < 0: # to add
NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
if diff == 0:
NewString = Ln
return NewString
'''def main_filehandler(overwrite=False):
for filename in os.listdir():
if ".sv" in filename:
GiantString = read_input(filename)
SOV = ID_start(GiantString)
ModifiedGS = modified_logNew(GiantString,SOV)
Newname = write_to_output(filename,ModifiedGS,overwrite)'''
def root_filehandler(path,overwrite=False):
for f in os.listdir(path):
if os.path.isdir(f):
root_filehandler(path+"/"+f)
else:
if ".sv" in f:
GiantString = read_input(f)
SOV = ID_start(GiantString)
ModifiedGS = modified_logNew(GiantString,SOV)
Newname = write_to_output(f,ModifiedGS,overwrite)
def driver(overwrite=False):
root_filehandler(os.getcwd())
driver(True)

2
src/ifu/bpred/bpred.sv
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@ -191,7 +191,7 @@ module bpred import cvw::*; #(parameter cvw_t P) (
if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
else assign NextValidPCE = PCE;
if(P.ZICOUNTERS_SUPPORTED) begin
if(P.ZIHPM_SUPPORTED) begin
logic [P.XLEN-1:0] RASPCD, RASPCE;
logic BTAWrongE, RASPredPCWrongE;
// performance counters

1
src/ifu/decompress.sv
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@ -181,4 +181,3 @@ module decompress #(parameter XLEN)(
endcase
end
endmodule

7
src/ifu/ifu.sv
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@ -107,7 +107,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
logic [P.XLEN-1:0] PCF; // Fetch stage instruction address
logic [P.PA_BITS-1:0] PCPF; // Physical address after address translation
logic [P.XLEN+1:0] PCFExt; //
logic [P.XLEN+1:0] PCFExt;
logic [31:0] IROMInstrF; // Instruction from the IROM
logic [31:0] ICacheInstrF; // Instruction from the I$
@ -124,7 +124,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic [31:0] InstrE; // Instruction in the Execution stage
logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
logic CacheableF; // PMA indicates instruction address is cacheable
logic SelSpillNextF; // In a spill, stall pipeline and gate local stallF
logic BusStall; // Bus interface busy with multicycle operation
@ -199,6 +198,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
////////////////////////////////////////////////////////////////////////////////////////////////
// Memory
////////////////////////////////////////////////////////////////////////////////////////////////
// CommittedM tells the CPU's privileged unit the current instruction
// in the memory stage is a memory operaton and that memory operation is either completed
// or is partially executed. Partially completed memory operations need to prevent an interrupts.
@ -321,7 +321,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
////////////////////////////////////////////////////////////////////////////////////////////////
// Branch and Jump Predictor
////////////////////////////////////////////////////////////////////////////////////////////////
@ -341,10 +340,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
assign NextValidPCE = PCE;
end
////////////////////////////////////////////////////////////////////////////////////////////////
// Decode stage pipeline register and compressed instruction decoding.
////////////////////////////////////////////////////////////////////////////////////////////////
// Decode stage pipeline register and logic
flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);

2
src/ifu/irom.sv
View File

@ -37,7 +37,6 @@ module irom import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] IROMInstrFFull;
logic [31:0] RawIROMInstrF;
logic [1:0] AdrD;
flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
@ -52,4 +51,3 @@ module irom import cvw::*; #(parameter cvw_t P) (
// The spill logic will handle merging the two together.
assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
endmodule

1
src/ifu/spill.sv
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@ -71,7 +71,6 @@ module spill import cvw::*; #(parameter cvw_t P) (
// select between PCF and PCF+2
mux2 #(P.XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
////////////////////////////////////////////////////////////////////////////////////////////////////
// Detect spill
////////////////////////////////////////////////////////////////////////////////////////////////////

1
src/lsu/amoalu.sv
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@ -72,4 +72,3 @@ module amoalu import cvw::*; #(parameter cvw_t P) (
end
end
endmodule

1
src/lsu/dtim.sv
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@ -52,4 +52,3 @@ module dtim import cvw::*; #(parameter cvw_t P) (
ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN))
ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
endmodule

4
src/lsu/lsu.sv
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@ -132,7 +132,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
logic SelDTIM; // Select DTIM rather than bus or D$
/////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline for IEUAdr E to M
// Zero-extend address to 34 bits for XLEN=32
@ -320,6 +319,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
// Atomic operations
/////////////////////////////////////////////////////////////////////////////////////////////
if (P.A_SUPPORTED) begin:atomic
atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
@ -335,6 +335,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
// Subword Accesses
/////////////////////////////////////////////////////////////////////////////////////////////
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
@ -361,5 +362,4 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign LSUWriteDataM = LittleEndianWriteDataM;
assign LittleEndianReadDataWordM = ReadDataWordMuxM;
end
endmodule

2
src/mdu/mdu.sv
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@ -84,5 +84,3 @@ module mdu import cvw::*; #(parameter cvw_t P) (
// Writeback stage pipeline register
flopenrc #(P.XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);
endmodule // mdu

1
src/mdu/mul.sv
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@ -90,4 +90,3 @@ module mul #(parameter XLEN) (
// add up partial products; this multi-input add implies CSAs and a final CPA
assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
endmodule

1
src/mmu/adrdec.sv
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@ -50,4 +50,3 @@ module adrdec #(parameter PA_BITS) (
// Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok
assign Sel = Match & Supported & AccessValid & SizeValid;
endmodule

1
src/mmu/pmachecker.sv
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@ -70,4 +70,3 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault;
assign PMAStoreAmoAccessFaultM = WriteAccessM & PMAAccessFault;
endmodule

1
src/mmu/pmpadrdec.sv
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@ -87,4 +87,3 @@ module pmpadrdec import cvw::*; #(parameter cvw_t P) (
// attempts an 8-byte access to 0x8, the access should fail (see page 60 of privileged specification 20211203). This
// implementation will not detect the failure.
endmodule

10
src/privileged/csr.sv
View File

@ -123,6 +123,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] TVecAlignedM;
logic InstrValidNotFlushedM;
logic STimerInt;
logic MENVCFG_STCE;
// only valid unflushed instructions can access CSRs
assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
@ -213,7 +214,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
csri #(P) csri(.clk, .reset,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
.MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
.MIDELEG_REGW, .MENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
csrsr #(P) csrsr(.clk, .reset, .StallW,
.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
@ -231,7 +232,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
.MENVCFG_STCE);
if (P.S_SUPPORTED) begin:csrs
@ -242,7 +244,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
.CSRWriteValM, .PrivilegeModeW,
.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
.SCOUNTEREN_REGW,
.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT,
.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .MENVCFG_STCE,
.WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt);
end else begin
assign WriteSSTATUSM = 0;
@ -266,7 +268,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
assign IllegalCSRUAccessM = 1;
end
if (P.ZICOUNTERS_SUPPORTED) begin:counters
if (P.ZICNTR_SUPPORTED) begin:counters
csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,

8
src/privileged/csrc.sv
View File

@ -1,5 +1,3 @@
///////////////////////////////////////////
// csrc.sv
//
@ -92,9 +90,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[0] = 1'b1; // MCYCLE always increments
assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
assign CounterEvent[2] = InstrValidNotFlushedM; // MINSTRET instructions retired
if(P.QEMU) begin: cevent // No other performance counters in QEMU
assign CounterEvent[P.COUNTERS-1:3] = 0;
end else begin: cevent // User-defined counters
if (P.ZIHPM_SUPPORTED) begin: cevent // User-defined counters
assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
@ -121,6 +117,8 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[24] = DivBusyE | FDivBusyE; // division cycles *** RT: might need to be delay until the next cycle
// coverage on
assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
end else begin: cevent
assign CounterEvent[P.COUNTERS-1:3] = 0;
end
// Counter update and write logic

4
src/privileged/csri.sv
View File

@ -34,6 +34,7 @@ module csri import cvw::*; #(parameter cvw_t P) (
input logic [11:0] CSRAdrM,
input logic MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
input logic [11:0] MIDELEG_REGW,
input logic MENVCFG_STCE,
output logic [11:0] MIP_REGW, MIE_REGW,
output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
);
@ -60,7 +61,7 @@ module csri import cvw::*; #(parameter cvw_t P) (
if (P.S_SUPPORTED) begin:mask
if (P.SSTC_SUPPORTED) begin
assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec)
assign STIP = STimerInt;
assign STIP = MENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5];
end else begin
assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
assign STIP = MIP_REGW_writeable[5];
@ -81,7 +82,6 @@ module csri import cvw::*; #(parameter cvw_t P) (
else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields
assign MIP_REGW = {MExtInt, 1'b0, SExtInt|MIP_REGW_writeable[9], 1'b0,
MTimerInt, 1'b0, STIP, 1'b0,
MSwInt, 1'b0, MIP_REGW_writeable[1], 1'b0};

45
src/privileged/csrm.sv
View File

@ -47,14 +47,19 @@ module csrm import cvw::*; #(parameter cvw_t P) (
output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
output logic WriteMSTATUSM, WriteMSTATUSHM,
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM,
output logic MENVCFG_STCE
);
logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW;
logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
logic [63:0] MENVCFG_REGW;
logic [P.XLEN-1:0] MENVCFGH_REGW;
logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
logic WriteMENVCFGM;
// Machine CSRs
localparam MVENDORID = 12'hF11;
@ -69,7 +74,9 @@ module csrm import cvw::*; #(parameter cvw_t P) (
localparam MIE = 12'h304;
localparam MTVEC = 12'h305;
localparam MCOUNTEREN = 12'h306;
localparam MENVCFG = 12'h30A;
localparam MSTATUSH = 12'h310;
localparam MENVCFGH = 12'h31A;
localparam MCOUNTINHIBIT = 12'h320;
localparam MSCRATCH = 12'h340;
localparam MEPC = 12'h341;
@ -140,6 +147,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
@ -161,6 +169,39 @@ module csrm import cvw::*; #(parameter cvw_t P) (
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
end else assign MCOUNTEREN_REGW = '0;
// MENVCFG is always 64 bits even for RV32
assign MENVCFG_WriteValM = {
MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED,
MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED,
54'b0,
MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED,
MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
3'b0,
MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
};
if (P.XLEN == 64) begin
assign MENVCFG_PreWriteValM = CSRWriteValM;
flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW);
assign MENVCFGH_REGW = 0;
end else begin
logic WriteMENVCFGHM;
assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32);
flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]);
flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]);
assign MENVCFGH_REGW = MENVCFG_REGW[63:32];
end
// Extract bit fields
assign MENVCFG_STCE = MENVCFG_REGW[63];
// Uncomment these other fields when they are defined
// assign MENVCFG_PBMTE = MENVCFG_REGW[62];
// assign MENVCFG_CBZE = MENVCFG_REGW[7];
// assign MENVCFG_CBCFE = MENVCFG_REGW[6];
// assign MENVCFG_CBIE = MENVCFG_REGW[5:4];
// assign MENVCFG_FIOM = MENVCFG_REGW[0];
// Read machine mode CSRs
// verilator lint_off WIDTH
logic [5:0] entry;
@ -200,6 +241,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
MTVAL: CSRMReadValM = MTVAL_REGW;
MTINST: CSRMReadValM = 0; // implemented as trivial zero
MCOUNTEREN: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW};
MENVCFG: CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
MENVCFGH: CSRMReadValM = MENVCFGH_REGW;
MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
default: begin

37
src/privileged/csrs.sv
View File

@ -44,6 +44,7 @@ module csrs import cvw::*; #(parameter cvw_t P) (
output logic [P.XLEN-1:0] SATP_REGW,
input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
input logic [63:0] MTIME_CLINT,
input logic MENVCFG_STCE,
output logic WriteSSTATUSM,
output logic IllegalCSRSAccessM,
output logic STimerInt
@ -54,6 +55,7 @@ module csrs import cvw::*; #(parameter cvw_t P) (
localparam SIE = 12'h104;
localparam STVEC = 12'h105;
localparam SCOUNTEREN = 12'h106;
localparam SENVCFG = 12'h10A;
localparam SSCRATCH = 12'h140;
localparam SEPC = 12'h141;
localparam SCAUSE = 12'h142;
@ -70,7 +72,12 @@ module csrs import cvw::*; #(parameter cvw_t P) (
logic WriteSSCRATCHM, WriteSEPCM;
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
logic WriteSTIMECMPM, WriteSTIMECMPHM;
logic WriteSENVCFGM;
logic [P.XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
logic [P.XLEN-1:0] SENVCFG_REGW;
logic [P.XLEN-1:0] SENVCFG_WriteValM;
logic [63:0] STIMECMP_REGW;
// write enables
@ -82,8 +89,9 @@ module csrs import cvw::*; #(parameter cvw_t P) (
assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM);
assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN);
assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM);
assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM) & (P.XLEN == 32);
assign WriteSENVCFGM = CSRSWriteM & (CSRAdrM == SENVCFG);
assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE));
assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE)) & (P.XLEN == 32);
// CSRs
flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW);
@ -112,6 +120,24 @@ module csrs import cvw::*; #(parameter cvw_t P) (
else
assign STimerInt = 0;
assign SENVCFG_WriteValM = {
{(P.XLEN-8){1'b0}},
CSRWriteValM[7] & P.ZICBOZ_SUPPORTED,
CSRWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
3'b0,
CSRWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
};
flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW);
// Extract bit fields
// Uncomment these other fields when they are defined
// assign SENVCFG_PBMTE = SENVCFG_REGW[62];
// assign SENVCFG_CBZE = SENVCFG_REGW[7];
// assign SENVCFG_CBCFE = SENVCFG_REGW[6];
// assign SENVCFG_CBIE = SENVCFG_REGW[5:4];
// assign SENVCFG_FIOM = SENVCFG_REGW[0];
// CSR Reads
always_comb begin:csrr
IllegalCSRSAccessM = 0;
@ -130,12 +156,15 @@ module csrs import cvw::*; #(parameter cvw_t P) (
IllegalCSRSAccessM = 1;
end
SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW};
STIMECMP: if (P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM)) CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0];
SENVCFG: CSRSReadValM = SENVCFG_REGW;
STIMECMP: if (P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE)))
CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0];
else begin
CSRSReadValM = 0;
IllegalCSRSAccessM = 1;
end
STIMECMPH: if (P.SSTC_SUPPORTED & (P.XLEN == 32) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM)) CSRSReadValM[31:0] = STIMECMP_REGW[63:32];
STIMECMPH: if (P.SSTC_SUPPORTED & (P.XLEN == 32) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE)))
CSRSReadValM[31:0] = STIMECMP_REGW[63:32];
else begin // not supported for RV64
CSRSReadValM = 0;
IllegalCSRSAccessM = 1;

2
src/privileged/csrsr.sv
View File

@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Status register
// Purpose: Status register (and environment configuration register and others shared across modes)
// See RISC-V Privileged Mode Specification 20190608
//
// Documentation: RISC-V System on Chip Design Chapter 5

6
src/privileged/privileged.sv
View File

@ -112,7 +112,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
logic ExceptionM; // Memory stage instruction caused a fault
logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
// track the current privilege level
privmode #(P) privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
@ -156,8 +155,3 @@ module privileged import cvw::*; #(parameter cvw_t P) (
.InstrValidM, .CommittedM, .CommittedF,
.TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
endmodule

1
src/uncore/ahbapbbridge.sv
View File

@ -103,4 +103,3 @@ assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before a
// resp logic
assign HRESP = 0; // bridge never indicates errors
endmodule

1
src/uncore/gpio_apb.sv
View File

@ -151,4 +151,3 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) (
assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
endmodule

2
src/uncore/plic_apb.sv
View File

@ -97,6 +97,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
// ==================
// Register Interface
// ==================
always @(posedge PCLK) begin
// resetting
if (~PRESETn) begin
@ -245,4 +246,3 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
endmodule

2
src/uncore/ram_ahb.sv
View File

@ -74,7 +74,6 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1),
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
// use this to add arbitrary latency to ram. Helps test AHB controller correctness
if(`RAM_LATENCY > 0) begin
logic [7:0] NextCycle, Cycle;
@ -110,4 +109,3 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
end
endmodule

1
src/uncore/rom_ahb.sv
View File

@ -48,4 +48,3 @@ module rom_ahb import cvw::*; #(parameter cvw_t P,
rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
endmodule

8
src/uncore/uartPC16550D.sv
View File

@ -122,6 +122,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// Input synchronization: 2-stage synchronizer
///////////////////////////////////////////
always_ff @(posedge PCLK) begin
{SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
{SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} :
@ -132,6 +133,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// Register interface (Table 1, note some are read only and some write only)
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin // Table 3 Reset Configuration
IER <= #1 4'b0;
@ -208,6 +210,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// Ross Thompson: Found a bug. If the baud rate dividers DLM, and DLL are reloaded
// the baudcount is not reset to {DLM, DLL, UART_PRESCALE}
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin
baudcount <= #1 1;
@ -233,6 +236,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// receive timing and control
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin
rxoversampledcnt <= #1 0;
@ -267,6 +271,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// receive shift register, buffer register, FIFO
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit
else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
@ -368,6 +373,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// transmit timing and control
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin
txoversampledcnt <= #1 0;
@ -395,6 +401,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// transmit holding register, shift register, FIFO
///////////////////////////////////////////
always_comb begin // compute value for parity and tx holding register
nexttxdata = fifoenabled ? txfifo[txfifotail] : TXHR; // pick from FIFO or holding register
case (LCR[1:0]) // compute parity from appropriate number of bits
@ -495,6 +502,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// interrupts
///////////////////////////////////////////
assign RXerr = |LSR[4:1]; // LS interrupt if any of the flags are true
assign RXerrIP = RXerr & ~squashRXerrIP; // intr squashed upon reading LSR
assign rxdataavailintr = fifoenabled ? rxfifotriggered : rxdataready;

1
src/uncore/uart_apb.sv
View File

@ -97,4 +97,3 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
);
endmodule

1
src/uncore/uncore.sv
View File

@ -189,4 +189,3 @@ module uncore import cvw::*; #(parameter cvw_t P)(
HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
endmodule

8
src/wally/cvw.sv
View File

@ -48,7 +48,8 @@ typedef struct packed {
logic ZICSR_SUPPORTED;
logic ZIFENCEI_SUPPORTED;
logic [11:0] COUNTERS;
logic ZICOUNTERS_SUPPORTED;
logic ZICNTR_SUPPORTED;
logic ZIHPM_SUPPORTED;
logic ZFH_SUPPORTED;
logic SSTC_SUPPORTED;
logic VIRTMEM_SUPPORTED;
@ -56,6 +57,10 @@ typedef struct packed {
logic BIGENDIAN_SUPPORTED;
logic SVADU_SUPPORTED;
logic ZMMUL_SUPPORTED;
logic ZICBOM_SUPPORTED;
logic ZICBOZ_SUPPORTED;
logic ZICBOP_SUPPORTED;
logic SVPBMT_SUPPORTED;
// Microarchitectural Features
logic BUS_SUPPORTED;
@ -143,7 +148,6 @@ typedef struct packed {
int BPRED_SIZE;
int BTB_SIZE;
// FPU division architecture
int RADIX;
int DIVCOPIES;

12
testbench/common/wallyTracer.sv
View File

@ -139,6 +139,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
CSRArray[12'h30A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW;
CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
@ -157,6 +158,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW;
CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW;
CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW;
CSRArray[12'h10A] = testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW;
CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW;
CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
@ -189,6 +191,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h344] = CSRArrayOld[12'h344];
CSRArray[12'h304] = CSRArrayOld[12'h304];
CSRArray[12'h301] = CSRArrayOld[12'h301];
CSRArray[12'h30A] = CSRArrayOld[12'h30A];
CSRArray[12'hF14] = CSRArrayOld[12'hF14];
CSRArray[12'h340] = CSRArrayOld[12'h340];
CSRArray[12'h342] = CSRArrayOld[12'h342];
@ -207,6 +210,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArray[12'h105] = CSRArrayOld[12'h105];
CSRArray[12'h141] = CSRArrayOld[12'h141];
CSRArray[12'h106] = CSRArrayOld[12'h106];
CSRArray[12'h10A] = CSRArrayOld[12'h10A];
CSRArray[12'h180] = CSRArrayOld[12'h180];
CSRArray[12'h140] = CSRArrayOld[12'h140];
CSRArray[12'h143] = CSRArrayOld[12'h143];
@ -308,6 +312,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArrayOld[12'h344] = CSRArray[12'h344];
CSRArrayOld[12'h304] = CSRArray[12'h304];
CSRArrayOld[12'h301] = CSRArray[12'h301];
CSRArrayOld[12'h30A] = CSRArray[12'h30A];
CSRArrayOld[12'hF14] = CSRArray[12'hF14];
CSRArrayOld[12'h340] = CSRArray[12'h340];
CSRArrayOld[12'h342] = CSRArray[12'h342];
@ -326,6 +331,7 @@ module wallyTracer(rvviTrace rvvi);
CSRArrayOld[12'h105] = CSRArray[12'h105];
CSRArrayOld[12'h141] = CSRArray[12'h141];
CSRArrayOld[12'h106] = CSRArray[12'h106];
CSRArrayOld[12'h10A] = CSRArray[12'h10A];
CSRArrayOld[12'h180] = CSRArray[12'h180];
CSRArrayOld[12'h140] = CSRArray[12'h140];
CSRArrayOld[12'h143] = CSRArray[12'h143];
@ -352,6 +358,7 @@ module wallyTracer(rvviTrace rvvi);
assign #2 CSR_W[12'h305] = (CSRArrayOld[12'h305] != CSRArray[12'h305]) ? 1 : 0;
assign #2 CSR_W[12'h341] = (CSRArrayOld[12'h341] != CSRArray[12'h341]) ? 1 : 0;
assign #2 CSR_W[12'h306] = (CSRArrayOld[12'h306] != CSRArray[12'h306]) ? 1 : 0;
assign #2 CSR_W[12'h30A] = (CSRArrayOld[12'h30A] != CSRArray[12'h30A]) ? 1 : 0;
assign #2 CSR_W[12'h320] = (CSRArrayOld[12'h320] != CSRArray[12'h320]) ? 1 : 0;
assign #2 CSR_W[12'h302] = (CSRArrayOld[12'h302] != CSRArray[12'h302]) ? 1 : 0;
assign #2 CSR_W[12'h303] = (CSRArrayOld[12'h303] != CSRArray[12'h303]) ? 1 : 0;
@ -374,6 +381,7 @@ module wallyTracer(rvviTrace rvvi);
assign #2 CSR_W[12'h105] = (CSRArrayOld[12'h105] != CSRArray[12'h105]) ? 1 : 0;
assign #2 CSR_W[12'h141] = (CSRArrayOld[12'h141] != CSRArray[12'h141]) ? 1 : 0;
assign #2 CSR_W[12'h106] = (CSRArrayOld[12'h106] != CSRArray[12'h106]) ? 1 : 0;
assign #2 CSR_W[12'h10A] = (CSRArrayOld[12'h10A] != CSRArray[12'h10A]) ? 1 : 0;
assign #2 CSR_W[12'h180] = (CSRArrayOld[12'h180] != CSRArray[12'h180]) ? 1 : 0;
assign #2 CSR_W[12'h140] = (CSRArrayOld[12'h140] != CSRArray[12'h140]) ? 1 : 0;
assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
@ -394,6 +402,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr_wb[0][0][12'h303] = CSR_W[12'h303];
assign rvvi.csr_wb[0][0][12'h344] = CSR_W[12'h344];
assign rvvi.csr_wb[0][0][12'h304] = CSR_W[12'h304];
assign rvvi.csr_wb[0][0][12'h30A] = CSR_W[12'h30A];
assign rvvi.csr_wb[0][0][12'h301] = CSR_W[12'h301];
assign rvvi.csr_wb[0][0][12'hF14] = CSR_W[12'hF14];
assign rvvi.csr_wb[0][0][12'h340] = CSR_W[12'h340];
@ -411,6 +420,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr_wb[0][0][12'h105] = CSR_W[12'h105];
assign rvvi.csr_wb[0][0][12'h141] = CSR_W[12'h141];
assign rvvi.csr_wb[0][0][12'h106] = CSR_W[12'h106];
assign rvvi.csr_wb[0][0][12'h10A] = CSR_W[12'h10A];
assign rvvi.csr_wb[0][0][12'h180] = CSR_W[12'h180];
assign rvvi.csr_wb[0][0][12'h140] = CSR_W[12'h140];
assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
@ -431,6 +441,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr[0][0][12'h303] = CSRArray[12'h303];
assign rvvi.csr[0][0][12'h344] = CSRArray[12'h344];
assign rvvi.csr[0][0][12'h304] = CSRArray[12'h304];
assign rvvi.csr[0][0][12'h30A] = CSRArray[12'h30A];
assign rvvi.csr[0][0][12'h301] = CSRArray[12'h301];
assign rvvi.csr[0][0][12'hF14] = CSRArray[12'hF14];
assign rvvi.csr[0][0][12'h340] = CSRArray[12'h340];
@ -448,6 +459,7 @@ module wallyTracer(rvviTrace rvvi);
assign rvvi.csr[0][0][12'h105] = CSRArray[12'h105];
assign rvvi.csr[0][0][12'h141] = CSRArray[12'h141];
assign rvvi.csr[0][0][12'h106] = CSRArray[12'h106];
assign rvvi.csr[0][0][12'h10A] = CSRArray[12'h10A];
assign rvvi.csr[0][0][12'h180] = CSRArray[12'h180];
assign rvvi.csr[0][0][12'h140] = CSRArray[12'h140];
assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143];

16
testbench/testbench-fp.sv
View File

@ -113,8 +113,6 @@ module testbenchfp;
`include "parameter-defs.vh"
///////////////////////////////////////////////////////////////////////////////////////////////
// ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| |||
@ -699,13 +697,13 @@ module testbenchfp;
.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal),
fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal),
.XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
.Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
end
if (TEST === "cmp" | TEST === "all") begin: fcmp
fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye,
fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye,
.Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
.XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
end
@ -892,13 +890,13 @@ always @(negedge clk) begin
// check if result is correct
// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
assign divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
assign DivDone = OldFDivBusyE & ~FDivBusyE;
//assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL;
CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
assign CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
if(~(ResMatch & FlagMatch) & CheckNow) begin
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
errors += 1;
@ -986,6 +984,7 @@ module readvectors (
output logic DivStart,
output logic [`FLEN-1:0] X, Y, Z, XPostBox
);
logic XEn, YEn, ZEn;
`include "parameter-defs.vh"
@ -1346,7 +1345,6 @@ module readvectors (
assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
assign ZEn = (Unit == `FMAUNIT);
unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,

2
testbench/testbench-linux-imperas.sv
View File

@ -866,10 +866,12 @@ module testbench;
"medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW)
"mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW)
"mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW)
"menvcfg": `checkCSR(`CSR_BASE.csrm.MENVCFG_REGW)
"sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW)
"scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
"stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
"senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW)
"mip": begin
`checkCSR(`CSR_BASE.csrm.MIP_REGW)
if(!NO_SPOOFING) begin

3
tests/coverage/csrwrites.S
View File

@ -33,5 +33,8 @@ main:
csrrw t0, satp, zero
csrrw t0, stvec, zero
csrrw t0, sscratch, zero
li t0, -2
csrrw t1, menvcfg, t0
csrrw t2, senvcfg, t0
j done

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -1,3 +1,5 @@
FFFFFFFF # stimecmp readback
80000000 # menvcfg readback
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0)

7
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
View File

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I_Zicsr")
RVTEST_ISA("RV32I_Sstc_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap)
INIT_TESTS
@ -34,8 +34,9 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
WRITE_READ_CSR menvcfgh, 0x80000000 // Enable menvcfg.STCE
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// test 5.3.1.4 Basic trap tests
// instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -1,3 +1,7 @@
FFFFFFFF # stimecmp low bits
00000000 # stimecmp high bits
00000000 # menvcfg low bits
80000000 # menvcfg high bits
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
00000001 # mcause from an instruction access fault

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
View File

@ -22,7 +22,7 @@
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr")
RVTEST_ISA("RV64I_Sstc_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap)
INIT_TESTS
@ -33,6 +33,8 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
WRITE_READ_CSR menvcfg, 0x8000000000000000 // Enable menvcfg.STCE
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
// test 5.3.1.4 Basic trap tests