diff --git a/pipelined/src/fpu/adderparts.sv b/pipelined/src/fpu/adderparts.sv deleted file mode 100644 index 045a8accc..000000000 --- a/pipelined/src/fpu/adderparts.sv +++ /dev/null @@ -1,758 +0,0 @@ -// The following module make up the basic building blocks that -// are used by the cla64, cla_sub64, and cla52. - -module INVBLOCK ( GIN, GOUT ); - - input GIN; - output GOUT; - - assign GOUT = ~ GIN; - -endmodule // INVBLOCK - - -module XXOR1 ( A, B, GIN, SUM ); - - input A; - input B; - input GIN; - output SUM; - - assign SUM = ( ~ (A ^ B)) ^ GIN; - -endmodule // XXOR1 - - -module BLOCK0 ( A, B, POUT, GOUT ); - - input A; - input B; - output POUT; - output GOUT; - - assign POUT = ~ (A | B); - assign GOUT = ~ (A & B); - -endmodule // BLOCK0 - - -module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 | PIN2); - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1 - - -module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 & PIN2); - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule // BLOCK2 - - -module BLOCK1A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1A - - -module BLOCK2A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule -//***KEP all 0:63, 0:64 ect changed - changed due to lint warning -module PRESTAGE_64 ( A, B, CIN, POUT, GOUT ); - - input [63:0] A; - input [63:0] B; - input CIN; - - output [63:0] POUT; - output [64:0] GOUT; - - BLOCK0 U10 (A[0] , B[0] , POUT[0] , GOUT[1] ); - BLOCK0 U11 (A[1] , B[1] , POUT[1] , GOUT[2] ); - BLOCK0 U12 (A[2] , B[2] , POUT[2] , GOUT[3] ); - BLOCK0 U13 (A[3] , B[3] , POUT[3] , GOUT[4] ); - BLOCK0 U14 (A[4] , B[4] , POUT[4] , GOUT[5] ); - BLOCK0 U15 (A[5] , B[5] , POUT[5] , GOUT[6] ); - BLOCK0 U16 (A[6] , B[6] , POUT[6] , GOUT[7] ); - BLOCK0 U17 (A[7] , B[7] , POUT[7] , GOUT[8] ); - BLOCK0 U18 (A[8] , B[8] , POUT[8] , GOUT[9] ); - BLOCK0 U19 (A[9] , B[9] , POUT[9] , GOUT[10] ); - BLOCK0 U110 (A[10] , B[10] , POUT[10] , GOUT[11] ); - BLOCK0 U111 (A[11] , B[11] , POUT[11] , GOUT[12] ); - BLOCK0 U112 (A[12] , B[12] , POUT[12] , GOUT[13] ); - BLOCK0 U113 (A[13] , B[13] , POUT[13] , GOUT[14] ); - BLOCK0 U114 (A[14] , B[14] , POUT[14] , GOUT[15] ); - BLOCK0 U115 (A[15] , B[15] , POUT[15] , GOUT[16] ); - BLOCK0 U116 (A[16] , B[16] , POUT[16] , GOUT[17] ); - BLOCK0 U117 (A[17] , B[17] , POUT[17] , GOUT[18] ); - BLOCK0 U118 (A[18] , B[18] , POUT[18] , GOUT[19] ); - BLOCK0 U119 (A[19] , B[19] , POUT[19] , GOUT[20] ); - BLOCK0 U120 (A[20] , B[20] , POUT[20] , GOUT[21] ); - BLOCK0 U121 (A[21] , B[21] , POUT[21] , GOUT[22] ); - BLOCK0 U122 (A[22] , B[22] , POUT[22] , GOUT[23] ); - BLOCK0 U123 (A[23] , B[23] , POUT[23] , GOUT[24] ); - BLOCK0 U124 (A[24] , B[24] , POUT[24] , GOUT[25] ); - BLOCK0 U125 (A[25] , B[25] , POUT[25] , GOUT[26] ); - BLOCK0 U126 (A[26] , B[26] , POUT[26] , GOUT[27] ); - BLOCK0 U127 (A[27] , B[27] , POUT[27] , GOUT[28] ); - BLOCK0 U128 (A[28] , B[28] , POUT[28] , GOUT[29] ); - BLOCK0 U129 (A[29] , B[29] , POUT[29] , GOUT[30] ); - BLOCK0 U130 (A[30] , B[30] , POUT[30] , GOUT[31] ); - BLOCK0 U131 (A[31] , B[31] , POUT[31] , GOUT[32] ); - BLOCK0 U132 (A[32] , B[32] , POUT[32] , GOUT[33] ); - BLOCK0 U133 (A[33] , B[33] , POUT[33] , GOUT[34] ); - BLOCK0 U134 (A[34] , B[34] , POUT[34] , GOUT[35] ); - BLOCK0 U135 (A[35] , B[35] , POUT[35] , GOUT[36] ); - BLOCK0 U136 (A[36] , B[36] , POUT[36] , GOUT[37] ); - BLOCK0 U137 (A[37] , B[37] , POUT[37] , GOUT[38] ); - BLOCK0 U138 (A[38] , B[38] , POUT[38] , GOUT[39] ); - BLOCK0 U139 (A[39] , B[39] , POUT[39] , GOUT[40] ); - BLOCK0 U140 (A[40] , B[40] , POUT[40] , GOUT[41] ); - BLOCK0 U141 (A[41] , B[41] , POUT[41] , GOUT[42] ); - BLOCK0 U142 (A[42] , B[42] , POUT[42] , GOUT[43] ); - BLOCK0 U143 (A[43] , B[43] , POUT[43] , GOUT[44] ); - BLOCK0 U144 (A[44] , B[44] , POUT[44] , GOUT[45] ); - BLOCK0 U145 (A[45] , B[45] , POUT[45] , GOUT[46] ); - BLOCK0 U146 (A[46] , B[46] , POUT[46] , GOUT[47] ); - BLOCK0 U147 (A[47] , B[47] , POUT[47] , GOUT[48] ); - BLOCK0 U148 (A[48] , B[48] , POUT[48] , GOUT[49] ); - BLOCK0 U149 (A[49] , B[49] , POUT[49] , GOUT[50] ); - BLOCK0 U150 (A[50] , B[50] , POUT[50] , GOUT[51] ); - BLOCK0 U151 (A[51] , B[51] , POUT[51] , GOUT[52] ); - BLOCK0 U152 (A[52] , B[52] , POUT[52] , GOUT[53] ); - BLOCK0 U153 (A[53] , B[53] , POUT[53] , GOUT[54] ); - BLOCK0 U154 (A[54] , B[54] , POUT[54] , GOUT[55] ); - BLOCK0 U155 (A[55] , B[55] , POUT[55] , GOUT[56] ); - BLOCK0 U156 (A[56] , B[56] , POUT[56] , GOUT[57] ); - BLOCK0 U157 (A[57] , B[57] , POUT[57] , GOUT[58] ); - BLOCK0 U158 (A[58] , B[58] , POUT[58] , GOUT[59] ); - BLOCK0 U159 (A[59] , B[59] , POUT[59] , GOUT[60] ); - BLOCK0 U160 (A[60] , B[60] , POUT[60] , GOUT[61] ); - BLOCK0 U161 (A[61] , B[61] , POUT[61] , GOUT[62] ); - BLOCK0 U162 (A[62] , B[62] , POUT[62] , GOUT[63] ); - BLOCK0 U163 (A[63] , B[63] , POUT[63] , GOUT[64] ); - INVBLOCK U2 (CIN , GOUT[0] ); - -endmodule // PRESTAGE_64 - - -module DBLC_0_64 ( PIN, GIN, POUT, GOUT ); - - input [63:0] PIN; - input [64:0] GIN; - - output [62:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , GOUT[1] ); - BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , POUT[0] , GOUT[2] ); - BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , POUT[1] , GOUT[3] ); - BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , POUT[2] , GOUT[4] ); - BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , POUT[3] , GOUT[5] ); - BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , POUT[4] , GOUT[6] ); - BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , POUT[5] , GOUT[7] ); - BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , POUT[6] , GOUT[8] ); - BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , POUT[7] , GOUT[9] ); - BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , POUT[8] , GOUT[10] ); - BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , POUT[9] , GOUT[11] ); - BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , POUT[10] , GOUT[12] ); - BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , POUT[11] , GOUT[13] ); - BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , POUT[12] , GOUT[14] ); - BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , POUT[13] , GOUT[15] ); - BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , POUT[14] , GOUT[16] ); - BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , POUT[15] , GOUT[17] ); - BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , POUT[16] , GOUT[18] ); - BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , POUT[17] , GOUT[19] ); - BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , POUT[18] , GOUT[20] ); - BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , POUT[19] , GOUT[21] ); - BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , POUT[20] , GOUT[22] ); - BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , POUT[21] , GOUT[23] ); - BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , POUT[22] , GOUT[24] ); - BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , POUT[23] , GOUT[25] ); - BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , POUT[24] , GOUT[26] ); - BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , POUT[25] , GOUT[27] ); - BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , POUT[26] , GOUT[28] ); - BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , POUT[27] , GOUT[29] ); - BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , POUT[28] , GOUT[30] ); - BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , POUT[29] , GOUT[31] ); - BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , POUT[30] , GOUT[32] ); - BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , POUT[31] , GOUT[33] ); - BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , POUT[32] , GOUT[34] ); - BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , POUT[33] , GOUT[35] ); - BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , POUT[34] , GOUT[36] ); - BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , POUT[35] , GOUT[37] ); - BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , POUT[36] , GOUT[38] ); - BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , POUT[37] , GOUT[39] ); - BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , POUT[38] , GOUT[40] ); - BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , POUT[39] , GOUT[41] ); - BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , POUT[40] , GOUT[42] ); - BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , POUT[41] , GOUT[43] ); - BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , POUT[42] , GOUT[44] ); - BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , POUT[43] , GOUT[45] ); - BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , POUT[44] , GOUT[46] ); - BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , POUT[45] , GOUT[47] ); - BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , POUT[46] , GOUT[48] ); - BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , POUT[47] , GOUT[49] ); - BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , POUT[48] , GOUT[50] ); - BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , POUT[49] , GOUT[51] ); - BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , POUT[50] , GOUT[52] ); - BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , POUT[51] , GOUT[53] ); - BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , POUT[52] , GOUT[54] ); - BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , POUT[53] , GOUT[55] ); - BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , POUT[54] , GOUT[56] ); - BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , POUT[55] , GOUT[57] ); - BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , POUT[56] , GOUT[58] ); - BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , POUT[57] , GOUT[59] ); - BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , POUT[58] , GOUT[60] ); - BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , POUT[59] , GOUT[61] ); - BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , POUT[60] , GOUT[62] ); - BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , POUT[61] , GOUT[63] ); - BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , POUT[62] , GOUT[64] ); - -endmodule // DBLC_0_64 - - -module DBLC_1_64 ( PIN, GIN, POUT, GOUT ); - - input [62:0] PIN; - input [64:0] GIN; - - output [60:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , GOUT[2] ); - BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , GOUT[3] ); - BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , POUT[0] , GOUT[4] ); - BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , POUT[1] , GOUT[5] ); - BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , POUT[2] , GOUT[6] ); - BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , POUT[3] , GOUT[7] ); - BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , POUT[4] , GOUT[8] ); - BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , POUT[5] , GOUT[9] ); - BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , POUT[6] , GOUT[10] ); - BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , POUT[7] , GOUT[11] ); - BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , POUT[8] , GOUT[12] ); - BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , POUT[9] , GOUT[13] ); - BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , POUT[10] , GOUT[14] ); - BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , POUT[11] , GOUT[15] ); - BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , POUT[12] , GOUT[16] ); - BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , POUT[13] , GOUT[17] ); - BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , POUT[14] , GOUT[18] ); - BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , POUT[15] , GOUT[19] ); - BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , POUT[16] , GOUT[20] ); - BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , POUT[17] , GOUT[21] ); - BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , POUT[18] , GOUT[22] ); - BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , POUT[19] , GOUT[23] ); - BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , POUT[20] , GOUT[24] ); - BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , POUT[21] , GOUT[25] ); - BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , POUT[22] , GOUT[26] ); - BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , POUT[23] , GOUT[27] ); - BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , POUT[24] , GOUT[28] ); - BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , POUT[25] , GOUT[29] ); - BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , POUT[26] , GOUT[30] ); - BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , POUT[27] , GOUT[31] ); - BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , POUT[28] , GOUT[32] ); - BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , POUT[29] , GOUT[33] ); - BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , POUT[30] , GOUT[34] ); - BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , POUT[31] , GOUT[35] ); - BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , POUT[32] , GOUT[36] ); - BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , POUT[33] , GOUT[37] ); - BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , POUT[34] , GOUT[38] ); - BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , POUT[35] , GOUT[39] ); - BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , POUT[36] , GOUT[40] ); - BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , POUT[37] , GOUT[41] ); - BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , POUT[38] , GOUT[42] ); - BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , POUT[39] , GOUT[43] ); - BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , POUT[40] , GOUT[44] ); - BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , POUT[41] , GOUT[45] ); - BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , POUT[42] , GOUT[46] ); - BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , POUT[43] , GOUT[47] ); - BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , POUT[44] , GOUT[48] ); - BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , POUT[45] , GOUT[49] ); - BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , POUT[46] , GOUT[50] ); - BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , POUT[47] , GOUT[51] ); - BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , POUT[48] , GOUT[52] ); - BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , POUT[49] , GOUT[53] ); - BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , POUT[50] , GOUT[54] ); - BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , POUT[51] , GOUT[55] ); - BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , POUT[52] , GOUT[56] ); - BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , POUT[53] , GOUT[57] ); - BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , POUT[54] , GOUT[58] ); - BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , POUT[55] , GOUT[59] ); - BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , POUT[56] , GOUT[60] ); - BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , POUT[57] , GOUT[61] ); - BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , POUT[58] , GOUT[62] ); - BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , POUT[59] , GOUT[63] ); - BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , POUT[60] , GOUT[64] ); - -endmodule // DBLC_1_64 - - -module DBLC_2_64 ( PIN, GIN, POUT, GOUT ); - - input [60:0] PIN; - input [64:0] GIN; - - output [56:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , GOUT[4] ); - BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , GOUT[5] ); - BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , GOUT[6] ); - BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , GOUT[7] ); - BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , POUT[0] , GOUT[8] ); - BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , POUT[1] , GOUT[9] ); - BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , POUT[2] , GOUT[10] ); - BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , POUT[3] , GOUT[11] ); - BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , POUT[4] , GOUT[12] ); - BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , POUT[5] , GOUT[13] ); - BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , POUT[6] , GOUT[14] ); - BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , POUT[7] , GOUT[15] ); - BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , POUT[8] , GOUT[16] ); - BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , POUT[9] , GOUT[17] ); - BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , POUT[10] , GOUT[18] ); - BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , POUT[11] , GOUT[19] ); - BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , POUT[12] , GOUT[20] ); - BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , POUT[13] , GOUT[21] ); - BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , POUT[14] , GOUT[22] ); - BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , POUT[15] , GOUT[23] ); - BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , POUT[16] , GOUT[24] ); - BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , POUT[17] , GOUT[25] ); - BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , POUT[18] , GOUT[26] ); - BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , POUT[19] , GOUT[27] ); - BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , POUT[20] , GOUT[28] ); - BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , POUT[21] , GOUT[29] ); - BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , POUT[22] , GOUT[30] ); - BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , POUT[23] , GOUT[31] ); - BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , POUT[24] , GOUT[32] ); - BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , POUT[25] , GOUT[33] ); - BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , POUT[26] , GOUT[34] ); - BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , POUT[27] , GOUT[35] ); - BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , POUT[28] , GOUT[36] ); - BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , POUT[29] , GOUT[37] ); - BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , POUT[30] , GOUT[38] ); - BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , POUT[31] , GOUT[39] ); - BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , POUT[32] , GOUT[40] ); - BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , POUT[33] , GOUT[41] ); - BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , POUT[34] , GOUT[42] ); - BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , POUT[35] , GOUT[43] ); - BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , POUT[36] , GOUT[44] ); - BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , POUT[37] , GOUT[45] ); - BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , POUT[38] , GOUT[46] ); - BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , POUT[39] , GOUT[47] ); - BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , POUT[40] , GOUT[48] ); - BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , POUT[41] , GOUT[49] ); - BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , POUT[42] , GOUT[50] ); - BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , POUT[43] , GOUT[51] ); - BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , POUT[44] , GOUT[52] ); - BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , POUT[45] , GOUT[53] ); - BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , POUT[46] , GOUT[54] ); - BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , POUT[47] , GOUT[55] ); - BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , POUT[48] , GOUT[56] ); - BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , POUT[49] , GOUT[57] ); - BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , POUT[50] , GOUT[58] ); - BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , POUT[51] , GOUT[59] ); - BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , POUT[52] , GOUT[60] ); - BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , POUT[53] , GOUT[61] ); - BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , POUT[54] , GOUT[62] ); - BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , POUT[55] , GOUT[63] ); - BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , POUT[56] , GOUT[64] ); - -endmodule // DBLC_2_64 - - -module DBLC_3_64 ( PIN, GIN, POUT, GOUT ); - - input [56:0] PIN; - input [64:0] GIN; - - output [48:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , GOUT[8] ); - BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , GOUT[9] ); - BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , GOUT[10] ); - BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , GOUT[11] ); - BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , GOUT[12] ); - BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , GOUT[13] ); - BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , GOUT[14] ); - BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , GOUT[15] ); - BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , POUT[0] , GOUT[16] ); - BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , POUT[1] , GOUT[17] ); - BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , POUT[2] , GOUT[18] ); - BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , POUT[3] , GOUT[19] ); - BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , POUT[4] , GOUT[20] ); - BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , POUT[5] , GOUT[21] ); - BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , POUT[6] , GOUT[22] ); - BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , POUT[7] , GOUT[23] ); - BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , POUT[8] , GOUT[24] ); - BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , POUT[9] , GOUT[25] ); - BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , POUT[10] , GOUT[26] ); - BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , POUT[11] , GOUT[27] ); - BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , POUT[12] , GOUT[28] ); - BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , POUT[13] , GOUT[29] ); - BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , POUT[14] , GOUT[30] ); - BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , POUT[15] , GOUT[31] ); - BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , POUT[16] , GOUT[32] ); - BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , POUT[17] , GOUT[33] ); - BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , POUT[18] , GOUT[34] ); - BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , POUT[19] , GOUT[35] ); - BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , POUT[20] , GOUT[36] ); - BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , POUT[21] , GOUT[37] ); - BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , POUT[22] , GOUT[38] ); - BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , POUT[23] , GOUT[39] ); - BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , POUT[24] , GOUT[40] ); - BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , POUT[25] , GOUT[41] ); - BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , POUT[26] , GOUT[42] ); - BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , POUT[27] , GOUT[43] ); - BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , POUT[28] , GOUT[44] ); - BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , POUT[29] , GOUT[45] ); - BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , POUT[30] , GOUT[46] ); - BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , POUT[31] , GOUT[47] ); - BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , POUT[32] , GOUT[48] ); - BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , POUT[33] , GOUT[49] ); - BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , POUT[34] , GOUT[50] ); - BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , POUT[35] , GOUT[51] ); - BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , POUT[36] , GOUT[52] ); - BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , POUT[37] , GOUT[53] ); - BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , POUT[38] , GOUT[54] ); - BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , POUT[39] , GOUT[55] ); - BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , POUT[40] , GOUT[56] ); - BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , POUT[41] , GOUT[57] ); - BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , POUT[42] , GOUT[58] ); - BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , POUT[43] , GOUT[59] ); - BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , POUT[44] , GOUT[60] ); - BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , POUT[45] , GOUT[61] ); - BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , POUT[46] , GOUT[62] ); - BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , POUT[47] , GOUT[63] ); - BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , POUT[48] , GOUT[64] ); - -endmodule // DBLC_3_64 - - -module DBLC_4_64 ( PIN, GIN, POUT, GOUT ); - - input [48:0] PIN; - input [64:0] GIN; - - output [32:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , GOUT[16] ); - BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , GOUT[17] ); - BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , GOUT[18] ); - BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , GOUT[19] ); - BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , GOUT[20] ); - BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , GOUT[21] ); - BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , GOUT[22] ); - BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , GOUT[23] ); - BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , GOUT[24] ); - BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , GOUT[25] ); - BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , GOUT[26] ); - BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , GOUT[27] ); - BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , GOUT[28] ); - BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , GOUT[29] ); - BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , GOUT[30] ); - BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , GOUT[31] ); - BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , POUT[0] , GOUT[32] ); - BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , POUT[1] , GOUT[33] ); - BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , POUT[2] , GOUT[34] ); - BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , POUT[3] , GOUT[35] ); - BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , POUT[4] , GOUT[36] ); - BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , POUT[5] , GOUT[37] ); - BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , POUT[6] , GOUT[38] ); - BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , POUT[7] , GOUT[39] ); - BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , POUT[8] , GOUT[40] ); - BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , POUT[9] , GOUT[41] ); - BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , POUT[10] , GOUT[42] ); - BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , POUT[11] , GOUT[43] ); - BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , POUT[12] , GOUT[44] ); - BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , POUT[13] , GOUT[45] ); - BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , POUT[14] , GOUT[46] ); - BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , POUT[15] , GOUT[47] ); - BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , POUT[16] , GOUT[48] ); - BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , POUT[17] , GOUT[49] ); - BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , POUT[18] , GOUT[50] ); - BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , POUT[19] , GOUT[51] ); - BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , POUT[20] , GOUT[52] ); - BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , POUT[21] , GOUT[53] ); - BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , POUT[22] , GOUT[54] ); - BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , POUT[23] , GOUT[55] ); - BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , POUT[24] , GOUT[56] ); - BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , POUT[25] , GOUT[57] ); - BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , POUT[26] , GOUT[58] ); - BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , POUT[27] , GOUT[59] ); - BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , POUT[28] , GOUT[60] ); - BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , POUT[29] , GOUT[61] ); - BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , POUT[30] , GOUT[62] ); - BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , POUT[31] , GOUT[63] ); - BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , POUT[32] , GOUT[64] ); - -endmodule // DBLC_4_64 - - -module DBLC_5_64 ( PIN, GIN, POUT, GOUT ); - - input [32:0] PIN; - input [64:0] GIN; - - output [0:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - INVBLOCK U116 (GIN[16] , GOUT[16] ); - INVBLOCK U117 (GIN[17] , GOUT[17] ); - INVBLOCK U118 (GIN[18] , GOUT[18] ); - INVBLOCK U119 (GIN[19] , GOUT[19] ); - INVBLOCK U120 (GIN[20] , GOUT[20] ); - INVBLOCK U121 (GIN[21] , GOUT[21] ); - INVBLOCK U122 (GIN[22] , GOUT[22] ); - INVBLOCK U123 (GIN[23] , GOUT[23] ); - INVBLOCK U124 (GIN[24] , GOUT[24] ); - INVBLOCK U125 (GIN[25] , GOUT[25] ); - INVBLOCK U126 (GIN[26] , GOUT[26] ); - INVBLOCK U127 (GIN[27] , GOUT[27] ); - INVBLOCK U128 (GIN[28] , GOUT[28] ); - INVBLOCK U129 (GIN[29] , GOUT[29] ); - INVBLOCK U130 (GIN[30] , GOUT[30] ); - INVBLOCK U131 (GIN[31] , GOUT[31] ); - BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , GOUT[32] ); - BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , GOUT[33] ); - BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , GOUT[34] ); - BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , GOUT[35] ); - BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , GOUT[36] ); - BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , GOUT[37] ); - BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , GOUT[38] ); - BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , GOUT[39] ); - BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , GOUT[40] ); - BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , GOUT[41] ); - BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , GOUT[42] ); - BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , GOUT[43] ); - BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , GOUT[44] ); - BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , GOUT[45] ); - BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , GOUT[46] ); - BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , GOUT[47] ); - BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , GOUT[48] ); - BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , GOUT[49] ); - BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , GOUT[50] ); - BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , GOUT[51] ); - BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , GOUT[52] ); - BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , GOUT[53] ); - BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , GOUT[54] ); - BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , GOUT[55] ); - BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , GOUT[56] ); - BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , GOUT[57] ); - BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , GOUT[58] ); - BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , GOUT[59] ); - BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , GOUT[60] ); - BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , GOUT[61] ); - BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , GOUT[62] ); - BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , GOUT[63] ); - BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , POUT[0] , GOUT[64] ); - -endmodule // DBLC_5_64 - - -module XORSTAGE_64 ( A, B, PBIT, CARRY, SUM, COUT ); - - input [63:0] A; - input [63:0] B; - input PBIT; - input [64:0] CARRY; - - output [63:0] SUM; - output COUT; - - XXOR1 U20 (A[0] , B[0] , CARRY[0] , SUM[0] ); - XXOR1 U21 (A[1] , B[1] , CARRY[1] , SUM[1] ); - XXOR1 U22 (A[2] , B[2] , CARRY[2] , SUM[2] ); - XXOR1 U23 (A[3] , B[3] , CARRY[3] , SUM[3] ); - XXOR1 U24 (A[4] , B[4] , CARRY[4] , SUM[4] ); - XXOR1 U25 (A[5] , B[5] , CARRY[5] , SUM[5] ); - XXOR1 U26 (A[6] , B[6] , CARRY[6] , SUM[6] ); - XXOR1 U27 (A[7] , B[7] , CARRY[7] , SUM[7] ); - XXOR1 U28 (A[8] , B[8] , CARRY[8] , SUM[8] ); - XXOR1 U29 (A[9] , B[9] , CARRY[9] , SUM[9] ); - XXOR1 U210 (A[10] , B[10] , CARRY[10] , SUM[10] ); - XXOR1 U211 (A[11] , B[11] , CARRY[11] , SUM[11] ); - XXOR1 U212 (A[12] , B[12] , CARRY[12] , SUM[12] ); - XXOR1 U213 (A[13] , B[13] , CARRY[13] , SUM[13] ); - XXOR1 U214 (A[14] , B[14] , CARRY[14] , SUM[14] ); - XXOR1 U215 (A[15] , B[15] , CARRY[15] , SUM[15] ); - XXOR1 U216 (A[16] , B[16] , CARRY[16] , SUM[16] ); - XXOR1 U217 (A[17] , B[17] , CARRY[17] , SUM[17] ); - XXOR1 U218 (A[18] , B[18] , CARRY[18] , SUM[18] ); - XXOR1 U219 (A[19] , B[19] , CARRY[19] , SUM[19] ); - XXOR1 U220 (A[20] , B[20] , CARRY[20] , SUM[20] ); - XXOR1 U221 (A[21] , B[21] , CARRY[21] , SUM[21] ); - XXOR1 U222 (A[22] , B[22] , CARRY[22] , SUM[22] ); - XXOR1 U223 (A[23] , B[23] , CARRY[23] , SUM[23] ); - XXOR1 U224 (A[24] , B[24] , CARRY[24] , SUM[24] ); - XXOR1 U225 (A[25] , B[25] , CARRY[25] , SUM[25] ); - XXOR1 U226 (A[26] , B[26] , CARRY[26] , SUM[26] ); - XXOR1 U227 (A[27] , B[27] , CARRY[27] , SUM[27] ); - XXOR1 U228 (A[28] , B[28] , CARRY[28] , SUM[28] ); - XXOR1 U229 (A[29] , B[29] , CARRY[29] , SUM[29] ); - XXOR1 U230 (A[30] , B[30] , CARRY[30] , SUM[30] ); - XXOR1 U231 (A[31] , B[31] , CARRY[31] , SUM[31] ); - XXOR1 U232 (A[32] , B[32] , CARRY[32] , SUM[32] ); - XXOR1 U233 (A[33] , B[33] , CARRY[33] , SUM[33] ); - XXOR1 U234 (A[34] , B[34] , CARRY[34] , SUM[34] ); - XXOR1 U235 (A[35] , B[35] , CARRY[35] , SUM[35] ); - XXOR1 U236 (A[36] , B[36] , CARRY[36] , SUM[36] ); - XXOR1 U237 (A[37] , B[37] , CARRY[37] , SUM[37] ); - XXOR1 U238 (A[38] , B[38] , CARRY[38] , SUM[38] ); - XXOR1 U239 (A[39] , B[39] , CARRY[39] , SUM[39] ); - XXOR1 U240 (A[40] , B[40] , CARRY[40] , SUM[40] ); - XXOR1 U241 (A[41] , B[41] , CARRY[41] , SUM[41] ); - XXOR1 U242 (A[42] , B[42] , CARRY[42] , SUM[42] ); - XXOR1 U243 (A[43] , B[43] , CARRY[43] , SUM[43] ); - XXOR1 U244 (A[44] , B[44] , CARRY[44] , SUM[44] ); - XXOR1 U245 (A[45] , B[45] , CARRY[45] , SUM[45] ); - XXOR1 U246 (A[46] , B[46] , CARRY[46] , SUM[46] ); - XXOR1 U247 (A[47] , B[47] , CARRY[47] , SUM[47] ); - XXOR1 U248 (A[48] , B[48] , CARRY[48] , SUM[48] ); - XXOR1 U249 (A[49] , B[49] , CARRY[49] , SUM[49] ); - XXOR1 U250 (A[50] , B[50] , CARRY[50] , SUM[50] ); - XXOR1 U251 (A[51] , B[51] , CARRY[51] , SUM[51] ); - XXOR1 U252 (A[52] , B[52] , CARRY[52] , SUM[52] ); - XXOR1 U253 (A[53] , B[53] , CARRY[53] , SUM[53] ); - XXOR1 U254 (A[54] , B[54] , CARRY[54] , SUM[54] ); - XXOR1 U255 (A[55] , B[55] , CARRY[55] , SUM[55] ); - XXOR1 U256 (A[56] , B[56] , CARRY[56] , SUM[56] ); - XXOR1 U257 (A[57] , B[57] , CARRY[57] , SUM[57] ); - XXOR1 U258 (A[58] , B[58] , CARRY[58] , SUM[58] ); - XXOR1 U259 (A[59] , B[59] , CARRY[59] , SUM[59] ); - XXOR1 U260 (A[60] , B[60] , CARRY[60] , SUM[60] ); - XXOR1 U261 (A[61] , B[61] , CARRY[61] , SUM[61] ); - XXOR1 U262 (A[62] , B[62] , CARRY[62] , SUM[62] ); - XXOR1 U263 (A[63] , B[63] , CARRY[63] , SUM[63] ); - BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , COUT ); - -endmodule // XORSTAGE_64 - - -module DBLCTREE_64 ( PIN, GIN, GOUT, POUT ); - - input [63:0] PIN; - input [64:0] GIN; - - output [64:0] GOUT; - output [0:0] POUT; - - wire [62:0] INTPROP_0; - wire [64:0] INTGEN_0; - wire [60:0] INTPROP_1; - wire [64:0] INTGEN_1; - wire [56:0] INTPROP_2; - wire [64:0] INTGEN_2; - wire [48:0] INTPROP_3; - wire [64:0] INTGEN_3; - wire [32:0] INTPROP_4; - wire [64:0] INTGEN_4; - - DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) ); - DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) ); - DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) ); - DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) ); - DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) ); - DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .POUT(POUT) , .GOUT(GOUT) ); - -endmodule // DBLCTREE_64 - - -module DBLCADDER_64_64 ( OPA, OPB, CIN, SUM, COUT ); - - input [63:0] OPA; - input [63:0] OPB; - input CIN; - - output [63:0] SUM; - output COUT; - - wire [63:0] INTPROP; - wire [64:0] INTGEN; - wire [0:0] PBIT; - wire [64:0] CARRY; - - PRESTAGE_64 U1 (OPA , OPB , CIN , INTPROP , INTGEN ); - DBLCTREE_64 U2 (INTPROP , INTGEN , CARRY , PBIT ); - XORSTAGE_64 U3 (OPA[63:0] , OPB[63:0] , PBIT[0] , CARRY[64:0] , SUM , COUT ); - -endmodule diff --git a/pipelined/src/fpu/cla12.sv b/pipelined/src/fpu/cla12.sv deleted file mode 100644 index b098228c8..000000000 --- a/pipelined/src/fpu/cla12.sv +++ /dev/null @@ -1,332 +0,0 @@ -// This module implements a 12-bit carry lookahead adder. It is used -// for rounding in the floating point adder. - -module cla12 (S, CO, X, Y); - - input [11:0] X; - input [11:0] Y; - - output [11:0] S; - output CO; - - wire [63:0] A,B,Q;//***KEP was 0:63 - changed due to lint warning - wire LOGIC0; - wire CIN; - wire CO_64; - - assign LOGIC0 = 0; - assign CIN = 0; - - DBLCADDER_64_64 U1 (A , B , CIN, Q , CO_64); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = LOGIC0; - assign B[12] = LOGIC0; - assign A[13] = LOGIC0; - assign B[13] = LOGIC0; - assign A[14] = LOGIC0; - assign B[14] = LOGIC0; - assign A[15] = LOGIC0; - assign B[15] = LOGIC0; - assign A[16] = LOGIC0; - assign B[16] = LOGIC0; - assign A[17] = LOGIC0; - assign B[17] = LOGIC0; - assign A[18] = LOGIC0; - assign B[18] = LOGIC0; - assign A[19] = LOGIC0; - assign B[19] = LOGIC0; - assign A[20] = LOGIC0; - assign B[20] = LOGIC0; - assign A[21] = LOGIC0; - assign B[21] = LOGIC0; - assign A[22] = LOGIC0; - assign B[22] = LOGIC0; - assign A[23] = LOGIC0; - assign B[23] = LOGIC0; - assign A[24] = LOGIC0; - assign B[24] = LOGIC0; - assign A[25] = LOGIC0; - assign B[25] = LOGIC0; - assign A[26] = LOGIC0; - assign B[26] = LOGIC0; - assign A[27] = LOGIC0; - assign B[27] = LOGIC0; - assign A[28] = LOGIC0; - assign B[28] = LOGIC0; - assign A[29] = LOGIC0; - assign B[29] = LOGIC0; - assign A[30] = LOGIC0; - assign B[30] = LOGIC0; - assign A[31] = LOGIC0; - assign B[31] = LOGIC0; - assign A[32] = LOGIC0; - assign B[32] = LOGIC0; - assign A[33] = LOGIC0; - assign B[33] = LOGIC0; - assign A[34] = LOGIC0; - assign B[34] = LOGIC0; - assign A[35] = LOGIC0; - assign B[35] = LOGIC0; - assign A[36] = LOGIC0; - assign B[36] = LOGIC0; - assign A[37] = LOGIC0; - assign B[37] = LOGIC0; - assign A[38] = LOGIC0; - assign B[38] = LOGIC0; - assign A[39] = LOGIC0; - assign B[39] = LOGIC0; - assign A[40] = LOGIC0; - assign B[40] = LOGIC0; - assign A[41] = LOGIC0; - assign B[41] = LOGIC0; - assign A[42] = LOGIC0; - assign B[42] = LOGIC0; - assign A[43] = LOGIC0; - assign B[43] = LOGIC0; - assign A[44] = LOGIC0; - assign B[44] = LOGIC0; - assign A[45] = LOGIC0; - assign B[45] = LOGIC0; - assign A[46] = LOGIC0; - assign B[46] = LOGIC0; - assign A[47] = LOGIC0; - assign B[47] = LOGIC0; - assign A[48] = LOGIC0; - assign B[48] = LOGIC0; - assign A[49] = LOGIC0; - assign B[49] = LOGIC0; - assign A[50] = LOGIC0; - assign B[50] = LOGIC0; - assign A[51] = LOGIC0; - assign B[51] = LOGIC0; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign CO = Q[12]; - -endmodule //cla52 - -// This module implements a 12-bit carry lookahead subtractor. It is used -// for rounding in the floating point adder. - -module cla_sub12 (S, X, Y); - - input [11:0] X; - input [11:0] Y; - - output [11:0] S; - - wire [63:0] A,B,Q,Bbar;//***KEP was 0:63 - changed due to lint warning - wire CO; - wire LOGIC0; - wire VDD; - logic CO_12; - - assign Bbar = ~B; - assign LOGIC0 = 0; - assign VDD = 1; - - DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = LOGIC0; - assign B[12] = LOGIC0; - assign A[13] = LOGIC0; - assign B[13] = LOGIC0; - assign A[14] = LOGIC0; - assign B[14] = LOGIC0; - assign A[15] = LOGIC0; - assign B[15] = LOGIC0; - assign A[16] = LOGIC0; - assign B[16] = LOGIC0; - assign A[17] = LOGIC0; - assign B[17] = LOGIC0; - assign A[18] = LOGIC0; - assign B[18] = LOGIC0; - assign A[19] = LOGIC0; - assign B[19] = LOGIC0; - assign A[20] = LOGIC0; - assign B[20] = LOGIC0; - assign A[21] = LOGIC0; - assign B[21] = LOGIC0; - assign A[22] = LOGIC0; - assign B[22] = LOGIC0; - assign A[23] = LOGIC0; - assign B[23] = LOGIC0; - assign A[24] = LOGIC0; - assign B[24] = LOGIC0; - assign A[25] = LOGIC0; - assign B[25] = LOGIC0; - assign A[26] = LOGIC0; - assign B[26] = LOGIC0; - assign A[27] = LOGIC0; - assign B[27] = LOGIC0; - assign A[28] = LOGIC0; - assign B[28] = LOGIC0; - assign A[29] = LOGIC0; - assign B[29] = LOGIC0; - assign A[30] = LOGIC0; - assign B[30] = LOGIC0; - assign A[31] = LOGIC0; - assign B[31] = LOGIC0; - assign A[32] = LOGIC0; - assign B[32] = LOGIC0; - assign A[33] = LOGIC0; - assign B[33] = LOGIC0; - assign A[34] = LOGIC0; - assign B[34] = LOGIC0; - assign A[35] = LOGIC0; - assign B[35] = LOGIC0; - assign A[36] = LOGIC0; - assign B[36] = LOGIC0; - assign A[37] = LOGIC0; - assign B[37] = LOGIC0; - assign A[38] = LOGIC0; - assign B[38] = LOGIC0; - assign A[39] = LOGIC0; - assign B[39] = LOGIC0; - assign A[40] = LOGIC0; - assign B[40] = LOGIC0; - assign A[41] = LOGIC0; - assign B[41] = LOGIC0; - assign A[42] = LOGIC0; - assign B[42] = LOGIC0; - assign A[43] = LOGIC0; - assign B[43] = LOGIC0; - assign A[44] = LOGIC0; - assign B[44] = LOGIC0; - assign A[45] = LOGIC0; - assign B[45] = LOGIC0; - assign A[46] = LOGIC0; - assign B[46] = LOGIC0; - assign A[47] = LOGIC0; - assign B[47] = LOGIC0; - assign A[48] = LOGIC0; - assign B[48] = LOGIC0; - assign A[49] = LOGIC0; - assign B[49] = LOGIC0; - assign A[50] = LOGIC0; - assign B[50] = LOGIC0; - assign A[51] = LOGIC0; - assign B[51] = LOGIC0; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign CO_12 = Q[12]; - -endmodule //cla_sub52 diff --git a/pipelined/src/fpu/cla52.sv b/pipelined/src/fpu/cla52.sv deleted file mode 100644 index 5f818fbd8..000000000 --- a/pipelined/src/fpu/cla52.sv +++ /dev/null @@ -1,409 +0,0 @@ -// This module implements a 52-bit carry lookahead adder. It is used -// for rounding in the floating point adder. - -module cla52 (S, CO, X, Y); - - input [51:0] X; - input [51:0] Y; - - output [51:0] S; - output CO; - - wire [63:0] A,B,Q;//***KEP was 0:63 - changed due to lint warning - wire LOGIC0; - wire CIN; - wire CO_64; - - assign LOGIC0 = 0; - assign CIN = 0; - DBLCADDER_64_64 U1 (A , B , CIN, Q , CO_64); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign CO = Q[52]; - -endmodule //cla52 - -// This module implements a 52-bit carry lookahead subtractor. It is used -// for rounding in the floating point adder. - -module cla_sub52 (S, X, Y); - - input [51:0] X; - input [51:0] Y; - - output [51:0] S; - - wire [63:0] A,B,Q,Bbar;//***KEP was 0:63 - changed due to lint warning - wire LOGIC0; - wire CIN; - wire CO_52; - wire CO_64; - - assign Bbar = ~B; - assign LOGIC0 = 0; - assign CIN = 0; - - DBLCADDER_64_64 U1 (A , Bbar , CIN, Q , CO_64); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign CO_52 = Q[52]; - -endmodule //cla_sub52 diff --git a/pipelined/src/fpu/cla64.sv b/pipelined/src/fpu/cla64.sv deleted file mode 100755 index 6d28be10f..000000000 --- a/pipelined/src/fpu/cla64.sv +++ /dev/null @@ -1,420 +0,0 @@ -// This module implements a 64-bit carry lookehead adder/subtractor. -// It is used to perform the primary addition in the floating point -// adder - -module cla64 (S, X, Y, Sub); - - input [63:0] X; - input [63:0] Y; - input Sub; - output [63:0] S; - wire CO; - wire [63:0] A,B,Q, Bbar; //***KEP was 0:63 - changed due to lint warning - - DBLCADDER_64_64 U1 (A , Bbar , Sub , Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = B ^ {64{Sub}}; - -endmodule // cla64 - -// This module performs 64-bit subtraction. It is used to get the two's complement -// of main addition or subtraction in the floating point adder. - -module cla_sub64 (S, X, Y); - - input [63:0] X; - input [63:0] Y; - - output [63:0] S; - - wire CO; - wire VDD = 1'b1; - wire [63:0] A,B,Q, Bbar; //***KEP was 0:63 - changed due to lint warning - - DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = ~B; - -endmodule // cla_sub64 \ No newline at end of file diff --git a/pipelined/src/fpu/exception.sv b/pipelined/src/fpu/exception.sv deleted file mode 100755 index bccfa01f4..000000000 --- a/pipelined/src/fpu/exception.sv +++ /dev/null @@ -1,83 +0,0 @@ -// Exception logic for the floating point adder. Note: We may -// actually want to move to where the result is computed. - -module exception ( - - input logic [2:0] op_type, // Function opcode - input logic XSgnE, YSgnE, - // input logic [52:0] XManE, YManE, - input logic XDenormE, YDenormE, - input logic XNormE, YNormE, - input logic XZeroE, YZeroE, - input logic XInfE, YInfE, - input logic XNaNE, YNaNE, - input logic XSNaNE, YSNaNE, - output logic [3:0] Ztype, // Indicates type of result (Z) - output logic Invalid, // Invalid operation exception - output logic Denorm, // Denormalized logic - output logic Sub // The effective operation is subtraction -); - wire ZQNaN; // '1' if result Z is a quiet NaN - wire ZPInf; // '1' if result Z positive infnity - wire ZNInf; // '1' if result Z negative infnity - wire add_sub; // '1' if operation is add or subtract - wire converts; // See if there are any converts - - - - // Is this instruction a convert - assign converts = op_type[1]; - - - - // An "Invalid Operation" exception occurs if (A or B is a signalling NaN) - // or (A and B are both Infinite and the "effective operation" is - // subtraction). - assign add_sub = ~op_type[1]; - assign Invalid = (XSNaNE | YSNaNE | (add_sub & XInfE & YInfE & (XSgnE^YSgnE^op_type[0]))) & ~converts; - - // The Denorm flag is set if (A is denormlized and the operation is not integer - // conversion ) or (if B is normalized and the operation is addition or subtraction). - assign Denorm = XDenormE | YDenormE & add_sub; - - // The result is a quiet NaN if (an "Invalid Operation" exception occurs) - // or (A is a NaN) or (B is a NaN and the operation uses B). - assign ZQNaN = Invalid | XNaNE | (YNaNE & add_sub); - - // The result is +Inf if ((A is +Inf) or (B is -Inf and the operation is - // subtraction) or (B is +Inf and the operation is addition)) and (the - // result is not a quiet NaN). - assign ZPInf = (XInfE&XSgnE | add_sub&YInfE&(~YSgnE^op_type[0]))&~ZQNaN; - - // The result is -Inf if ((A is -Inf) or (B is +Inf and the operation is - // subtraction) or (B is -Inf and the operation is addition)) and the - // result is not a quiet NaN. - assign ZNInf = (XInfE&~XSgnE | add_sub&YInfE&(YSgnE^op_type[0]))&~ZQNaN; - - // Set the type of the result as follows: - // (needs optimization - got lazy or was late) - // Ztype Result - // 0000 Normal - // 0001 Quiet NaN - // 0010 Negative Infinity - // 0011 Positive Infinity - // 0100 +Bzero and +Azero (and vice-versa) - // 0101 +Bzero and -Azero (and vice-versa) - // 1000 Convert SP to DP (and vice-versa) - - assign Ztype[0] = (ZQNaN | ZPInf) | - ((XZeroE & YZeroE & (XSgnE^YSgnE^op_type[0])) - & ~converts); - assign Ztype[1] = (ZNInf | ZPInf) | - (((XZeroE & YZeroE & XSgnE & YSgnE & ~op_type[0]) | - (XZeroE & YZeroE & XSgnE & ~YSgnE & op_type[0])) - & ~converts); - assign Ztype[2] = ((XZeroE & YZeroE & ~op_type[1]) - & ~converts); - assign Ztype[3] = (op_type[1] & ~op_type[0]); - - // Determine if the effective operation is subtraction - assign Sub = add_sub & (XSgnE^YSgnE^op_type[0]); - -endmodule // exception - diff --git a/pipelined/src/fpu/faddcvt.sv b/pipelined/src/fpu/faddcvt.sv deleted file mode 100755 index e5dddb7e9..000000000 --- a/pipelined/src/fpu/faddcvt.sv +++ /dev/null @@ -1,426 +0,0 @@ -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr., Brett Mathis -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// Copyright AFRL -// -// Basic and Denormalized Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller exponent, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put sum onto output. -// - -module faddcvt( - input logic clk, - input logic reset, - input logic FlushM, // flush the memory stage - input logic StallM, // stall the memory stage - input logic [63:0] FSrcXE, // 1st input operand (A) - input logic [63:0] FSrcYE, // 2nd input operand (B) - input logic [2:0] FOpCtrlE, FOpCtrlM, // Function opcode - input logic FmtE, FmtM, // Result Precision (0 for double, 1 for single) - input logic [2:0] FrmM, // Rounding mode - specify values - input logic XSgnE, YSgnE, - input logic [52:0] XManE, YManE, - input logic [10:0] XExpE, YExpE, - input logic XSgnM, YSgnM, - input logic [52:0] XManM, YManM, - input logic [10:0] XExpM, YExpM, - input logic XDenormE, YDenormE, - input logic XNormE, YNormE, - input logic XNormM, YNormM, - input logic XZeroE, YZeroE, - input logic XInfE, YInfE, - input logic XNaNE, YNaNE, - input logic XSNaNE, YSNaNE, - output logic [63:0] FAddResM, // Result of operation - output logic [4:0] FAddFlgM); // IEEE exception flags - - logic [63:0] AddSumE, AddSumM; - logic [63:0] AddSumTcE, AddSumTcM; - logic [3:0] AddSelInvE, AddSelInvM; - logic [10:0] AddExpPostSumE,AddExpPostSumM; - logic AddCorrSignE, AddCorrSignM; - logic AddOpANormE, AddOpANormM; - logic AddOpBNormE, AddOpBNormM; - logic AddInvalidE, AddInvalidM; - logic AddDenormInE, AddDenormInM; - logic AddSwapE, AddSwapM; - logic AddSignAE, AddSignAM; - logic [11:0] AddExp1DenormE, AddExp2DenormE, AddExp1DenormM, AddExp2DenormM; - logic [10:0] AddExponentE, AddExponentM; - - - fpuaddcvt1 fpadd1 (.FOpCtrlE, .FmtE, .AddExponentE, - .AddExpPostSumE, .AddExp1DenormE, .AddExp2DenormE, .AddSumE, .AddSumTcE, .AddSelInvE, - .XSgnE, .YSgnE,.XManE, .YManE, .XExpE, .YExpE, .XDenormE, .YDenormE, .XNormE, .YNormE, .XZeroE, .YZeroE, .XInfE, .YInfE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, - .AddCorrSignE, .AddSignAE, .AddOpANormE, .AddOpBNormE, .AddInvalidE, - .AddDenormInE, .AddSwapE); - - // E/M pipeline registers - flopenrc #(64) EMRegAdd1(clk, reset, FlushM, ~StallM, AddSumE, AddSumM); - flopenrc #(64) EMRegAdd2(clk, reset, FlushM, ~StallM, AddSumTcE, AddSumTcM); - flopenrc #(11) EMRegAdd3(clk, reset, FlushM, ~StallM, AddExpPostSumE, AddExpPostSumM); - flopenrc #(12) EMRegAdd6(clk, reset, FlushM, ~StallM, AddExp1DenormE, AddExp1DenormM); - flopenrc #(12) EMRegAdd7(clk, reset, FlushM, ~StallM, AddExp2DenormE, AddExp2DenormM); - flopenrc #(11) EMRegAdd8(clk, reset, FlushM, ~StallM, AddExponentE, AddExponentM); - flopenrc #(11) EMRegAdd9(clk, reset, FlushM, ~StallM, - {AddSelInvE, AddCorrSignE, AddOpANormE, AddOpBNormE, AddInvalidE, AddDenormInE, AddSwapE, AddSignAE}, - {AddSelInvM, AddCorrSignM, AddOpANormM, AddOpBNormM, AddInvalidM, AddDenormInM, AddSwapM, AddSignAM}); - - - fpuaddcvt2 fpadd2 (.FrmM, .FOpCtrlM, .FmtM, .AddSumM, .AddSumTcM, .XNormM, .YNormM, - .AddExp1DenormM, .AddExp2DenormM, .AddExponentM, .AddExpPostSumM, .AddSelInvM, .XSgnM, .YSgnM, .XManM, .YManM, .XExpM, .YExpM, - .AddOpANormM, .AddOpBNormM, .AddInvalidM, .AddDenormInM, - .AddSignAM, .AddCorrSignM, .AddSwapM, .FAddResM, .FAddFlgM); -endmodule - -module fpuaddcvt1 ( - input logic [2:0] FOpCtrlE, // Function opcode - input logic FmtE, // Result Precision (1 for double, 0 for single) - input logic XSgnE, YSgnE, - input logic [10:0] XExpE, YExpE, - input logic [52:0] XManE, YManE, - input logic XDenormE, YDenormE, - input logic XNormE, YNormE, - input logic XZeroE, YZeroE, - input logic XInfE, YInfE, - input logic XNaNE, YNaNE, - input logic XSNaNE, YSNaNE, - - output logic [10:0] AddExponentE, - output logic [10:0] AddExpPostSumE, - output logic [11:0] AddExp1DenormE, AddExp2DenormE,//KEP used to be [10:0] - output logic [63:0] AddSumE, AddSumTcE, - output logic [3:0] AddSelInvE, - output logic AddCorrSignE, - output logic AddSignAE, - output logic AddOpANormE, AddOpBNormE, - output logic AddInvalidE, - output logic AddDenormInE, - output logic AddSwapE - ); - - logic [5:0] ZP_mantissaA; - logic [5:0] ZP_mantissaB; - wire ZV_mantissaA; - wire ZV_mantissaB; - - wire P; - assign P = ~(FmtE^FOpCtrlE[1]); - - wire [63:0] IntValue; - wire [11:0] exp1, exp2; - wire [11:0] exp_diff1, exp_diff2; - wire [11:0] exp_shift; - wire [51:0] mantissaA; - wire [56:0] mantissaA1; - wire [63:0] mantissaA3; - wire [51:0] mantissaB; - wire [56:0] mantissaB1, mantissaB2; - wire [63:0] mantissaB3; - wire exp_gt63; - wire Sticky_out; - wire sub; - wire zeroB; - wire [5:0] align_shift; - - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input Flags. The "AddSelInvE" is used in - // the third pipeline stage to select the result. Also, AddOp1NormE - // and AddOp2NormE are one if FSrcXE and FSrcYE are not zero or denormalized. - // sub is one if the effective operation is subtaction. - - exception exc1 (.Ztype(AddSelInvE), .Invalid(AddInvalidE), .Denorm(AddDenormInE), .Sub(sub), - .XSgnE, .YSgnE, .XDenormE, .YDenormE, .XNormE, .YNormE, .XZeroE, .YZeroE, .XInfE, .YInfE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, - .op_type(FOpCtrlE)); - - // Perform Exponent Subtraction (used for alignment). For performance - // both exponent subtractions are performed in parallel. This was - // changed to a behavior level to allow the tools to try to optimize - // the two parallel additions. The input values are zero-extended to 12 - // bits prior to performing the addition. - - assign exp1 = {1'b0, XExpE}; - assign exp2 = {1'b0, YExpE}; - assign exp_diff1 = exp1 - exp2; - assign exp_diff2 = AddDenormInE ? ({YSgnE, YExpE} - {XSgnE, XExpE}): exp2 - exp1; - - // The second operand (B) should be set to zero, if FOpCtrlE does not - // specify addition or subtraction - assign zeroB = FOpCtrlE[1]; - - // Swapped operands if zeroB is not one and exp1 < exp2. - // Swapping causes exp2 to be used for the result exponent. - // Only the exponent of the larger operand is used to determine - // the final result. - assign AddSwapE = exp_diff1[11] & ~zeroB; - assign AddExponentE = AddSwapE ? YExpE : XExpE; - assign AddExpPostSumE = AddSwapE ? YExpE : XExpE; - assign mantissaA = AddSwapE ? YManE[51:0] : XManE[51:0]; - assign mantissaB = AddSwapE ? XManE[51:0] : YManE[51:0]; - assign AddSignAE = AddSwapE ? YSgnE : XSgnE; - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - // modified to 52 bits to detect leading zeroes on denormalized mantissas - // lz52 lz_norm_1 (ZP_mantissaA, ZV_mantissaA, mantissaA); - // lz52 lz_norm_2 (ZP_mantissaB, ZV_mantissaB, mantissaB); - logic [8:0] i; - logic [8:0] j; - always_comb begin - i = 0; - while (~mantissaA[52-i] & $unsigned(i) <= $unsigned(52)) i = i+1; // search for leading one - ZP_mantissaA = i; - end - always_comb begin - j = 0; - while (~mantissaB[52-j] & $unsigned(j) <= $unsigned(52)) j = j+1; // search for leading one - ZP_mantissaB = j; - end - - // Denormalized exponents created by subtracting the leading zeroes from the original exponents - assign AddExp1DenormE = AddSwapE ? (exp1 - {6'b0, ZP_mantissaB}) : (exp1 - {6'b0, ZP_mantissaA}); //KEP extended ZP_mantissa - assign AddExp2DenormE = AddSwapE ? (exp2 - {6'b0, ZP_mantissaA}) : (exp2 - {6'b0, ZP_mantissaB}); - - // Determine the alignment shift and limit it to 63. If any bit from - // exp_shift[6] to exp_shift[11] is one, then shift is set to all ones. - assign exp_shift = AddSwapE ? exp_diff2 : exp_diff1; - assign exp_gt63 = exp_shift[11] | exp_shift[10] | exp_shift[9] - | exp_shift[8] | exp_shift[7] | exp_shift[6]; - assign align_shift = exp_shift[5:0] | {6{exp_gt63}}; //KEP used to be all of exp_shift - - // Unpack the 52-bit mantissas to 57-bit numbers of the form. - // 001.M[51]M[50] ... M[1]M[0]00 - // Unless the number has an exponent of zero, in which case it - // is unpacked as - // 000.00 ... 00 - // This effectively flushes denormalized values to zero. - // The three bits of to the left of the binary point prevent overflow - // and loss of sign information. The two bits to the right of the - // original mantissa form the "guard" and "round" bits that are used - // to round the result. - assign AddOpANormE = AddSwapE ? YNormE : XNormE; - assign AddOpBNormE = AddSwapE ? XNormE : YNormE; - assign mantissaA1 = {2'h0, AddOpANormE, mantissaA[51:0]&{52{AddOpANormE}}, 2'h0}; - assign mantissaB1 = {2'h0, AddOpBNormE, mantissaB[51:0]&{52{AddOpBNormE}}, 2'h0}; - - // Perform mantissa alignment using a 57-bit barrel shifter - // If any of the bits shifted out are one, Sticky_out is set. - // The size of the barrel shifter could be reduced by two bits - // by not adding the leading two zeros until after the shift. - barrel_shifter_r57 bs1 (mantissaB2, Sticky_out, mantissaB1, align_shift); - - // Place either the sign-extened 32-bit value or the original 64-bit value - // into IntValue (to be used for integer to floating point conversion) - // assign IntValue [31:0] = FSrcXE[31:0]; - // assign IntValue [63:32] = FOpCtrlE[0] ? {32{FSrcXE[31]}} : FSrcXE[63:32]; - - // If doing an integer to floating point conversion, mantissaA3 is set to - // IntVal and the prenomalized exponent is set to 1084. Otherwise, - // mantissaA3 is simply extended to 64-bits by setting the 7 LSBs to zero, - // and the exponent value is left unchanged. - // Under denormalized cases, the exponent before the rounder is set to 1 - // if the normal shift value is 11. - assign mantissaA3 = AddDenormInE ? ({12'h0, mantissaA}) : {mantissaA1, 7'h0}; - - // Put zero in for mantissaB3, if zeroB is one. Otherwise, B is extended to - // 64-bits by setting the 7 LSBs to the Sticky_out bit followed by six - // zeros. - assign mantissaB3[63:7] = AddDenormInE ? {12'h0, mantissaB[51:7]} : mantissaB2 & {57{~zeroB}}; - assign mantissaB3[6] = AddDenormInE ? mantissaB[6] : Sticky_out & ~zeroB; - assign mantissaB3[5:0] = AddDenormInE ? mantissaB[5:0] : 6'h0; - - // The sign of the result needs to be corrected if the true - // operation is subtraction and the input operands were swapped. - assign AddCorrSignE = ~FOpCtrlE[1]&FOpCtrlE[0]&AddSwapE; - - // 64-bit Mantissa Adder/Subtractor - cla64 add1 (AddSumE, mantissaA3, mantissaB3, sub); //***adder - - // 64-bit Mantissa Subtractor - to get the two's complement of the - // result when the sign from the adder/subtractor is negative. - cla_sub64 sub1 (AddSumTcE, mantissaB3, mantissaA3); //***adder - - // Finds normal underflow result to determine whether to round final exponent down - //***KEP used to be (AddSumE == 16'h0) I am unsure what it's supposed to be - // assign AddNormOvflowE = (AddDenormInE & (AddSumE == 64'h0) & (AddOpANormE | AddOpBNormE) & ~FOpCtrlE[0]) ? 1'b1 : (AddSumE[63] ? AddSumTcE[52] : AddSumE[52]); - -endmodule // fpadd - - -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr., Brett Mathis -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// Copyright AFRL -// -// Basic and Denormalized Operations -// -// Step 1: Load operands, set flags, and AddConvertM SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller AddExponentM, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put AddSumM onto output. -// - - -module fpuaddcvt2 ( - input logic [2:0] FrmM, // Rounding mode - specify values - input logic [2:0] FOpCtrlM, // Function opcode - input logic FmtM, // Result Precision (0 for double, 1 for single) - input logic [63:0] AddSumM, AddSumTcM, - input logic [11:0] AddExp1DenormM, AddExp2DenormM, - input logic [10:0] AddExponentM, AddExpPostSumM, - input logic [3:0] AddSelInvM, - input logic XSgnM, YSgnM, - input logic [52:0] XManM, YManM, - input logic [10:0] XExpM, YExpM, - input logic XNormM, YNormM, - input logic AddOpANormM, AddOpBNormM, - input logic AddInvalidM, - input logic AddDenormInM, - input logic AddSignAM, - input logic AddCorrSignM, - input logic AddSwapM, - - output logic [63:0] FAddResM, // Result of operation - output logic [4:0] FAddFlgM // IEEE exception flags -); - wire AddDenormM; // AddDenormM on input or output - - wire P; - assign P = ~(FmtM^FOpCtrlM[1]); - - wire [10:0] exp_pre; - wire [63:0] Result; - wire [63:0] sum_norm, sum_norm_w_bypass; - wire [5:0] norm_shift, norm_shift_denorm; - wire exp_valid; - wire DenormIO; - wire [4:0] FlagsIn; - wire Sticky_out; - wire sign_corr; - wire zeroB; - wire mantissa_comp; - wire mantissa_comp_sum; - wire mantissa_comp_sum_tc; - wire Float1_sum_comp; - wire Float2_sum_comp; - wire Float1_sum_tc_comp; - wire Float2_sum_tc_comp; - wire normal_underflow; - wire [63:0] sum_corr; - logic AddNormOvflowM; - - - logic AddOvEnM; // Overflow trap enabled - logic AddUnEnM; // Underflow trap enabled - - assign AddOvEnM = 1'b1; - assign AddUnEnM = 1'b1; - //AddExponentM value pre-rounding with considerations for denormalized - //cases/conversion cases - assign exp_pre = AddDenormInM ? - ((norm_shift == 6'b001011) ? 11'b00000000001 : (AddSwapM ? AddExp2DenormM[10:0] : AddExp1DenormM[10:0])) - : AddExponentM; - - - // Finds normal underflow result to determine whether to round final AddExponentM down - // Comparison between each float and the resulting AddSumM of the primary cla adder/subtractor and cla subtractor - assign Float1_sum_comp = ~(XManM[51:0] > AddSumM[51:0]); - assign Float2_sum_comp = ~(YManM[51:0] > AddSumM[51:0]); - assign Float1_sum_tc_comp = ~(XManM[51:0] > AddSumTcM[51:0]); - assign Float2_sum_tc_comp = ~(YManM[51:0] > AddSumTcM[51:0]); - - // Determines the correct Float value to compare based on AddSwapM result - assign mantissa_comp_sum = AddSwapM ? Float2_sum_comp : Float1_sum_comp; - assign mantissa_comp_sum_tc = AddSwapM ? Float2_sum_tc_comp : Float1_sum_tc_comp; - - // Determines the correct comparison result based on operation and sign of resulting AddSumM - assign mantissa_comp = (FOpCtrlM[0] ^ AddSumM[63]) ? mantissa_comp_sum_tc : mantissa_comp_sum; - - // If the signs are different and both operands aren't denormalized - // the normal underflow bit is needed and therefore updated. - assign normal_underflow = ((XSgnM ^ YSgnM) & (AddOpANormM | AddOpBNormM)) ? mantissa_comp : 1'b0; - - // Determine the correct sign of the result - assign sign_corr = (AddCorrSignM ^ AddSignAM) ^ AddSumM[63]; - - // If the AddSumM is negative, use its two complement instead. - // This value has to be 64-bits to correctly handle the - // case 10...00 - assign sum_corr = (AddDenormInM & (AddOpANormM | AddOpBNormM) & ( ( (XSgnM ~^ YSgnM) & FOpCtrlM[0] ) | ((XSgnM ^ YSgnM) & ~FOpCtrlM[0]) )) - ? (AddSumM[63] ? AddSumM : AddSumTcM) : (AddSumM[63] ? AddSumTcM : AddSumM); - - // Finds normal underflow result to determine whether to round final AddExponentM down - //KEP used to be (AddSumM == 16'h0) not sure what it is supposed to be - assign AddNormOvflowM = (AddDenormInM & (AddSumM == 64'h0) & (AddOpANormM | AddOpBNormM) & ~FOpCtrlM[0]) ? 1'b1 : (AddSumM[63] ? AddSumTcM[52] : AddSumM[52]); - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - lz64 lzd1 (norm_shift, exp_valid, sum_corr); - - assign norm_shift_denorm = (AddDenormInM & ( (~AddOpANormM & ~AddOpBNormM) | normal_underflow)) ? (6'h00) : (norm_shift); - - // Barell shifter used for normalization. It takes as inputs the - // the corrected AddSumM and the amount by which the AddSumM should - // be right shifted. It outputs the normalized AddSumM. - barrel_shifter_l64 bs2 (sum_norm, sum_corr, norm_shift_denorm); - - assign sum_norm_w_bypass = sum_norm; - - // Round the mantissa to a 52-bit value, with the leading one - // removed. If the result is a single precision number, the actual - // mantissa is in the upper 23 bits and the lower 29 bits are zero. - // At this point, normalization has already been performed, so we know - // exactly where the rounding point is. The rounding units also - // handles special cases and set the exception flags. - - // Changed DenormIO -> AddDenormM and FlagsIn -> FAddFlgM in order to - // help in processor reservation station detection of load/stores. In - // other words, the processor would like to know ahead of time that - // if the result is an exception then don't load or store. - rounder round1 (.Result, .DenormIO, .Flags(FlagsIn), .rm(FrmM), .P, .OvEn(AddOvEnM), .UnEn(AddUnEnM), .exp_valid, - .sel_inv(AddSelInvM), .Invalid(AddInvalidM), .DenormIn(AddDenormInM), .Asign(sign_corr), .Aexp(exp_pre), .norm_shift, .A(sum_norm_w_bypass), - .exponent_postsum(AddExpPostSumM), .A_Norm(XNormM), .B_Norm(YNormM), .exp_A_unmodified({XSgnM, XExpM}), .exp_B_unmodified({YSgnM, YExpM}), - .normal_overflow(AddNormOvflowM), .normal_underflow, .swap(AddSwapM), .op_type(FOpCtrlM), .sum(AddSumM)); - - // Store the final result and the exception flags in registers. - assign FAddResM = Result; - assign {AddDenormM, FAddFlgM} = {DenormIO, FlagsIn}; - -endmodule // fpadd - - diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv deleted file mode 100644 index f43d15661..000000000 --- a/pipelined/src/fpu/fcvtfp.sv +++ /dev/null @@ -1,190 +0,0 @@ - -`include "wally-config.vh" -module fcvtfp ( - input logic [10:0] XExpE, // input's exponent - input logic [52:0] XManE, // input's mantissa - input logic XSgnE, // input's sign - input logic XZeroE, // is the input zero - input logic XDenormE, // is the input denormalized - input logic XInfE, // is the input infinity - input logic XNaNE, // is the input a NaN - input logic XSNaNE, // is the input a signaling NaN - input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic FmtE, // the input's precision (1 = double 0 = single) - output logic [63:0] CvtFpResE, // the fp to fp conversion's result - output logic [4:0] CvtFpFlgE); // the fp to fp conversion's flags - - logic [12:0] DSExp; // double to single precision exponent - logic Denorm; // is the double to single precision result denormalized - logic Shift; // do you shift the double precision exponent (if single precision result is denormalized) - logic [51:0] SDFrac; // single to double precision fraction - logic [25:0] DSFrac; // double to single precision fraction - logic [77:0] DSFracShifted; // single precision fraction shifted for double precision - logic Sticky, UfSticky, Guard, Round, LSBFrac, UfGuard, UfRound, UfLSBFrac; // rounding bits - logic CalcPlus1, UfCalcPlus1, Plus1, UfPlus1; // do you add one to the result - logic [12:0] DSExpFull; // full double to single exponent - logic [22:0] DSResFrac; // final double to single fraction - logic [7:0] DSResExp; // final double to single exponent - logic [10:0] SDExp; // final single to double precision exponent - logic Overflow, Underflow, Inexact; // flags - logic [31:0] DSRes; // double to single precision result - - - // add support for all formats - // consider reordering code blocks so upconverting is in one region of the file - // and downconverting is in the other region. - - /////////////////////////////////////////////////////////////////////////////// - // LZC: Leading Zero Counter - /////////////////////////////////////////////////////////////////////////////// - - // *** consider sharing this with fcvtint - // *** emphasize parallel structure between the two - // *** add a priorityencoder module to generic (similar to priorityonehot) and use it - - // LZC - find the first 1 in the input's mantissa - logic [8:0] i,NormCnt; - always_comb begin - i = 0; - while (~XManE[52-i] & i <= 52) i = i+1; // search for leading one - NormCnt = i; - end - - - /////////////////////////////////////////////////////////////////////////////// - // Expoents - /////////////////////////////////////////////////////////////////////////////// - - // convert the single precion exponent to single precision. - // - subtract the double precision exponent (1023) and add the - // single precsision exponent (127) - // - if the input is zero then kill the exponent - - assign DSExp = ({2'b0,XExpE}-13'd1023+13'd127)&{13{~XZeroE}}; - - // is the converted double to single precision exponent in the denormalized range - assign Denorm = $signed(DSExp) <= 0 & $signed(DSExp) > $signed(-(13'd23)); - - - // caluculate the final single to double precsion exponent - // - subtract the single precision bias (127) and add the double - // precision bias (127) - // - if the result is zero or denormalized, kill the exponent - assign SDExp = XExpE-({2'b0,NormCnt&{9{~XZeroE}}})+({11{XDenormE}}&1024-127); //*** seems ineffecient - - - - /////////////////////////////////////////////////////////////////////////////// - // Fraction - /////////////////////////////////////////////////////////////////////////////// - - - // normalize the single precision fraction for double precsion - // - needed for denormal single precsion values - assign SDFrac = XManE[51:0] << NormCnt; - - // check if the double precision mantissa needs to be shifted - // - the mantissa needs to be shifted if the single precision result is denormal - assign Shift = Denorm | (($signed(DSExp) > $signed(-(13'd25))) & DSExp[12]); - // shift the mantissa - assign DSFracShifted = {XManE, 25'b0} >> ((-DSExp+1)&{13{Shift}}); //***might be some optimization here - assign DSFrac = DSFracShifted[76:51]; - - - - /////////////////////////////////////////////////////////////////////////////// - // Rounder - /////////////////////////////////////////////////////////////////////////////// - - // used to determine underflow flag - assign UfSticky = |DSFracShifted[50:0]; - assign UfGuard = DSFrac[1]; - assign UfRound = DSFrac[0]; - assign UfLSBFrac = DSFrac[2]; - - - assign Sticky = UfSticky | UfRound; - assign Guard = DSFrac[2]; - assign Round = DSFrac[1]; - assign LSBFrac = DSFrac[3]; - - - always_comb begin // ***remove guard bit - // Determine if you add 1 - case (FrmE) - 3'b000: CalcPlus1 = Guard & (Round | (Sticky) | (~Round&~Sticky&LSBFrac));//round to nearest even - 3'b001: CalcPlus1 = 0;//round to zero - 3'b010: CalcPlus1 = XSgnE;//round down - 3'b011: CalcPlus1 = ~XSgnE;//round up - 3'b100: CalcPlus1 = (Guard & (Round | (Sticky) | (~Round&~Sticky)));//round to nearest max magnitude - default: CalcPlus1 = 1'bx; - endcase - // Determine if you add 1 (for underflow flag) - case (FrmE) - 3'b000: UfCalcPlus1 = UfGuard & (UfRound | UfSticky | (~UfRound&~UfSticky&UfLSBFrac));//round to nearest even - 3'b001: UfCalcPlus1 = 0;//round to zero - 3'b010: UfCalcPlus1 = XSgnE;//round down - 3'b011: UfCalcPlus1 = ~XSgnE;//round up - 3'b100: UfCalcPlus1 = (UfGuard & (UfRound | UfSticky | (~UfRound&~UfSticky)));//round to nearest max magnitude - default: UfCalcPlus1 = 1'bx; - endcase - - end - - // if an answer is exact don't round - assign Plus1 = CalcPlus1 & (Sticky | UfGuard | Guard | Round); - assign UfPlus1 = UfCalcPlus1 & (Sticky | UfGuard); - - - - // round the double to single precision result - assign {DSExpFull, DSResFrac} = {DSExp&{13{~Denorm}}, DSFrac[25:3]} + {35'b0,Plus1}; - assign DSResExp = DSExpFull[7:0]; - - - /////////////////////////////////////////////////////////////////////////////// - // Flags - /////////////////////////////////////////////////////////////////////////////// - - // calculate the flags - // - overflow, underflow and inexact can only be set by the double to single precision opperation - // - don't set underflow or overflow if the input is NaN or Infinity - // - don't set the inexact flag if the input is NaN - assign Overflow = $signed(DSExpFull) >= $signed({5'b0, {8{1'b1}}}) & ~(XNaNE|XInfE); - assign Underflow = (($signed(DSExpFull) <= 0) & ((Sticky|Guard|Round) | (XManE[52]&~|DSFrac) | (|DSFrac&~Denorm)) | ((DSExpFull == 1) & Denorm & ~(UfPlus1&UfLSBFrac))) & ~(XNaNE|XInfE); - assign Inexact = (Sticky|Guard|Round|Underflow|Overflow) &~(XNaNE); - - // pack the flags together and choose the result based on the opperation - assign CvtFpFlgE = FmtE ? {XSNaNE, 1'b0, Overflow, Underflow, Inexact} : {XSNaNE, 4'b0}; - - - - /////////////////////////////////////////////////////////////////////////////// - // Result Selection - /////////////////////////////////////////////////////////////////////////////// - - if(`IEEE754) begin - // select the double to single precision result - assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} : - Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} : - Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} : - {XSgnE, 8'hff, 23'b0} : - {XSgnE, DSResExp, DSResFrac}; - - // select the final result based on the opperation - //*** in al units before putting into : ? put in a seperate signal - assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]}; - end else begin - // select the double to single precision result - assign DSRes = XNaNE ? {1'b0, {8{1'b1}}, 1'b1, 22'b0} : - Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} : - Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} : - {XSgnE, 8'hff, 23'b0} : - {XSgnE, DSResExp, DSResFrac}; - - // select the final result based on the opperation - assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE&~XNaNE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]&{51{~XNaNE}}}; - end -endmodule // fpadd - - diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv deleted file mode 100644 index 97007d660..000000000 --- a/pipelined/src/fpu/fcvtint.sv +++ /dev/null @@ -1,190 +0,0 @@ - -`include "wally-config.vh" -// `include "../../config/rv64icfd/wally-config.vh" -// `define XLEN 64 -module fcvtint ( - input logic XSgnE, // X's sign - input logic [10:0] XExpE, // X's exponent - input logic [52:0] XManE, // X's fraction - input logic XZeroE, // is X zero - input logic XNaNE, // is X NaN - input logic XInfE, // is X infinity - input logic XDenormE, // is X denormalized - input logic [`XLEN-1:0] ForwardedSrcAE, // integer input - input logic [2:0] FOpCtrlE, // chooses which instruction is done (full list below) - input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic FmtE, // precision 1 = double 0 = single - output logic [63:0] CvtResE, // convert final result - output logic [4:0] CvtFlgE); // convert flags {invalid, divide by zero, overflow, underflow, inexact} - - logic ResSgn; // FP result's sign - logic [10:0] ResExp,TmpExp; // FP result's exponent - logic [51:0] ResFrac; // FP result's fraction - logic [6:0] LZResP; // lz output - logic [7:0] Bits; // how many bits are in the integer result - logic [7:0] SubBits; // subtract these bits from the exponent (FP result) - logic [64+51:0] ShiftedManTmp; // Shifted mantissa - logic [64+51:0] ShiftVal; // value being shifted (to int - XMan, to FP - |integer input|) - logic [64+1:0] ShiftedMan; // shifted mantissa truncated - logic [64:0] RoundedTmp; // full size rounded result - in case of overfow - logic [63:0] Rounded; // rounded result - logic [12:0] ExpVal; // unbiased X exponent - logic [12:0] ShiftCnt; // how much is the mantissa shifted - logic [64-1:0] IntIn; // trimed integer input - logic [64-1:0] PosInt; // absolute value of the integer input - logic [63:0] CvtIntRes; // interger result from the fp -> int instructions - logic [63:0] CvtFPRes; // floating point result from the int -> fp instructions - logic Of, Uf; // did the integer result underflow or overflow - logic Guard, Round, LSB, Sticky; // bits used to determine rounding - logic Plus1,CalcPlus1; // do you add one for rounding - logic SgnRes; // sign of the floating point result - logic Res64, In64; // is the result or input 64 bits - logic RoundMSB; // most significant bit of the fraction - logic RoundSgn; // sign of the rounded result - logic Invalid, Inexact; // flags - - // FOpCtrlE: - // fcvt.w.s = 001 - // fcvt.wu.s = 011 - // fcvt.s.w = 000 - // fcvt.s.wu = 010 - // fcvt.l.s = 101 - // fcvt.lu.s = 111 - // fcvt.s.l = 100 - // fcvt.s.lu = 110 - // fcvt.w.d = 001 - // fcvt.wu.d = 011 - // fcvt.d.w = 000 - // fcvt.d.wu = 010 - // fcvt.l.d = 101 - // fcvt.lu.d = 111 - // fcvt.d.l = 100 - // fcvt.d.lu = 110 - // {long, unsigned, to int} - - // *** revisit this module, explain in more depth - // should the int to fp and fp to int paths be separated? - // add support for all formats - - // calculate signals based off the input and output's size - assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]); - assign In64 = (~FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&FOpCtrlE[0]); - assign SubBits = In64 ? 8'd64 : 8'd32; - assign Bits = Res64 ? 8'd64 : 8'd32; - - // calulate the unbiased exponent - assign ExpVal = {1'b0,XExpE} - {1'b0, (11)'(`BIAS)} + {12'b0, XDenormE}; - -//////////////////////////////////////////////////////// - - // position the input in the most significant bits - assign IntIn = FOpCtrlE[2] ? {ForwardedSrcAE, {64-`XLEN{1'b0}}} : {ForwardedSrcAE[31:0], 32'b0}; - // make the integer positive - assign PosInt = IntIn[64-1]&~FOpCtrlE[1] ? -IntIn : IntIn; - // determine the integer's sign - assign ResSgn = ~FOpCtrlE[1]&IntIn[64-1]; - - // Leading one detector - logic [8:0] i; - always_comb begin - i = 0; - while (~PosInt[64-1-i] & i < `XLEN) i = i+1; // search for leading one - LZResP = i[5:0]+1; // compute shift count - end - - // if no one was found set to zero otherwise calculate the exponent - assign TmpExp = i==`XLEN ? 0 : FmtE ? 11'd1023 + {3'b0, SubBits} - {4'b0, LZResP} : 11'd127 + {3'b0, SubBits} - {4'b0, LZResP}; - - - - -//////////////////////////////////////////// - - - // select the shift value and amount based on operation (to fp or int) - assign ShiftCnt = FOpCtrlE[0] ? ExpVal : {6'b0, LZResP}; - assign ShiftVal = FOpCtrlE[0] ? {{64-1{1'b0}}, XManE} : {PosInt, 52'b0}; - - // if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds) - // if the shift is negitive add a bit for sticky bit calculation - // otherwise shift left - assign ShiftedManTmp = &ShiftCnt ? {{64{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt; - - // truncate the shifted mantissa - assign ShiftedMan = ShiftedManTmp[64+51:50]; - - // calculate sticky bit - // - take into account the possible right shift from before - // - the sticky bit calculation covers three diffrent sizes depending on the opperation - assign Sticky = |ShiftedManTmp[49:0] | &ShiftCnt&XManE[0] | (~FOpCtrlE[0]&|ShiftedManTmp[62:50]) | (~FOpCtrlE[0]&~FmtE&|ShiftedManTmp[91:63]); - - - // determine guard, round, and least significant bit of the result - assign Guard = FOpCtrlE[0] ? ShiftedMan[1] : FmtE ? ShiftedMan[13] : ShiftedMan[42]; - assign Round = FOpCtrlE[0] ? ShiftedMan[0] : FmtE ? ShiftedMan[12] : ShiftedMan[41]; - assign LSB = FOpCtrlE[0] ? ShiftedMan[2] : FmtE ? ShiftedMan[14] : ShiftedMan[43]; - - always_comb begin//*** remove guard bit - // Determine if you add 1 - case (FrmE) - 3'b000: CalcPlus1 = Guard & (Round | Sticky | (~Round&~Sticky&LSB));//round to nearest even - 3'b001: CalcPlus1 = 0;//round to zero - 3'b010: CalcPlus1 = (XSgnE&FOpCtrlE[0]) | (ResSgn&~FOpCtrlE[0]);//round down - 3'b011: CalcPlus1 = (~XSgnE&FOpCtrlE[0]) | (~ResSgn&~FOpCtrlE[0]);//round up - 3'b100: CalcPlus1 = Guard & (Round | Sticky | (~Round&~Sticky));//round to nearest max magnitude - default: CalcPlus1 = 1'bx; - endcase - end - - // dont tound if the result is exact - assign Plus1 = CalcPlus1 & (Guard|Round|Sticky)&~(XZeroE&FOpCtrlE[0]); - - // round the shifted mantissa - assign RoundedTmp = ShiftedMan[64+1:2] + {64'b0, Plus1}; - assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + {62'b0, Plus1} : {{TmpExp, ShiftedMan[64+1:43]} + {33'b0,Plus1}, 29'b0} ; - - // fit the rounded result into the appropriate size and take the 2's complement if needed - assign Rounded = Res64 ? XSgnE&FOpCtrlE[0] ? -RoundedTmp[63:0] : RoundedTmp[63:0] : - XSgnE ? {{32{1'b1}}, -RoundedTmp[31:0]} : {32'b0, RoundedTmp[31:0]}; - - // extract the MSB and Sign for later use (will be used to determine underflow and overflow) - assign RoundMSB = Res64 ? RoundedTmp[64] : RoundedTmp[32]; - assign RoundSgn = Res64 ? Rounded[63] : Rounded[31]; - - - // check if the result overflows - assign Of = (~XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (~XSgnE&RoundSgn&~FOpCtrlE[1]) | (RoundMSB&(ShiftCnt==({{5{Bits[7]}}, Bits}-1))) | (~XSgnE&XInfE) | XNaNE; - - // check if the result underflows (this calculation changes if the result is signed or unsigned) - assign Uf = FOpCtrlE[1] ? XSgnE&~XZeroE | (XSgnE&XInfE) | (XSgnE&~XZeroE&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgnE&XInfE) | (XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (XSgnE&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgnE | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded; - - // calculate the result's sign - assign SgnRes = ~FOpCtrlE[2] & FOpCtrlE[0]; - - // select the integer result - assign CvtIntRes = Of ? FOpCtrlE[1] ? {64{1'b1}} : SgnRes ? {33'b0, {31{1'b1}}}: {1'b0, {63{1'b1}}} : - Uf ? FOpCtrlE[1] ? {63'b0, Plus1&~XSgnE} : SgnRes ? {{33{1'b1}}, 31'b0} : {1'b1, 63'b0} : - |RoundedTmp ? Rounded[64-1:0] : 64'b0; - - // select the floating point result - assign CvtFPRes = FmtE ? {ResSgn, ResExp, ResFrac} : {{32{1'b1}}, ResSgn, ResExp[7:0], ResFrac[51:29]}; - - // select the result - assign CvtResE = FOpCtrlE[0] ? CvtIntRes : CvtFPRes; - - // calculate the flags - // - only set invalid flag for out-of-range vales - // - set inexact if in representable range and not exact - - if(`IEEE754) begin // checks before rounding - assign Invalid = (Of | Uf)&FOpCtrlE[0]; - assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&(XSgnE|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]); - assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact}; - end else begin // RISC-V checks if the result is in range after rounding - assign Invalid = (Of | Uf)&FOpCtrlE[0]; - assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&((XSgnE&~(ShiftCnt[12]&~Plus1))|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]); - assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact}; - end -endmodule // fpadd - - diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 383b6200b..053d3dd5c 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -214,7 +214,7 @@ module fpu ( // other FP execution units fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE); - fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE); + fsgninj fsgninj(.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE); fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE); fcvt fcvt (.XSgnE, .XExpE, .XManE, .ForwardedSrcAE, .FOpCtrlE, .FWriteIntE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtResE, .CvtIntResE, .CvtFlgE); diff --git a/pipelined/src/fpu/fsgn.sv b/pipelined/src/fpu/fsgn.sv deleted file mode 100755 index b95fd078f..000000000 --- a/pipelined/src/fpu/fsgn.sv +++ /dev/null @@ -1,29 +0,0 @@ -//performs the fsgnj/fsgnjn/fsgnjx RISCV instructions - -module fsgn ( - input logic XSgnE, YSgnE, // X and Y sign bits - input logic [63:0] FSrcXE, // X - input logic FmtE, // precision 1 = double 0 = single - input logic [1:0] SgnOpCodeE, // operation control - output logic [63:0] SgnResE // result - ); - - logic ResSgn; - - //op code designation: - // - //00 - fsgnj - directly copy over sign value of FSrcYE - //01 - fsgnjn - negate sign value of FSrcYE - //10 - fsgnjx - XOR sign values of FSrcXE & FSrcYE - // - - // calculate the result's sign - assign ResSgn = SgnOpCodeE[1] ? (XSgnE ^ YSgnE) : (YSgnE ^ SgnOpCodeE[0]); - - // format final result based on precision - // - uses NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s - assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]}; - - -endmodule diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv new file mode 100755 index 000000000..8474fdff6 --- /dev/null +++ b/pipelined/src/fpu/fsgninj.sv @@ -0,0 +1,56 @@ +/////////////////////////////////////////// +// +// Written: Katherine Parry +// Modified: 6/23/2021 +// +// Purpose: FPU Sign Injection instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module fsgninj ( + input logic XSgnE, YSgnE, // X and Y sign bits + input logic [63:0] FSrcXE, // X + input logic FmtE, // precision 1 = double 0 = single + input logic [1:0] SgnOpCodeE, // operation control + output logic [63:0] SgnResE // result +); + + logic ResSgn; + + //op code designation: + // + //00 - fsgnj - directly copy over sign value of FSrcYE + //01 - fsgnjn - negate sign value of FSrcYE + //10 - fsgnjx - XOR sign values of FSrcXE & FSrcYE + // + + // calculate the result's sign + assign ResSgn = SgnOpCodeE[1] ? (XSgnE ^ YSgnE) : (YSgnE ^ SgnOpCodeE[0]); + + // format final result based on precision + // - uses NaN-blocking format + // - if there are any unsused bits the most significant bits are filled with 1s + assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]}; + + +endmodule