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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-02-09 16:11:31 -06:00
commit d1e79aaea5
1 changed files with 17 additions and 9 deletions
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26
synthDC/scripts/synth.tcl
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@ -1,7 +1,11 @@
# #
# OKSTATE Main Synopsys Flow # Synthesis Synopsys Flow
# Updated Sep 27, 2015 jes # james.stine@okstate.edu 27 Sep 2015
# #
# Enables name mapping
saif_map -start
# get outputDir from environment (Makefile) # get outputDir from environment (Makefile)
set outputDir $::env(OUTPUTDIR) set outputDir $::env(OUTPUTDIR)
set cfgName $::env(CONFIG) set cfgName $::env(CONFIG)
@ -15,7 +19,6 @@ eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
# Verilog files # Verilog files
set my_verilog_files [glob hdl/*] set my_verilog_files [glob hdl/*]
@ -48,6 +51,12 @@ link
# Reset all constraints # Reset all constraints
reset_design reset_design
# SAIF power prediction (optional)
# set_power_prediction
# Power Dissipation Analysis
# read_saif -input vcd/mult.saif -instance_name stimulus/dut -auto_map_names -verbose
# Set reset false path # Set reset false path
set_false_path -from [get_ports reset] set_false_path -from [get_ports reset]
@ -71,13 +80,13 @@ if { $find_clock != [list] } {
} }
# Partitioning - flatten or hierarchically synthesize # Partitioning - flatten or hierarchically synthesize
#ungroup -all -flatten -simple_names # ungroup -all -flatten -simple_names
# Set input pins except clock # Set input pins except clock
set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
# Specifies delays be propagated through the clock network # Specifies delays be propagated through the clock network
#set_propagated_clock [get_clocks $my_clk] # set_propagated_clock [get_clocks $my_clk]
# Setting constraints on input ports # Setting constraints on input ports
#set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk #set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
@ -99,7 +108,6 @@ if {$tech == "130"} {
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
} }
# Set the wire load model # Set the wire load model
set_wire_load_mode "top" set_wire_load_mode "top"
@ -116,9 +124,9 @@ set_max_fanout 6 $all_in_ex_clk
set_fix_multiple_port_nets -all -buffer_constants set_fix_multiple_port_nets -all -buffer_constants
# setting up the group paths to find out the required timings # setting up the group paths to find out the required timings
#group_path -name OUTPUTS -to [all_outputs] # group_path -name OUTPUTS -to [all_outputs]
#group_path -name INPUTS -from [all_inputs] # group_path -name INPUTS -from [all_inputs]
#group_path -name COMBO -from [all_inputs] -to [all_outputs] # group_path -name COMBO -from [all_inputs] -to [all_outputs]
# Save Unmapped Design # Save Unmapped Design
set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"]