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https://github.com/openhwgroup/cvw
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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commit
d1e79aaea5
@ -1,7 +1,11 @@
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#
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#
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# OKSTATE Main Synopsys Flow
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# Synthesis Synopsys Flow
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# Updated Sep 27, 2015 jes
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# james.stine@okstate.edu 27 Sep 2015
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#
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#
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# Enables name mapping
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saif_map -start
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# get outputDir from environment (Makefile)
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# get outputDir from environment (Makefile)
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set outputDir $::env(OUTPUTDIR)
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set outputDir $::env(OUTPUTDIR)
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set cfgName $::env(CONFIG)
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set cfgName $::env(CONFIG)
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@ -15,7 +19,6 @@ eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
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eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
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eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
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eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
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eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
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# Verilog files
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# Verilog files
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set my_verilog_files [glob hdl/*]
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set my_verilog_files [glob hdl/*]
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@ -48,6 +51,12 @@ link
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# Reset all constraints
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# Reset all constraints
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reset_design
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reset_design
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# SAIF power prediction (optional)
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# set_power_prediction
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# Power Dissipation Analysis
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# read_saif -input vcd/mult.saif -instance_name stimulus/dut -auto_map_names -verbose
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# Set reset false path
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# Set reset false path
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set_false_path -from [get_ports reset]
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set_false_path -from [get_ports reset]
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@ -99,7 +108,6 @@ if {$tech == "130"} {
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set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
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set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
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}
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}
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# Set the wire load model
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# Set the wire load model
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set_wire_load_mode "top"
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set_wire_load_mode "top"
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