diff --git a/.gitignore b/.gitignore index 047e9ed7a..eae7c79e8 100644 --- a/.gitignore +++ b/.gitignore @@ -52,4 +52,7 @@ examples/asm/sumtest/sumtest examples/asm/example/example examples/C/sum/sum examples/C/fir/fir - +synthDC/hdl/*.sv +linux/devicetree/debug/* +!linux/devicetree/debug/dumpdts.sh +*.dtb diff --git a/.gitmodules b/.gitmodules index ba8877ce5..b396b1d43 100644 --- a/.gitmodules +++ b/.gitmodules @@ -20,3 +20,6 @@ [submodule "addins/sky130_osu_sc_t18"] path = addins/sky130_osu_sc_t18 url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18 +[submodule "addins/sky130_osu_sc_t12"] + path = addins/sky130_osu_sc_t12 + url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 diff --git a/addins/sky130_osu_sc_t12 b/addins/sky130_osu_sc_t12 new file mode 160000 index 000000000..f1eef8447 --- /dev/null +++ b/addins/sky130_osu_sc_t12 @@ -0,0 +1 @@ +Subproject commit f1eef844734f73d3c79d83b82352118263eb7686 diff --git a/benchmarks/riscv-coremark/Makefile b/benchmarks/riscv-coremark/Makefile index 1e8869408..2100b784f 100644 --- a/benchmarks/riscv-coremark/Makefile +++ b/benchmarks/riscv-coremark/Makefile @@ -6,8 +6,10 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ $(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \ $(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c -work/coremark.bare.riscv.memfile: work/coremark.bare.riscv +work/coremark.bare.riscv.elf.memfile: work/coremark.bare.riscv + riscv64-unknown-elf-objdump -D $< > $<.elf.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@ + extractFunctionRadix.sh $<.elf.objdump work/coremark.bare.riscv.objdump: work/coremark.bare.riscv riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump diff --git a/examples/C/fir/fir b/examples/C/fir/fir deleted file mode 100755 index 4266f84b9..000000000 Binary files a/examples/C/fir/fir and /dev/null differ diff --git a/examples/verilog/xz/distributedmux.sv b/examples/verilog/xz/distributedmux.sv new file mode 100644 index 000000000..060705ecf --- /dev/null +++ b/examples/verilog/xz/distributedmux.sv @@ -0,0 +1,58 @@ +// xz.sv +// David_Harris@hmc.edu 30 January 2022 +// Demonstrate impact of x and z. + +// load with vsim xz.sv + +module testbench(); + logic [3:0] d0, d1, d2; + logic s0, s1, s2; + tri [3:0] y; + + distributedmux dut(.d0, .d1, .d2, .s0, .s1, .s2, .y); + + initial begin + d0 = 4'b0000; d1 = 4'b0101; // d2 unknown (xxxx) + s0 = 0; s1 = 0; s2 = 0; + #10; // y should be floating + s0 = 1; + #10; //y should be driven to 0000 + s0 = 0; s1 = 1; + #10; // y should be driven to 0101 + s0 = 1; + #10; // y should be driven to 0x0x because of contention on bits 0 and 2 + s0 = 0; s1 = 0; s2 = 1; + #10; // y should be driven to unknown because d2 is unknown + end +endmodule + +module tristate #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, + input logic en, + output logic [WIDTH-1:0] y); + + assign y = en ? a : 'z; +endmodule + +module distributedmux( + input logic [3:0] d0, d1, d2, + input logic s0, s1, s2, + output tri [3:0] y); + + tristate #(4) t0(d0, s0, y); + tristate #(4) t1(d1, s1, y); + tristate #(4) t2(d2, s2, y); +endmodule + +module gpio #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] GPIOOutVal, GPIOEn, + output logic [WIDTH-1:0] GPIOInVal, + inout tri [WIDTH-1:0] GPIOPin); + + assign GPIOInVal = GPIOPin; + tristate #(1) ts[WIDTH-1:0](GPIOOutVal, GPIOEn, GPIOPin); +endmodule + +module silly(output logic [128:0] y); + assign y = 'bz; +endmodule \ No newline at end of file diff --git a/examples/verilog/xz/xz.sv b/examples/verilog/xz/xz.sv new file mode 100644 index 000000000..d9837e75c --- /dev/null +++ b/examples/verilog/xz/xz.sv @@ -0,0 +1,19 @@ +// xz.sv +// David_Harris@hmc.edu 30 January 2022 +// Demonstrate impact of x and z. + +// load with vsim xz.sv + +module xz( + output logic w, x, y, z); + + logic p, q, r; + + // let p be undriven + assign q = 1'bz; + assign r = 1'bx; + + assign w = q & 1'b1; + assign x = q | 1'b1; +endmodule + diff --git a/linux/add_wally_to_QEMU.patch b/linux/add_wally_to_QEMU.patch deleted file mode 100644 index 3b332f202..000000000 --- a/linux/add_wally_to_QEMU.patch +++ /dev/null @@ -1,645 +0,0 @@ -From 61696744ed1197c9435b85a4ac5610090faa3179 Mon Sep 17 00:00:00 2001 -From: bbracker -Date: Wed, 26 Jan 2022 14:43:11 +0000 -Subject: [PATCH] add Wally model to QEMU - ---- - configs/devices/riscv64-softmmu/default.mak | 1 + - hw/riscv/Kconfig | 7 + - hw/riscv/meson.build | 1 + - hw/riscv/wally.c | 501 ++++++++++++++++++++ - include/hw/riscv/wally.h | 79 +++ - 5 files changed, 589 insertions(+) - create mode 100644 hw/riscv/wally.c - create mode 100644 include/hw/riscv/wally.h - -diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/riscv64-softmmu/default.mak -index bc69301fa4..396ebb82a1 100644 ---- a/configs/devices/riscv64-softmmu/default.mak -+++ b/configs/devices/riscv64-softmmu/default.mak -@@ -14,3 +14,4 @@ CONFIG_SIFIVE_U=y - CONFIG_RISCV_VIRT=y - CONFIG_MICROCHIP_PFSOC=y - CONFIG_SHAKTI_C=y -+CONFIG_WALLY=y -diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig -index d2d869aaad..a7ed6ae06f 100644 ---- a/hw/riscv/Kconfig -+++ b/hw/riscv/Kconfig -@@ -81,3 +81,10 @@ config SPIKE - select MSI_NONBROKEN - select RISCV_ACLINT - select SIFIVE_PLIC -+ -+config WALLY -+ bool -+ select SERIAL -+ select RISCV_ACLINT -+ select SIFIVE_PLIC -+ select SIFIVE_TEST -diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build -index ab6cae57ea..b468f2c87c 100644 ---- a/hw/riscv/meson.build -+++ b/hw/riscv/meson.build -@@ -9,5 +9,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) - riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) - riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) - riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) -+riscv_ss.add(when: 'CONFIG_WALLY', if_true: files('wally.c')) - - hw_arch += {'riscv': riscv_ss} -diff --git a/hw/riscv/wally.c b/hw/riscv/wally.c -new file mode 100644 -index 0000000000..25792dd04c ---- /dev/null -+++ b/hw/riscv/wally.c -@@ -0,0 +1,501 @@ -+/* -+ * QEMU RISC-V Wally Board -+ * Modified from Virt Board -+ * -+ * Copyright (c) 2017 SiFive, Inc. -+ * *** What should we say for copyright? -+ * -+ * RISC-V machine with 16550a UART and VirtIO MMIO -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#include "qemu/osdep.h" -+#include "qemu/units.h" -+#include "qemu/error-report.h" -+#include "qapi/error.h" -+#include "hw/boards.h" -+#include "hw/loader.h" -+#include "hw/sysbus.h" -+#include "hw/qdev-properties.h" -+#include "hw/char/serial.h" -+#include "target/riscv/cpu.h" -+#include "hw/riscv/riscv_hart.h" -+#include "hw/riscv/wally.h" -+#include "hw/riscv/boot.h" -+#include "hw/riscv/numa.h" -+#include "hw/intc/riscv_aclint.h" -+#include "hw/intc/sifive_plic.h" -+#include "hw/misc/sifive_test.h" -+#include "chardev/char.h" -+#include "sysemu/device_tree.h" -+#include "sysemu/sysemu.h" -+#include "hw/pci/pci.h" -+#include "hw/pci-host/gpex.h" -+#include "hw/display/ramfb.h" -+ -+static const MemMapEntry wally_memmap[] = { -+ [WALLY_MROM] = { 0x1000, 0xf000 }, -+ [WALLY_CLINT] = { 0x2000000, 0x10000 }, -+ [WALLY_PLIC] = { 0xc000000, WALLY_PLIC_SIZE(WALLY_CPUS_MAX * 2) }, -+ [WALLY_UART0] = { 0x10000000, 0x100 }, -+ [WALLY_DRAM] = { 0x80000000, 0x0 }, -+}; -+ -+static void create_fdt_socket_cpus(WallyState *s, int socket, -+ char *clust_name, uint32_t *phandle, -+ bool is_32_bit, uint32_t *intc_phandles) -+{ -+ int cpu; -+ uint32_t cpu_phandle; -+ MachineState *mc = MACHINE(s); -+ char *name, *cpu_name, *core_name, *intc_name; -+ -+ for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { -+ cpu_phandle = (*phandle)++; -+ -+ cpu_name = g_strdup_printf("/cpus/cpu@%d", -+ s->soc[socket].hartid_base + cpu); -+ qemu_fdt_add_subnode(mc->fdt, cpu_name); -+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", -+ (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); -+ name = riscv_isa_string(&s->soc[socket].harts[cpu]); -+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); -+ g_free(name); -+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); -+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); -+ qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", -+ s->soc[socket].hartid_base + cpu); -+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); -+ riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); -+ qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); -+ -+ intc_phandles[cpu] = (*phandle)++; -+ -+ intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); -+ qemu_fdt_add_subnode(mc->fdt, intc_name); -+ qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", -+ intc_phandles[cpu]); -+ qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", -+ "riscv,cpu-intc"); -+ qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); -+ qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); -+ -+ core_name = g_strdup_printf("%s/core%d", clust_name, cpu); -+ qemu_fdt_add_subnode(mc->fdt, core_name); -+ qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); -+ -+ g_free(core_name); -+ g_free(intc_name); -+ g_free(cpu_name); -+ } -+} -+ -+static void create_fdt_socket_memory(WallyState *s, -+ const MemMapEntry *memmap, int socket) -+{ -+ char *mem_name; -+ uint64_t addr, size; -+ MachineState *mc = MACHINE(s); -+ -+ addr = memmap[WALLY_DRAM].base + riscv_socket_mem_offset(mc, socket); -+ size = riscv_socket_mem_size(mc, socket); -+ mem_name = g_strdup_printf("/memory@%lx", (long)addr); -+ qemu_fdt_add_subnode(mc->fdt, mem_name); -+ qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", -+ addr >> 32, addr, size >> 32, size); -+ qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); -+ riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); -+ g_free(mem_name); -+} -+ -+static void create_fdt_socket_clint(WallyState *s, -+ const MemMapEntry *memmap, int socket, -+ uint32_t *intc_phandles) -+{ -+ int cpu; -+ char *clint_name; -+ uint32_t *clint_cells; -+ unsigned long clint_addr; -+ MachineState *mc = MACHINE(s); -+ static const char * const clint_compat[2] = { -+ "sifive,clint0", "riscv,clint0" -+ }; -+ -+ clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); -+ -+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { -+ clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); -+ clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); -+ clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); -+ clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); -+ } -+ -+ clint_addr = memmap[WALLY_CLINT].base + (memmap[WALLY_CLINT].size * socket); -+ clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); -+ qemu_fdt_add_subnode(mc->fdt, clint_name); -+ qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", -+ (char **)&clint_compat, -+ ARRAY_SIZE(clint_compat)); -+ qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", -+ 0x0, clint_addr, 0x0, memmap[WALLY_CLINT].size); -+ qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", -+ clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); -+ riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); -+ g_free(clint_name); -+ -+ g_free(clint_cells); -+} -+ -+ -+static void create_fdt_socket_plic(WallyState *s, -+ const MemMapEntry *memmap, int socket, -+ uint32_t *phandle, uint32_t *intc_phandles, -+ uint32_t *plic_phandles) -+{ -+ int cpu; -+ char *plic_name; -+ uint32_t *plic_cells; -+ unsigned long plic_addr; -+ MachineState *mc = MACHINE(s); -+ static const char * const plic_compat[2] = { -+ "sifive,plic-1.0.0", "riscv,plic0" -+ }; -+ -+ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); -+ -+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { -+ plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); -+ plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); -+ plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); -+ plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); -+ } -+ -+ plic_phandles[socket] = (*phandle)++; -+ plic_addr = memmap[WALLY_PLIC].base + (memmap[WALLY_PLIC].size * socket); -+ plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); -+ qemu_fdt_add_subnode(mc->fdt, plic_name); -+ qemu_fdt_setprop_cell(mc->fdt, plic_name, -+ "#address-cells", FDT_PLIC_ADDR_CELLS); -+ qemu_fdt_setprop_cell(mc->fdt, plic_name, -+ "#interrupt-cells", FDT_PLIC_INT_CELLS); -+ qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", -+ (char **)&plic_compat, -+ ARRAY_SIZE(plic_compat)); -+ qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); -+ qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", -+ plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); -+ qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", -+ 0x0, plic_addr, 0x0, memmap[WALLY_PLIC].size); -+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", WALLYIO_NDEV); -+ riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); -+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", -+ plic_phandles[socket]); -+ g_free(plic_name); -+ -+ g_free(plic_cells); -+} -+ -+static void create_fdt_sockets(WallyState *s, const MemMapEntry *memmap, -+ bool is_32_bit, uint32_t *phandle) -+{ -+ int socket; -+ char *clust_name; -+ uint32_t *intc_phandles; -+ MachineState *mc = MACHINE(s); -+ uint32_t xplic_phandles[MAX_NODES]; -+ -+ qemu_fdt_add_subnode(mc->fdt, "/cpus"); -+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", -+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); -+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); -+ qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); -+ qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); -+ -+ for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { -+ clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); -+ qemu_fdt_add_subnode(mc->fdt, clust_name); -+ -+ intc_phandles = g_new0(uint32_t, s->soc[socket].num_harts); -+ -+ create_fdt_socket_cpus(s, socket, clust_name, phandle, -+ is_32_bit, intc_phandles); -+ -+ create_fdt_socket_memory(s, memmap, socket); -+ -+ create_fdt_socket_clint(s, memmap, socket, intc_phandles); -+ -+ create_fdt_socket_plic(s, memmap, socket, phandle, -+ intc_phandles, xplic_phandles); -+ -+ g_free(intc_phandles); -+ g_free(clust_name); -+ } -+ riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); -+} -+ -+static void create_fdt_uart(WallyState *s, const MemMapEntry *memmap) -+{ -+ char *name; -+ MachineState *mc = MACHINE(s); -+ -+ name = g_strdup_printf("/soc/uart@%lx", (long)memmap[WALLY_UART0].base); -+ qemu_fdt_add_subnode(mc->fdt, name); -+ qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); -+ qemu_fdt_setprop_cells(mc->fdt, name, "reg", -+ 0x0, memmap[WALLY_UART0].base, -+ 0x0, memmap[WALLY_UART0].size); -+ qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); -+ qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); -+ -+ qemu_fdt_add_subnode(mc->fdt, "/chosen"); -+ qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); -+ g_free(name); -+} -+ -+static void create_fdt(WallyState *s, const MemMapEntry *memmap, -+ uint64_t mem_size, const char *cmdline, bool is_32_bit) -+{ -+ MachineState *mc = MACHINE(s); -+ uint32_t phandle = 1; -+ -+ if (mc->dtb) { -+ mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); -+ if (!mc->fdt) { -+ error_report("load_device_tree() failed"); -+ exit(1); -+ } -+ goto update_bootargs; -+ } else { -+ mc->fdt = create_device_tree(&s->fdt_size); -+ if (!mc->fdt) { -+ error_report("create_device_tree() failed"); -+ exit(1); -+ } -+ } -+ -+ qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-wally,qemu"); -+ qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-wally"); -+ qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); -+ qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); -+ -+ qemu_fdt_add_subnode(mc->fdt, "/soc"); -+ qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); -+ qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); -+ qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); -+ qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); -+ -+ create_fdt_sockets(s, memmap, is_32_bit, &phandle); -+ create_fdt_uart(s, memmap); -+ -+update_bootargs: -+ if (cmdline) { -+ qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); -+ } -+} -+ -+static void wally_machine_init(MachineState *machine) -+{ -+ const MemMapEntry *memmap = wally_memmap; -+ WallyState *s = RISCV_WALLY_MACHINE(machine); -+ MemoryRegion *system_memory = get_system_memory(); -+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1); -+ char *plic_hart_config, *soc_name; -+ target_ulong start_addr = memmap[WALLY_DRAM].base; -+ target_ulong firmware_end_addr, kernel_start_addr; -+ uint32_t fdt_load_addr; -+ uint64_t kernel_entry; -+ DeviceState *mmio_plic, *wallyio_plic, *pcie_plic; -+ int i, base_hartid, hart_count; -+ -+ /* Check socket count limit */ -+ if (WALLY_SOCKETS_MAX < riscv_socket_count(machine)) { -+ error_report("number of sockets/nodes should be less than %d", -+ WALLY_SOCKETS_MAX); -+ exit(1); -+ } -+ -+ /* Initialize sockets */ -+ mmio_plic = wallyio_plic = pcie_plic = NULL; -+ for (i = 0; i < riscv_socket_count(machine); i++) { -+ if (!riscv_socket_check_hartids(machine, i)) { -+ error_report("discontinuous hartids in socket%d", i); -+ exit(1); -+ } -+ -+ base_hartid = riscv_socket_first_hartid(machine, i); -+ if (base_hartid < 0) { -+ error_report("can't find hartid base for socket%d", i); -+ exit(1); -+ } -+ -+ hart_count = riscv_socket_hart_count(machine, i); -+ if (hart_count < 0) { -+ error_report("can't find hart count for socket%d", i); -+ exit(1); -+ } -+ -+ soc_name = g_strdup_printf("soc%d", i); -+ object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], -+ TYPE_RISCV_HART_ARRAY); -+ g_free(soc_name); -+ object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", -+ machine->cpu_type, &error_abort); -+ object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", -+ base_hartid, &error_abort); -+ object_property_set_int(OBJECT(&s->soc[i]), "num-harts", -+ hart_count, &error_abort); -+ sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); -+ -+ /* Per-socket CLINT */ -+ riscv_aclint_swi_create( -+ memmap[WALLY_CLINT].base + i * memmap[WALLY_CLINT].size, -+ base_hartid, hart_count, false); -+ riscv_aclint_mtimer_create( -+ memmap[WALLY_CLINT].base + i * memmap[WALLY_CLINT].size + -+ RISCV_ACLINT_SWI_SIZE, -+ RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, -+ RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, -+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); -+ -+ /* Per-socket PLIC hart topology configuration string */ -+ plic_hart_config = riscv_plic_hart_config_string(hart_count); -+ -+ /* Per-socket PLIC */ -+ s->plic[i] = sifive_plic_create( -+ memmap[WALLY_PLIC].base + i * memmap[WALLY_PLIC].size, -+ plic_hart_config, hart_count, base_hartid, -+ WALLY_PLIC_NUM_SOURCES, -+ WALLY_PLIC_NUM_PRIORITIES, -+ WALLY_PLIC_PRIORITY_BASE, -+ WALLY_PLIC_PENDING_BASE, -+ WALLY_PLIC_ENABLE_BASE, -+ WALLY_PLIC_ENABLE_STRIDE, -+ WALLY_PLIC_CONTEXT_BASE, -+ WALLY_PLIC_CONTEXT_STRIDE, -+ memmap[WALLY_PLIC].size); -+ g_free(plic_hart_config); -+ -+ /* Try to use different PLIC instance based device type */ -+ if (i == 0) { -+ mmio_plic = s->plic[i]; -+ } -+ } -+ -+ if (riscv_is_32bit(&s->soc[0])) { -+#if HOST_LONG_BITS == 64 -+ /* limit RAM size in a 32-bit system */ -+ if (machine->ram_size > 10 * GiB) { -+ machine->ram_size = 10 * GiB; -+ error_report("Limiting RAM size to 10 GiB"); -+ } -+#endif -+ } -+ -+ /* register system main memory (actual RAM) */ -+ memory_region_add_subregion(system_memory, memmap[WALLY_DRAM].base, -+ machine->ram); -+ -+ /* create device tree */ -+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, -+ riscv_is_32bit(&s->soc[0])); -+ -+ /* boot rom */ -+ memory_region_init_rom(mask_rom, NULL, "wally_board.mrom", -+ memmap[WALLY_MROM].size, &error_fatal); -+ memory_region_add_subregion(system_memory, memmap[WALLY_MROM].base, -+ mask_rom); -+ -+ if (riscv_is_32bit(&s->soc[0])) { -+ firmware_end_addr = riscv_find_and_load_firmware(machine, -+ RISCV32_BIOS_BIN, start_addr, NULL); -+ } else { -+ firmware_end_addr = riscv_find_and_load_firmware(machine, -+ RISCV64_BIOS_BIN, start_addr, NULL); -+ } -+ -+ if (machine->kernel_filename) { -+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], -+ firmware_end_addr); -+ -+ kernel_entry = riscv_load_kernel(machine->kernel_filename, -+ kernel_start_addr, NULL); -+ -+ if (machine->initrd_filename) { -+ hwaddr start; -+ hwaddr end = riscv_load_initrd(machine->initrd_filename, -+ machine->ram_size, kernel_entry, -+ &start); -+ qemu_fdt_setprop_cell(machine->fdt, "/chosen", -+ "linux,initrd-start", start); -+ qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", -+ end); -+ } -+ } else { -+ /* -+ * If dynamic firmware is used, it doesn't know where is the next mode -+ * if kernel argument is not set. -+ */ -+ kernel_entry = 0; -+ } -+ -+ /* Compute the fdt load address in dram */ -+ fdt_load_addr = riscv_load_fdt(memmap[WALLY_DRAM].base, -+ machine->ram_size, machine->fdt); -+ /* load the reset vector */ -+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, -+ wally_memmap[WALLY_MROM].base, -+ wally_memmap[WALLY_MROM].size, kernel_entry, -+ fdt_load_addr, machine->fdt); -+ -+ serial_mm_init(system_memory, memmap[WALLY_UART0].base, -+ 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, -+ serial_hd(0), DEVICE_LITTLE_ENDIAN); -+} -+ -+static void wally_machine_instance_init(Object *obj) -+{ -+} -+ -+static void wally_machine_class_init(ObjectClass *oc, void *data) -+{ -+ MachineClass *mc = MACHINE_CLASS(oc); -+ -+ mc->desc = "Wally SoC"; -+ mc->init = wally_machine_init; -+ mc->max_cpus = WALLY_CPUS_MAX; -+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE; -+ mc->pci_allow_0_address = true; -+ mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; -+ mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; -+ mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; -+ mc->numa_mem_supported = false; -+ mc->default_ram_id = "wally_board.ram"; -+ -+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); -+} -+ -+static const TypeInfo wally_machine_typeinfo = { -+ .name = MACHINE_TYPE_NAME("wally"), -+ .parent = TYPE_MACHINE, -+ .class_init = wally_machine_class_init, -+ .instance_init = wally_machine_instance_init, -+ .instance_size = sizeof(WallyState), -+}; -+ -+static void wally_machine_init_register_types(void) -+{ -+ type_register_static(&wally_machine_typeinfo); -+} -+ -+type_init(wally_machine_init_register_types) -diff --git a/include/hw/riscv/wally.h b/include/hw/riscv/wally.h -new file mode 100644 -index 0000000000..80f2cc15dc ---- /dev/null -+++ b/include/hw/riscv/wally.h -@@ -0,0 +1,79 @@ -+/* -+ * QEMU RISC-V Wally machine interface -+ * Modified from VirtIO model -+ * -+ * Copyright (c) 2017 SiFive, Inc. -+ * *** What should we say for copyright? -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2 or later, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef HW_RISCV_WALLY_H -+#define HW_RISCV_WALLY_H -+ -+#include "hw/riscv/riscv_hart.h" -+#include "hw/sysbus.h" -+#include "qom/object.h" -+ -+#define WALLY_CPUS_MAX 8 -+#define WALLY_SOCKETS_MAX 8 -+ -+#define TYPE_RISCV_WALLY_MACHINE MACHINE_TYPE_NAME("wally") -+typedef struct WallyState WallyState; -+DECLARE_INSTANCE_CHECKER(WallyState, RISCV_WALLY_MACHINE, -+ TYPE_RISCV_WALLY_MACHINE) -+ -+struct WallyState { -+ /*< private >*/ -+ MachineState parent; -+ -+ /*< public >*/ -+ RISCVHartArrayState soc[WALLY_SOCKETS_MAX]; -+ DeviceState *plic[WALLY_SOCKETS_MAX]; -+ -+ int fdt_size; -+ bool have_aclint; -+}; -+ -+enum { -+ WALLY_MROM, -+ WALLY_CLINT, -+ WALLY_PLIC, -+ WALLY_UART0, -+ WALLY_DRAM, -+}; -+ -+enum { -+ UART0_IRQ = 10, -+ WALLYIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ -+}; -+ -+#define WALLY_PLIC_NUM_SOURCES 127 -+#define WALLY_PLIC_NUM_PRIORITIES 7 -+#define WALLY_PLIC_PRIORITY_BASE 0x04 -+#define WALLY_PLIC_PENDING_BASE 0x1000 -+#define WALLY_PLIC_ENABLE_BASE 0x2000 -+#define WALLY_PLIC_ENABLE_STRIDE 0x80 -+#define WALLY_PLIC_CONTEXT_BASE 0x200000 -+#define WALLY_PLIC_CONTEXT_STRIDE 0x1000 -+#define WALLY_PLIC_SIZE(__num_context) \ -+ (WALLY_PLIC_CONTEXT_BASE + (__num_context) * WALLY_PLIC_CONTEXT_STRIDE) -+ -+#define FDT_PCI_ADDR_CELLS 3 -+#define FDT_PCI_INT_CELLS 1 -+#define FDT_PLIC_ADDR_CELLS 0 -+#define FDT_PLIC_INT_CELLS 1 -+#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ -+ FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) -+ -+#endif --- -2.27.0 - diff --git a/tests/linux-testgen/buildroot-config-src/busybox.config b/linux/buildroot-config-src/busybox.config similarity index 100% rename from tests/linux-testgen/buildroot-config-src/busybox.config rename to linux/buildroot-config-src/busybox.config diff --git a/tests/linux-testgen/buildroot-config-src/linux.config b/linux/buildroot-config-src/linux.config similarity index 100% rename from tests/linux-testgen/buildroot-config-src/linux.config rename to linux/buildroot-config-src/linux.config diff --git a/tests/linux-testgen/buildroot-config-src/main.config b/linux/buildroot-config-src/main.config similarity index 98% rename from tests/linux-testgen/buildroot-config-src/main.config rename to linux/buildroot-config-src/main.config index 438d3f368..060c8892e 100644 --- a/tests/linux-testgen/buildroot-config-src/main.config +++ b/linux/buildroot-config-src/main.config @@ -1,8 +1,13 @@ # # Automatically generated file; DO NOT EDIT. -# Buildroot -g73f9753-dirty Configuration +# Buildroot 2021.05 Configuration # BR2_HAVE_DOT_CONFIG=y +BR2_HOST_GCC_AT_LEAST_4_9=y +BR2_HOST_GCC_AT_LEAST_5=y +BR2_HOST_GCC_AT_LEAST_6=y +BR2_HOST_GCC_AT_LEAST_7=y +BR2_HOST_GCC_AT_LEAST_8=y # # Target options @@ -101,7 +106,6 @@ BR2_ENABLE_DEBUG=y # BR2_DEBUG_1 is not set # BR2_DEBUG_2 is not set BR2_DEBUG_3=y -# BR2_ENABLE_RUNTIME_DEBUG is not set # BR2_STRIP_strip is not set # BR2_OPTIMIZE_0 is not set # BR2_OPTIMIZE_1 is not set @@ -165,11 +169,9 @@ BR2_KERNEL_HEADERS_AS_KERNEL=y # BR2_KERNEL_HEADERS_5_10 is not set # BR2_KERNEL_HEADERS_5_11 is not set # BR2_KERNEL_HEADERS_5_12 is not set -# BR2_KERNEL_HEADERS_5_13 is not set # BR2_KERNEL_HEADERS_VERSION is not set # BR2_KERNEL_HEADERS_CUSTOM_TARBALL is not set # BR2_KERNEL_HEADERS_CUSTOM_GIT is not set -# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_13 is not set # BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_12 is not set # BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_11 is not set BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_10=y @@ -250,7 +252,6 @@ BR2_BINUTILS_EXTRA_CONFIG_OPTIONS="" # BR2_GCC_VERSION_8_X is not set # BR2_GCC_VERSION_9_X is not set BR2_GCC_VERSION_10_X=y -# BR2_GCC_VERSION_11_X is not set BR2_GCC_VERSION="10.3.0" BR2_EXTRA_GCC_CONFIG_OPTIONS="" # BR2_TOOLCHAIN_BUILDROOT_CXX is not set @@ -368,10 +369,7 @@ BR2_TARGET_GENERIC_PASSWD_METHOD="sha-256" BR2_INIT_BUSYBOX=y # BR2_INIT_SYSV is not set # BR2_INIT_OPENRC is not set - -# -# systemd needs a glibc toolchain w/ SSP, headers >= 3.10, host and target gcc >= 5 -# +# BR2_INIT_SYSTEMD is not set # BR2_INIT_NONE is not set # BR2_ROOTFS_DEVICE_CREATION_STATIC is not set BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y @@ -656,7 +654,6 @@ BR2_PACKAGE_GDB_ARCH_SUPPORTS=y # BR2_PACKAGE_IOZONE is not set # BR2_PACKAGE_KTAP is not set # BR2_PACKAGE_LATENCYTOP is not set -# BR2_PACKAGE_LIBBPF is not set # BR2_PACKAGE_LMBENCH is not set BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y # BR2_PACKAGE_LTP_TESTSUITE is not set @@ -668,7 +665,6 @@ BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y # BR2_PACKAGE_NETSNIFF_NG is not set # BR2_PACKAGE_NMON is not set # BR2_PACKAGE_PAX_UTILS is not set -# BR2_PACKAGE_POKE is not set # BR2_PACKAGE_PV is not set # BR2_PACKAGE_RAMSMP is not set # BR2_PACKAGE_RAMSPEED is not set @@ -950,10 +946,6 @@ BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y # apitrace needs a toolchain w/ C++, wchar, dynamic library, threads, gcc >= 4.9 # -# -# mupdf needs a toolchain w/ C++, gcc >= 4.8 -# - # # vte needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 # @@ -1161,10 +1153,6 @@ BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y # BR2_PACKAGE_USB_MODESWITCH is not set # BR2_PACKAGE_USB_MODESWITCH_DATA is not set -# -# usbguard needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 -# - # # usbmount requires udev to be enabled # @@ -1185,24 +1173,19 @@ BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_ERLANG_ARCH_SUPPORTS=y # BR2_PACKAGE_EXECLINE is not set # BR2_PACKAGE_FICL is not set -# BR2_PACKAGE_GUILE is not set # BR2_PACKAGE_HASERL is not set # BR2_PACKAGE_JANET is not set # BR2_PACKAGE_JIMTCL is not set # BR2_PACKAGE_LUA is not set BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua" # BR2_PACKAGE_MICROPYTHON is not set -# BR2_PACKAGE_MOARVM is not set BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y # BR2_PACKAGE_PERL is not set # BR2_PACKAGE_PHP is not set # BR2_PACKAGE_PYTHON is not set # BR2_PACKAGE_PYTHON3 is not set - -# -# quickjs needs a glibc or musl toolchain w/ gcc >= 4.9, host gcc >= 4.9, dynamic library -# +# BR2_PACKAGE_QUICKJS is not set # BR2_PACKAGE_RUBY is not set # BR2_PACKAGE_TCL is not set @@ -1928,7 +1911,6 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y # czmq needs a toolchain w/ C++, threads # # BR2_PACKAGE_DAQ is not set -# BR2_PACKAGE_DAQ3 is not set # BR2_PACKAGE_DAVICI is not set # BR2_PACKAGE_ENET is not set @@ -2024,7 +2006,6 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y # # libpjsip needs a toolchain w/ C++, threads # -# BR2_PACKAGE_LIBPSL is not set # BR2_PACKAGE_LIBRELP is not set # BR2_PACKAGE_LIBRSYNC is not set # BR2_PACKAGE_LIBSHAIRPLAY is not set @@ -2167,7 +2148,6 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y # # bctoolbox needs a toolchain w/ C++, threads # -# BR2_PACKAGE_BDWGC is not set # # belr needs a toolchain w/ threads, C++ @@ -2260,8 +2240,6 @@ BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y # libabseil-cpp needs a toolchain w/ gcc >= 4.9, C++, threads, dynamic library # # BR2_PACKAGE_LIBARGTABLE2 is not set -BR2_PACKAGE_LIBATOMIC_OPS_ARCH_SUPPORTS=y -# BR2_PACKAGE_LIBATOMIC_OPS is not set # BR2_PACKAGE_LIBAVL is not set # BR2_PACKAGE_LIBB64 is not set # BR2_PACKAGE_LIBBACKTRACE is not set @@ -2317,7 +2295,6 @@ BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y # BR2_PACKAGE_LIBPTHREAD_STUBS is not set # BR2_PACKAGE_LIBPTHSEM is not set # BR2_PACKAGE_LIBPWQUALITY is not set -# BR2_PACKAGE_LIBQB is not set # # libsigc++ needs a toolchain w/ C++, gcc >= 4.8 @@ -3063,7 +3040,6 @@ BR2_PACKAGE_INITSCRIPTS=y # # sdbusplus needs systemd and a toolchain w/ C++, gcc >= 7 # -# BR2_PACKAGE_SEATD is not set # BR2_PACKAGE_SMACK is not set # @@ -3147,7 +3123,6 @@ BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y # BR2_PACKAGE_HOST_ANDROID_TOOLS is not set # BR2_PACKAGE_HOST_ASN1C is not set # BR2_PACKAGE_HOST_BABELTRACE2 is not set -# BR2_PACKAGE_HOST_BMAP_TOOLS is not set # BR2_PACKAGE_HOST_BTRFS_PROGS is not set # BR2_PACKAGE_HOST_CHECKPOLICY is not set # BR2_PACKAGE_HOST_CHECKSEC is not set @@ -3155,12 +3130,10 @@ BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y # BR2_PACKAGE_HOST_CRAMFS is not set # BR2_PACKAGE_HOST_CRYPTSETUP is not set # BR2_PACKAGE_HOST_DBUS_PYTHON is not set - -# -# host dfu-util needs a toolchain w/ host gcc >= 4.9 -# +# BR2_PACKAGE_HOST_DFU_UTIL is not set # BR2_PACKAGE_HOST_DOS2UNIX is not set # BR2_PACKAGE_HOST_DOSFSTOOLS is not set +# BR2_PACKAGE_HOST_DOXYGEN is not set # BR2_PACKAGE_HOST_DTC is not set BR2_PACKAGE_HOST_E2FSPROGS=y # BR2_PACKAGE_HOST_E2TOOLS is not set @@ -3197,10 +3170,7 @@ BR2_PACKAGE_HOST_KMOD=y # BR2_PACKAGE_HOST_MTD is not set # BR2_PACKAGE_HOST_MTOOLS is not set # BR2_PACKAGE_HOST_ODB is not set - -# -# host openocd needs a toolchain w/ host gcc >= 4.9 -# +# BR2_PACKAGE_HOST_OPENOCD is not set # BR2_PACKAGE_HOST_OPKG_UTILS is not set # BR2_PACKAGE_HOST_PARTED is not set BR2_PACKAGE_HOST_PATCHELF=y @@ -3225,10 +3195,7 @@ BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y # BR2_PACKAGE_HOST_QEMU_LINUX_USER_MODE is not set # BR2_PACKAGE_HOST_QEMU_VDE2 is not set # BR2_PACKAGE_HOST_QEMU_VIRTFS is not set - -# -# USB passthrough support needs a toolchain w/ host gcc >= 4.9 -# +# BR2_PACKAGE_HOST_QEMU_USB is not set # BR2_PACKAGE_HOST_QORIQ_RCW is not set # BR2_PACKAGE_HOST_RAUC is not set BR2_PACKAGE_HOST_RUSTC_ARCH_SUPPORTS=y diff --git a/linux/buildroot-scripts/start-buildroot-session.sh b/linux/buildroot-scripts/start-buildroot-session.sh new file mode 100755 index 000000000..f93815b6c --- /dev/null +++ b/linux/buildroot-scripts/start-buildroot-session.sh @@ -0,0 +1,80 @@ +script_dir=$(readlink -f ./) +personal_config=$(readlink -f ../buildroot-config-src) +shared_config=$RISCV/buildroot-config-src + +if [ -d "$shared_config" ]; then + echo "Hold the horses, friend!" >&2 + echo "There is already a buildroot-config-src folder in \$RISCV" >&2 + if [ ! -f "$shared_config/.owner" ]; then + echo "Oy vey -- it was improperly created too!" >&2 + echo "I see no .owner file in it!" >&2 + echo "Maybe just delete it." >&2 + exit 1 + fi + owner=$(cat $shared_config/.owner) + echo "It was created by $owner." >&2 + echo "Please contact them before overwriting their source files." >&2 + exit 1 +fi +echo "Starting new buildroot session" +# Copy configs to shared location +echo "Elevate permissions to copy ../buildroot-config-src to \$RISCV" +sudo cp -r "$personal_config" "$shared_config" +sudo chown -R cad $shared_config +# Document who created these configs +whoami>.owner +sudo mv .owner $shared_config +# Copy over main.config +echo "Copying main.config to buildroot/.config." +sudo cp $shared_config/main.config $RISCV/buildroot/.config +sudo chown cad $RISCV/buildroot/.config + +echo "==============================================" +echo "I'm about to sign you in as cad." +echo "" +echo "You can go straight to the \$RISCV/buildroot" +echo "and run \`make\` if you want." +echo "" +echo "You can also run:" +echo " * \`make menuconfig\`" +echo " * \`make linux-menuconfig\`" +echo " * \`make busybox-menuconfig\`" +echo "but if you do, you have to make extra certain" +echo "that you LOAD and SAVE configs from/to " +echo "\$RISCV/buildroot-config-src." +echo "" +echo "Run \`exit\` to sign out when you are done." +echo "And then any configs that were modified in" +echo "\$RISCV/buildroot-config-src will be copied" +echo "back to ../buildroot-config-src." +echo "==============================================" +read -p "Press any key to sign in as cad" -n1 -s +echo "" +cd $RISCV +sudo su cad +cd $script_dir + +echo "" +echo "Ending buildroot session" +if [ ! -d "$shared_config" ]; then + echo "Warning: $shared_config has already been deleted." + exit 0 +fi +if [ ! -f "$shared_config/.owner" ]; then + echo "Oy vey -- no .owner file found.">&2 + echo "Not sure whether to delete $shared_config.">&2 + exit 1 +fi +owner=$(cat "$shared_config"/.owner) +if [ $owner != $(whoami) ]; then + echo "Whoah there! It seems $owner created $shared_config.">&2 + echo "Ask them before deleting their work.">&2 + exit 1 +fi +echo "Copying modified configs from \$RISCV/buildroot-config-src back to ../buildroot-config-src." +for file in $personal_config/*; do + file=$(basename $file) + cp $shared_config/$file $personal_config/$file +done +echo "Elevate permissions to remove personal configs from shared location." +sudo rm -r $shared_config diff --git a/linux/devicetree/debug/dumpdts.sh b/linux/devicetree/debug/dumpdts.sh new file mode 100755 index 000000000..70057a78f --- /dev/null +++ b/linux/devicetree/debug/dumpdts.sh @@ -0,0 +1,6 @@ +#!/bin/bash +machine=virt + +qemu-system-riscv64 -M $machine,dumpdtb=$machine.dtb -bios $RISCV/buildroot/output/images/fw_jump.elf + +dtc -I dtb -O dts $machine.dtb > $machine.dts diff --git a/linux/devicetree/virt-trimmed.dts b/linux/devicetree/virt-trimmed.dts new file mode 100644 index 000000000..b517c3de5 --- /dev/null +++ b/linux/devicetree/virt-trimmed.dts @@ -0,0 +1,75 @@ +/dts-v1/; + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "riscv-virtio-trimmed"; + model = "riscv-virtio-trimmed,qemu"; + + chosen { + linux,initrd-end = <0x85c43a00>; + linux,initrd-start = <0x84200000>; + bootargs = "root=/dev/vda ro"; + stdout-path = "/soc/uart@10000000"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0x989680>; + + cpu@0 { + phandle = <0x01>; + device_type = "cpu"; + reg = <0x00>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsu"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x02>; + }; + }; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; + + uart@10000000 { + interrupts = <0x0a>; + interrupt-parent = <0x03>; + clock-frequency = <0x384000>; + reg = <0x00 0x10000000 0x00 0x100>; + compatible = "ns16550a"; + }; + + plic@c000000 { + phandle = <0x03>; + riscv,ndev = <0x35>; + reg = <0x00 0xc000000 0x00 0x210000>; + interrupts-extended = <0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible = "sifive,plic-1.0.0\0riscv,plic0"; + #interrupt-cells = <0x01>; + #address-cells = <0x00>; + }; + + clint@2000000 { + interrupts-extended = <0x02 0x03 0x02 0x07>; + reg = <0x00 0x2000000 0x00 0x10000>; + compatible = "sifive,clint0\0riscv,clint0"; + }; + }; +}; diff --git a/linux/testvector-generation/genTrace.gdb b/linux/testvector-generation/genTrace.gdb new file mode 100755 index 000000000..e69e28ec5 --- /dev/null +++ b/linux/testvector-generation/genTrace.gdb @@ -0,0 +1,25 @@ +define genTrace + # Arguments + set $tcpPort=$arg0 + set $vmlinux=$arg1 + + # GDB config + set pagination off + set logging overwrite on + set logging redirect on + set confirm off + + # Connect to QEMU session + eval "target extended-remote :%d",$tcpPort + + # Symbol Files + eval "file %s",$vmlinux + + # Run until Linux login prompt + b do_idle + ignore 1 2 + c + + kill + q +end diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh new file mode 100755 index 000000000..82f9e48be --- /dev/null +++ b/linux/testvector-generation/genTrace.sh @@ -0,0 +1,43 @@ +#!/bin/bash +tcpPort=1234 +imageDir=$RISCV/buildroot/output/images +outDir=$RISCV/linux-testvectors +recordFile="$outDir/all.qemu" +traceFile="$outDir/all.txt" + +read -p "Warning: running this script will overwrite the contents of: + * $recordFile + * $traceFile +Would you like to proceed? (y/n) " -n 1 -r +echo +if [[ $REPLY =~ ^[Yy]$ ]] +then + # Create Output Directory + sudo mkdir -p $outDir + sudo chown cad $outDir + sudo touch $recordFile + sudo touch $traceFile + sudo chmod a+rw $recordFile + sudo chmod a+rw $traceFile + + # Compile Devicetree from Source + dtc -I dts -O dtb ../devicetree/virt-trimmed.dts > ../devicetree/virt-trimmed.dtb + + # QEMU Simulation + (qemu-system-riscv64 \ + -M virt -dtb ../devicetree/virt-trimmed.dtb \ + -nographic -serial /dev/null \ + -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ + -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \ + -d nochain,cpu,in_asm \ + -gdb tcp::$tcpPort -S \ + 2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py | ./remove_dup.awk > $traceFile) \ + & riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort \"$imageDir/vmlinux\"" + + # Cleanup + sudo chown cad $recordFile + sudo chown cad $traceFile + sudo chmod o-w $recordFile + sudo chmod o-w $traceFile +fi + diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py new file mode 100755 index 000000000..ab63330fd --- /dev/null +++ b/linux/testvector-generation/parseGDBtoTrace.py @@ -0,0 +1,220 @@ +#! /usr/bin/python3 +import sys, fileinput, re + +# Ross Thompson +# July 27, 2021 +# Rewrite of the linux trace parser. + + +InstrStartDelim = '=>' +InstrEndDelim = '-----' + +#InputFile = 'noparse.txt' +#InputFile = sys.stdin +#InputFile = 'temp.txt' +#OutputFile = 'parsedAll.txt' + +HUMAN_READABLE = False + +def toDict(lst): + 'Converts the list of register values to a dictionary' + dct= {} + for item in lst: + regTup = item.split() + dct[regTup[0]] = int(regTup[2], 10) + del dct['pc'] + return dct + +def whichClass(text, Regs): + 'Which instruction class?' + #print(text, Regs) + if text[0:2] == 'ld' or text[0:2] == 'lw' or text[0:2] == 'lh' or text[0:2] == 'lb': + return ('load', WhatAddr(text, Regs), None, WhatMemDestSource(text)) + elif text[0:2] == 'sd' or text[0:2] == 'sw' or text[0:2] == 'sh' or text[0:2] == 'sb': + return ('store', WhatAddr(text, Regs), WhatMemDestSource(text), None) + elif text[0:3] == 'amo': + return ('amo', WhatAddrAMO(text, Regs), WhatMemDestSource(text), WhatMemDestSource(text)) + elif text[0:2] == 'lr': + return ('lr', WhatAddrLR(text, Regs), None, WhatMemDestSource(text)) + elif text[0:2] == 'sc': + return ('sc', WhatAddrSC(text, Regs), WhatMemDestSource(text), None) + else: + return ('other', None, None, None) + +def whatChanged(dct0, dct1): + 'Compares two dictionaries of instrution registers and indicates which registers changed' + dct = {} + for key in dct0: + if (dct1[key] != dct0[key]): + dct[key] = dct1[key] + return dct + +def WhatMemDestSource(text): + ''''What is the destination register. Used to compute where the read data is + on a load or the write data on a store.''' + return text.split()[1].split(',')[0] + +def WhatAddr(text, Regs): + 'What is the data memory address?' + Imm = text.split(',')[1] + (Imm, Src) = Imm.split('(') + Imm = int(Imm.strip(), 10) + Src = Src.strip(')').strip() + RegVal = Regs[Src] + return Imm + RegVal + +def WhatAddrAMO(text, Regs): + 'What is the data memory address?' + Src = text.split('(')[1] + Src = Src.strip(')').strip() + return Regs[Src] + +def WhatAddrLR(text, Regs): + 'What is the data memory address?' + Src = text.split('(')[1] + Src = Src.strip(')').strip() + return Regs[Src] + +def WhatAddrSC(text, Regs): + 'What is the data memory address?' + Src = text.split('(')[1] + Src = Src.strip(')').strip() + return Regs[Src] + +def PrintInstr(instr, fp): + if instr[2] == None: + return + ChangedRegisters = instr[4] + GPR = '' + CSR = [] + for key in ChangedRegisters: + # filter out csr which are not checked. + if(key in RegNumber): + if(RegNumber[key] < 32): + # GPR + if(HUMAN_READABLE): + GPR = '{:-2d} {:016x}'.format(RegNumber[key], ChangedRegisters[key]) + else: + GPR = '{:d} {:x}'.format(RegNumber[key], ChangedRegisters[key]) + else: + if(HUMAN_READABLE): + CSR.extend([key, '{:016x}'.format(ChangedRegisters[key])]) + else: + CSR.extend([key, '{:x}'.format(ChangedRegisters[key])]) + + CSRStr = ' '.join(CSR) + + #print(instr) + + if (HUMAN_READABLE == True): + fp.write('{:016x} {:08x} {:25s}'.format(instr[0], instr[1], instr[2])) + if(len(GPR) != 0): + fp.write(' GPR {}'.format(GPR)) + if(instr[3] == 'load' or instr[3] == 'lr'): + fp.write(' MemR {:016x} {:016x} {:016x}'.format(instr[5], 0, instr[7])) + if(instr[3] == 'store'): + fp.write('\t\t\t MemW {:016x} {:016x} {:016x}'.format(instr[5], instr[6], 0)) + + if(len(CSR) != 0): + fp.write(' CSR {}'.format(CSRStr)) + else: + fp.write('{:x} {:x} {:s}'.format(instr[0], instr[1], instr[2].replace(' ', '_'))) + if(len(GPR) != 0): + fp.write(' GPR {}'.format(GPR)) + if(instr[3] == 'load' or instr[3] == 'lr'): + fp.write(' MemR {:x} {:x} {:x}'.format(instr[5], 0, instr[7])) + if(instr[3] == 'store'): + fp.write(' MemW {:x} {:x} {:x}'.format(instr[5], instr[6], 0)) + + if(len(CSR) != 0): + fp.write(' CSR {}'.format(CSRStr)) + fp.write('\n') + +# reg number +RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45} +# initial state +CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None] + +#with open (InputFile, 'r') as InputFileFP: +#lines = InputFileFP.readlines() +lineNum = 0 +StartLine = 0 +EndLine = 0 +numInstrs = 0 +#instructions = [] +MemAdr = 0 +lines = [] +interrupts=open('interrupts.txt','w') +interrupts.close() + +for line in fileinput.input('-'): + if line.startswith('riscv_cpu_do_interrupt'): + with open('interrupts.txt','a') as interrupts: + interrupts.write(str(numInstrs)+': '+line.strip('riscv_cpu_do_interrupt')) + break + lines.insert(lineNum, line) + if InstrStartDelim in line: + lineNum = 0 + StartLine = lineNum + elif InstrEndDelim in line: + EndLine = lineNum + (InstrBits, text) = lines[StartLine].split(':') + InstrBits = int(InstrBits.strip('=> '), 16) + text = text.strip() + PC = int(lines[StartLine+1].split(':')[0][2:], 16) + Regs = toDict(lines[StartLine+2:EndLine]) + (Class, Addr, WriteReg, ReadReg) = whichClass(text, Regs) + #print("CWR", Class, WriteReg, ReadReg) + PreviousInstr = CurrentInstr + + Changed = whatChanged(PreviousInstr[4], Regs) + + if (ReadReg !=None): ReadData = ReadReg + else: ReadData = None + + if (WriteReg !=None): WriteData = WriteReg + else: WriteData = None + + CurrentInstr = [PC, InstrBits, text, Class, Regs, Changed, Addr, WriteData, ReadData] + + #print(CurrentInstr[0:4], PreviousInstr[5], CurrentInstr[6:7], PreviousInstr[8]) + + # pc, instrbits, text and class come from the last line. + MoveInstrToRegWriteLst = PreviousInstr[0:4] + # updated registers come from the current line. + MoveInstrToRegWriteLst.append(CurrentInstr[5]) # destination regs + # memory address if present comes from the last line. + MoveInstrToRegWriteLst.append(PreviousInstr[6]) # MemAdrM + # write data from the previous line + #MoveInstrToRegWriteLst.append(PreviousInstr[7]) # WriteDataM + + if (PreviousInstr[7] != None): + MoveInstrToRegWriteLst.append(Regs[PreviousInstr[7]]) # WriteDataM + else: + MoveInstrToRegWriteLst.append(None) + + # read data from the current line + #MoveInstrToRegWriteLst.append(PreviousInstr[8]) # ReadDataM + if (PreviousInstr[8] != None): + MoveInstrToRegWriteLst.append(Regs[PreviousInstr[8]]) # ReadDataM + else: + MoveInstrToRegWriteLst.append(None) + + lines.clear() + #instructions.append(MoveInstrToRegWriteLst) + PrintInstr(MoveInstrToRegWriteLst, sys.stdout) + numInstrs +=1 + if (numInstrs % 1e4 == 0): + sys.stderr.write('Trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n') + sys.stderr.flush() + lineNum += 1 + + +#for instruction in instructions[1::]: + + +#with open(OutputFile, 'w') as OutputFileFP: +# print('opened file') + + + diff --git a/linux/testvector-generation/parseQemuToGDB.py b/linux/testvector-generation/parseQemuToGDB.py new file mode 100755 index 000000000..932761db7 --- /dev/null +++ b/linux/testvector-generation/parseQemuToGDB.py @@ -0,0 +1,148 @@ +#! /usr/bin/python3 +import fileinput, sys + +sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n") +parseState = "idle" +beginPageFault = 0 +inPageFault = 0 +endPageFault = 0 +CSRs = {} +pageFaultCSRs = {} +regs = {} +pageFaultRegs = {} +instrs = {} +instrCount = 0 +returnAdr = 0 + +def printPC(l): + global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, instrCount + if not inPageFault: + inst = l.split() + if len(inst) > 3: + print(f'=> {inst[1]}:\t{inst[2]} {inst[3]}') + else: + print(f'=> {inst[1]}:\t{inst[2]}') + print(f'{inst[0]} 0x{inst[1]}') + instrCount += 1 + if ((instrCount % 100000) == 0): + sys.stderr.write("QEMU parser reached "+str(instrCount)+" instrs\n") + +def printCSRs(): + global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs + if not inPageFault: + for (csr,val) in CSRs.items(): + print('{}{}{:#x} {}'.format(csr, ' '*(15-len(csr)), val, val)) + print('-----') + +def parseCSRs(l): + global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs + if l.strip() and (not l.startswith("Disassembler")) and (not l.startswith("Please")): + # If we've hit the register file + if l.startswith(' x0/zero'): + parseState = "regFile" + if not inPageFault: + instr = instrs[CSRs["pc"]] + printPC(instr) + parseRegs(l) + # If we've hit a CSR + else: + csr = l.split()[0] + val = int(l.split()[1],16) + # Commented out this conditional because the pageFault instrs don't corrupt CSRs + #if inPageFault: + # Not sure if these CSRs should be updated or not during page fault. + #if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"): + # We do update some CSRs + # CSRs[csr] = val + #else: + # Others we preserve until changed later + # pageFaultCSRs[csr] = val + #elif pageFaultCSRs and (csr in pageFaultCSRs): + # if (val != pageFaultCSRs[csr]): + # del pageFaultCSRs[csr] + # CSRs[csr] = val + #else: + # CSRs[csr] = val + # + # However SEPC and STVAL do get corrupted upon exiting + if endPageFault and ((csr == 'sepc') or (csr == 'stval')): + CSRs[csr] = returnAdr + pageFaultCSRs[csr] = val + elif pageFaultCSRs and (csr in pageFaultCSRs): + if (val != pageFaultCSRs[csr]): + del pageFaultCSRs[csr] + CSRs[csr] = val + else: + CSRs[csr] = val + +def parseRegs(l): + global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, pageFaultRegs + if "pc" in l: + printCSRs() + # New non-disassembled instruction + parseState = "CSRs" + parseCSRs(l) + elif l.startswith('--------'): + # End of disassembled instruction + printCSRs() + parseState = "idle" + else: + s = l.split() + for i in range(0,len(s),2): + if '/' in s[i]: + reg = s[i].split('/')[1] + val = int(s[i+1], 16) + if inPageFault: + pageFaultRegs[reg] = val + else: + if pageFaultRegs and (reg in pageFaultRegs): + if (val != pageFaultRegs[reg]): + del pageFaultRegs[reg] + regs[reg] = val + else: + regs[reg] = val + val = regs[reg] + print('{}{}{:#x} {}'.format(reg, ' '*(15-len(reg)), val, val)) + else: + sys.stderr.write("Whoops. Expected a list of reg file regs; got:\n"+l) + +############# +# Main Code # +############# +interrupt_line="" +for l in fileinput.input(): + #sys.stderr.write(l) + if l.startswith('riscv_cpu_do_interrupt'): + sys.stderr.write(l) + interrupt_line = l.strip('\n') + continue + elif l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'): + break + elif l.startswith('IN:'): + # New disassembled instr + if len(interrupt_line)>0: + print(interrupt_line) + interrupt_line="" + parseState = "instr" + elif (parseState == "instr") and l.startswith('0x'): + # New instruction + if len(interrupt_line)>0: + print(interrupt_line) + interrupt_line="" + if "out of bounds" in l: + sys.stderr.write("Detected QEMU page fault error\n") + beginPageFault = not inPageFault + if beginPageFault: + returnAdr = int(l.split()[0][2:-1], 16) + sys.stderr.write('Saving SEPC of '+hex(returnAdr)+'\n') + inPageFault = 1 + else: + endPageFault = inPageFault + inPageFault = 0 + adr = int(l.split()[0][2:-1], 16) + instrs[adr] = l + parseState = "CSRs" + elif parseState == "CSRs": + parseCSRs(l) + elif parseState == "regFile": + parseRegs(l) diff --git a/linux/testvector-generation/remove_dup.awk b/linux/testvector-generation/remove_dup.awk new file mode 100755 index 000000000..7963d76a6 --- /dev/null +++ b/linux/testvector-generation/remove_dup.awk @@ -0,0 +1,20 @@ +#!/usr/bin/awk -f + +BEGIN{ + old = "first" +} + +{ + if($1 != old){ + if(old != "first"){ + print oldAll + } + } + old=$1 + oldAll=$0 +} + +END{ + print oldAll +} + diff --git a/linux/wallyVirtIO.patch b/linux/wallyVirtIO.patch deleted file mode 100644 index 76a1d240e..000000000 --- a/linux/wallyVirtIO.patch +++ /dev/null @@ -1,542 +0,0 @@ -diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c -index 4a3cd2599a..39b46e3122 100644 ---- a/hw/riscv/virt.c -+++ b/hw/riscv/virt.c -@@ -20,6 +20,7 @@ - - #include "qemu/osdep.h" - #include "qemu/units.h" -+#include "qemu/log.h" - #include "qemu/error-report.h" - #include "qapi/error.h" - #include "hw/boards.h" -@@ -44,19 +45,10 @@ - #include "hw/display/ramfb.h" - - static const MemMapEntry virt_memmap[] = { -- [VIRT_DEBUG] = { 0x0, 0x100 }, - [VIRT_MROM] = { 0x1000, 0xf000 }, -- [VIRT_TEST] = { 0x100000, 0x1000 }, -- [VIRT_RTC] = { 0x101000, 0x1000 }, - [VIRT_CLINT] = { 0x2000000, 0x10000 }, -- [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, - [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, - [VIRT_UART0] = { 0x10000000, 0x100 }, -- [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, -- [VIRT_FW_CFG] = { 0x10100000, 0x18 }, -- [VIRT_FLASH] = { 0x20000000, 0x4000000 }, -- [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, -- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, - [VIRT_DRAM] = { 0x80000000, 0x0 }, - }; - -@@ -67,139 +59,23 @@ static const MemMapEntry virt_memmap[] = { - /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ - #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) - --static MemMapEntry virt_high_pcie_memmap; -- - #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) - --static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, -- const char *name, -- const char *alias_prop_name) --{ -- /* -- * Create a single flash device. We use the same parameters as -- * the flash devices on the ARM virt board. -- */ -- DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); -- -- qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); -- qdev_prop_set_uint8(dev, "width", 4); -- qdev_prop_set_uint8(dev, "device-width", 2); -- qdev_prop_set_bit(dev, "big-endian", false); -- qdev_prop_set_uint16(dev, "id0", 0x89); -- qdev_prop_set_uint16(dev, "id1", 0x18); -- qdev_prop_set_uint16(dev, "id2", 0x00); -- qdev_prop_set_uint16(dev, "id3", 0x00); -- qdev_prop_set_string(dev, "name", name); -- -- object_property_add_child(OBJECT(s), name, OBJECT(dev)); -- object_property_add_alias(OBJECT(s), alias_prop_name, -- OBJECT(dev), "drive"); -- -- return PFLASH_CFI01(dev); --} -- --static void virt_flash_create(RISCVVirtState *s) --{ -- s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); -- s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); --} -- --static void virt_flash_map1(PFlashCFI01 *flash, -- hwaddr base, hwaddr size, -- MemoryRegion *sysmem) --{ -- DeviceState *dev = DEVICE(flash); -- -- assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); -- assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); -- qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); -- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -- -- memory_region_add_subregion(sysmem, base, -- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), -- 0)); --} -- --static void virt_flash_map(RISCVVirtState *s, -- MemoryRegion *sysmem) --{ -- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; -- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; -- -- virt_flash_map1(s->flash[0], flashbase, flashsize, -- sysmem); -- virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, -- sysmem); --} -- --static void create_pcie_irq_map(void *fdt, char *nodename, -- uint32_t plic_phandle) --{ -- int pin, dev; -- uint32_t -- full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; -- uint32_t *irq_map = full_irq_map; -- -- /* This code creates a standard swizzle of interrupts such that -- * each device's first interrupt is based on it's PCI_SLOT number. -- * (See pci_swizzle_map_irq_fn()) -- * -- * We only need one entry per interrupt in the table (not one per -- * possible slot) seeing the interrupt-map-mask will allow the table -- * to wrap to any number of devices. -- */ -- for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { -- int devfn = dev * 0x8; -- -- for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { -- int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); -- int i = 0; -- -- irq_map[i] = cpu_to_be32(devfn << 8); -- -- i += FDT_PCI_ADDR_CELLS; -- irq_map[i] = cpu_to_be32(pin + 1); -- -- i += FDT_PCI_INT_CELLS; -- irq_map[i++] = cpu_to_be32(plic_phandle); -- -- i += FDT_PLIC_ADDR_CELLS; -- irq_map[i] = cpu_to_be32(irq_nr); -- -- irq_map += FDT_INT_MAP_WIDTH; -- } -- } -- -- qemu_fdt_setprop(fdt, nodename, "interrupt-map", -- full_irq_map, sizeof(full_irq_map)); -- -- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", -- 0x1800, 0, 0, 0x7); --} -- - static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) - { - void *fdt; -- int i, cpu, socket; -+ //int i, cpu, socket; -+ int cpu, socket; - MachineState *mc = MACHINE(s); - uint64_t addr, size; - uint32_t *clint_cells, *plic_cells; - unsigned long clint_addr, plic_addr; - uint32_t plic_phandle[MAX_NODES]; -- uint32_t cpu_phandle, intc_phandle, test_phandle; -+ uint32_t cpu_phandle, intc_phandle; - uint32_t phandle = 1, plic_mmio_phandle = 1; -- uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; - char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; -- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; -- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; -- static const char * const clint_compat[2] = { -- "sifive,clint0", "riscv,clint0" -- }; -- static const char * const plic_compat[2] = { -- "sifive,plic-1.0.0", "riscv,plic0" -- }; - - if (mc->dtb) { - fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); -@@ -305,8 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - (memmap[VIRT_CLINT].size * socket); - clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(fdt, clint_name); -- qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", -- (char **)&clint_compat, ARRAY_SIZE(clint_compat)); -+ qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, clint_name, "reg", - 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", -@@ -322,8 +197,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, plic_name, - "#interrupt-cells", FDT_PLIC_INT_CELLS); -- qemu_fdt_setprop_string_array(fdt, plic_name, "compatible", -- (char **)&plic_compat, ARRAY_SIZE(plic_compat)); -+ qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); - qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", - plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); -@@ -342,95 +216,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - for (socket = 0; socket < riscv_socket_count(mc); socket++) { - if (socket == 0) { - plic_mmio_phandle = plic_phandle[socket]; -- plic_virtio_phandle = plic_phandle[socket]; -- plic_pcie_phandle = plic_phandle[socket]; -- } -- if (socket == 1) { -- plic_virtio_phandle = plic_phandle[socket]; -- plic_pcie_phandle = plic_phandle[socket]; -- } -- if (socket == 2) { -- plic_pcie_phandle = plic_phandle[socket]; - } - } - - riscv_socket_fdt_write_distance_matrix(mc, fdt); - -- for (i = 0; i < VIRTIO_COUNT; i++) { -- name = g_strdup_printf("/soc/virtio_mmio@%lx", -- (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, -- 0x0, memmap[VIRT_VIRTIO].size); -- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", -- plic_virtio_phandle); -- qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); -- g_free(name); -- } -- -- name = g_strdup_printf("/soc/pci@%lx", -- (long) memmap[VIRT_PCIE_ECAM].base); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); -- qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); -- qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); -- qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); -- qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); -- qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); -- qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, -- memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); -- qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); -- qemu_fdt_setprop_cells(fdt, name, "reg", 0, -- memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); -- qemu_fdt_setprop_sized_cells(fdt, name, "ranges", -- 1, FDT_PCI_RANGE_IOPORT, 2, 0, -- 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, -- 1, FDT_PCI_RANGE_MMIO, -- 2, memmap[VIRT_PCIE_MMIO].base, -- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, -- 1, FDT_PCI_RANGE_MMIO_64BIT, -- 2, virt_high_pcie_memmap.base, -- 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); -- -- create_pcie_irq_map(fdt, name, plic_pcie_phandle); -- g_free(name); -- -- test_phandle = phandle++; -- name = g_strdup_printf("/soc/test@%lx", -- (long)memmap[VIRT_TEST].base); -- qemu_fdt_add_subnode(fdt, name); -- { -- static const char * const compat[3] = { -- "sifive,test1", "sifive,test0", "syscon" -- }; -- qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat, -- ARRAY_SIZE(compat)); -- } -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_TEST].base, -- 0x0, memmap[VIRT_TEST].size); -- qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); -- test_phandle = qemu_fdt_get_phandle(fdt, name); -- g_free(name); -- -- name = g_strdup_printf("/soc/reboot"); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); -- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); -- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); -- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); -- g_free(name); -- -- name = g_strdup_printf("/soc/poweroff"); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); -- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); -- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); -- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); -- g_free(name); -- - name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); -@@ -445,102 +235,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); - g_free(name); - -- name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_RTC].base, -- 0x0, memmap[VIRT_RTC].size); -- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); -- qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); -- g_free(name); -- -- name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); -- qemu_fdt_add_subnode(mc->fdt, name); -- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); -- qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", -- 2, flashbase, 2, flashsize, -- 2, flashbase + flashsize, 2, flashsize); -- qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); -- g_free(name); -- - update_bootargs: - if (cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } - } - --static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, -- hwaddr ecam_base, hwaddr ecam_size, -- hwaddr mmio_base, hwaddr mmio_size, -- hwaddr high_mmio_base, -- hwaddr high_mmio_size, -- hwaddr pio_base, -- DeviceState *plic) --{ -- DeviceState *dev; -- MemoryRegion *ecam_alias, *ecam_reg; -- MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; -- qemu_irq irq; -- int i; -- -- dev = qdev_new(TYPE_GPEX_HOST); -- -- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -- -- ecam_alias = g_new0(MemoryRegion, 1); -- ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); -- memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", -- ecam_reg, 0, ecam_size); -- memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); -- -- mmio_alias = g_new0(MemoryRegion, 1); -- mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); -- memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", -- mmio_reg, mmio_base, mmio_size); -- memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); -- -- /* Map high MMIO space */ -- high_mmio_alias = g_new0(MemoryRegion, 1); -- memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", -- mmio_reg, high_mmio_base, high_mmio_size); -- memory_region_add_subregion(get_system_memory(), high_mmio_base, -- high_mmio_alias); -- -- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); -- -- for (i = 0; i < GPEX_NUM_IRQS; i++) { -- irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); -- -- sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); -- gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); -- } -- -- return dev; --} -- --static FWCfgState *create_fw_cfg(const MachineState *mc) --{ -- hwaddr base = virt_memmap[VIRT_FW_CFG].base; -- hwaddr size = virt_memmap[VIRT_FW_CFG].size; -- FWCfgState *fw_cfg; -- char *nodename; -- -- fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, -- &address_space_memory); -- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); -- -- nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); -- qemu_fdt_add_subnode(mc->fdt, nodename); -- qemu_fdt_setprop_string(mc->fdt, nodename, -- "compatible", "qemu,fw-cfg-mmio"); -- qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", -- 2, base, 2, size); -- qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); -- g_free(nodename); -- return fw_cfg; --} -- - static void virt_machine_init(MachineState *machine) - { - const MemMapEntry *memmap = virt_memmap; -@@ -554,7 +254,7 @@ static void virt_machine_init(MachineState *machine) - target_ulong firmware_end_addr, kernel_start_addr; - uint32_t fdt_load_addr; - uint64_t kernel_entry; -- DeviceState *mmio_plic, *virtio_plic, *pcie_plic; -+ DeviceState *mmio_plic; - int i, j, base_hartid, hart_count; - - /* Check socket count limit */ -@@ -565,7 +265,7 @@ static void virt_machine_init(MachineState *machine) - } - - /* Initialize sockets */ -- mmio_plic = virtio_plic = pcie_plic = NULL; -+ mmio_plic = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { - if (!riscv_socket_check_hartids(machine, i)) { - error_report("discontinuous hartids in socket%d", i); -@@ -634,15 +334,6 @@ static void virt_machine_init(MachineState *machine) - /* Try to use different PLIC instance based device type */ - if (i == 0) { - mmio_plic = s->plic[i]; -- virtio_plic = s->plic[i]; -- pcie_plic = s->plic[i]; -- } -- if (i == 1) { -- virtio_plic = s->plic[i]; -- pcie_plic = s->plic[i]; -- } -- if (i == 2) { -- pcie_plic = s->plic[i]; - } - } - -@@ -654,13 +345,6 @@ static void virt_machine_init(MachineState *machine) - error_report("Limiting RAM size to 10 GiB"); - } - #endif -- virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; -- virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; -- } else { -- virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; -- virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; -- virt_high_pcie_memmap.base = -- ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); - } - - /* register system main memory (actual RAM) */ -@@ -681,10 +365,12 @@ static void virt_machine_init(MachineState *machine) - - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr = riscv_find_and_load_firmware(machine, -- RISCV32_BIOS_BIN, start_addr, NULL); -+ "opensbi-riscv32-generic-fw_dynamic.bin", -+ start_addr, NULL); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, -- RISCV64_BIOS_BIN, start_addr, NULL); -+ "opensbi-riscv64-generic-fw_dynamic.bin", -+ start_addr, NULL); - } - - if (machine->kernel_filename) { -@@ -712,21 +398,6 @@ static void virt_machine_init(MachineState *machine) - kernel_entry = 0; - } - -- if (drive_get(IF_PFLASH, 0, 0)) { -- /* -- * Pflash was supplied, let's overwrite the address we jump to after -- * reset to the base of the flash. -- */ -- start_addr = virt_memmap[VIRT_FLASH].base; -- } -- -- /* -- * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device -- * tree cannot be altered and we get FDT_ERR_NOSPACE. -- */ -- s->fw_cfg = create_fw_cfg(machine); -- rom_set_fw(s->fw_cfg); -- - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); -@@ -736,41 +407,10 @@ static void virt_machine_init(MachineState *machine) - virt_memmap[VIRT_MROM].size, kernel_entry, - fdt_load_addr, machine->fdt); - -- /* SiFive Test MMIO device */ -- sifive_test_create(memmap[VIRT_TEST].base); -- -- /* VirtIO MMIO devices */ -- for (i = 0; i < VIRTIO_COUNT; i++) { -- sysbus_create_simple("virtio-mmio", -- memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, -- qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); -- } -- -- gpex_pcie_init(system_memory, -- memmap[VIRT_PCIE_ECAM].base, -- memmap[VIRT_PCIE_ECAM].size, -- memmap[VIRT_PCIE_MMIO].base, -- memmap[VIRT_PCIE_MMIO].size, -- virt_high_pcie_memmap.base, -- virt_high_pcie_memmap.size, -- memmap[VIRT_PCIE_PIO].base, -- DEVICE(pcie_plic)); -- -- serial_mm_init(system_memory, memmap[VIRT_UART0].base, -+ serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, - serial_hd(0), DEVICE_LITTLE_ENDIAN); - -- sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, -- qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); -- -- virt_flash_create(s); -- -- for (i = 0; i < ARRAY_SIZE(s->flash); i++) { -- /* Map legacy -drive if=pflash to machine properties */ -- pflash_cfi01_legacy_drive(s->flash[i], -- drive_get(IF_PFLASH, 0, i)); -- } -- virt_flash_map(s, system_memory); - } - - static void virt_machine_instance_init(Object *obj) -diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c -index 991a6bb760..401028b8d9 100644 ---- a/target/riscv/cpu.c -+++ b/target/riscv/cpu.c -@@ -269,6 +269,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); -+ - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - } diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index d88ec28ac..1bdea74a7 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -29,8 +29,6 @@ `define FPGA 1 `define QEMU 1 -`define BUILDROOT 1 -`define BUSYBEAR 0 `define LINUX_FIX_READ {'h10000005} `define LINUX_TEST_VECTORS "../../tests/linux-testgen/linux-testvectors/" // RV32 or RV64: XLEN = 32 or 64 @@ -50,11 +48,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 1 -`define MEM_IROM 0 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 +`define DMEM `MEM_CACHE +`define IMEM `MEM_CACHE +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -66,7 +62,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 @@ -129,3 +124,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/busybear/wally-config.vh b/pipelined/config/busybear/wally-config.vh deleted file mode 100644 index 38cc37211..000000000 --- a/pipelined/config/busybear/wally-config.vh +++ /dev/null @@ -1,135 +0,0 @@ -////////////////////////////////////////// -// busybear-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 1 -`define LINUX_FIX_READ {'h10000005} -`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/" -//`define LINUX_TEST_VECTORS "../../../busybear_boot/" -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -`define MISA (32'h0014112D) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define ZICOUNTERS_SUPPORTED 1 -`define COUNTERS 32 -`define DESIGN_COMPILER 0 - -// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 1 -`define MEM_IROM 0 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 2048 -`define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 -`define ICACHE_NUMWAYS 1 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 - -// Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 64'h0000000000001000 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -`define BOOTROM_SUPPORTED 1'b1 -//`define BOOTROM_BASE 56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -//`define BOOTROM_RANGE 56'h00003FFF -`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Bus Interface width -`define AHBW 64 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 - -// Hardware configuration -//`define UART_PRESCALE 1 -`define UART_PRESCALE 0 - -// Interrupt configuration -`define PLIC_NUM_SRC 53 -`define PLIC_UART_ID 4 - -`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt" -`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE -`define BPRED_ENABLED 1 - - - diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 85cf1fda3..223aa3d80 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -29,11 +29,8 @@ `define FPGA 1 `define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 `define DESIGN_COMPILER 0 -//`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/" // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 @@ -50,11 +47,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 1 -`define MEM_IROM 0 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 +`define DMEM `MEM_CACHE +`define IMEM `MEM_CACHE +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -66,7 +61,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 @@ -136,3 +130,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 1 + +`define REPLAY 0 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index e6f26a101..9102cf637 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -29,8 +29,6 @@ `define FPGA 0 `define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 `define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 @@ -41,21 +39,20 @@ // E `define MISA (32'h00000010) -`define ZICSR_SUPPORTED 1 +`define ZICSR_SUPPORTED 0 `define ZIFENCEI_SUPPORTED 0 -`define COUNTERS 32 +`define COUNTERS 0 `define ZICOUNTERS_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 0 -`define MEM_IROM 0 -`define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 +// *** replace with MEM_BUS +`define DMEM `MEM_BUS +`define IMEM `MEM_BUS +`define VIRTMEM_SUPPORTED 0 +`define VECTORED_INTERRUPTS_SUPPORTED 0 // TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 0 @@ -66,14 +63,13 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +`define DIV_BITSPERCYCLE 1 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 0 @@ -93,16 +89,16 @@ `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 +`define CLINT_SUPPORTED 1'b0 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 +`define GPIO_SUPPORTED 1'b0 `define GPIO_BASE 34'h10060000 `define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 +`define UART_SUPPORTED 1'b0 `define UART_BASE 34'h10000000 `define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 +`define PLIC_SUPPORTED 1'b0 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF `define SDC_SUPPORTED 1'b0 @@ -129,6 +125,8 @@ `define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" `define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" -`define BPRED_ENABLED 1 +`define BPRED_ENABLED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/rv32etim/BTBPredictor.txt b/pipelined/config/rv32etim/BTBPredictor.txt deleted file mode 100644 index fd3eedffb..000000000 --- a/pipelined/config/rv32etim/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 diff --git a/pipelined/config/rv32etim/twoBitPredictor.txt b/pipelined/config/rv32etim/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv32etim/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv32etim/wally-config.vh b/pipelined/config/rv32etim/wally-config.vh deleted file mode 100644 index 58e31d2cd..000000000 --- a/pipelined/config/rv32etim/wally-config.vh +++ /dev/null @@ -1,134 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 -`define DESIGN_COMPILER 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -// E, M, C -`define MISA (32'h00001014) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 0 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 - -// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 1 -`define MEM_DCACHE 0 -`define MEM_IROM 1 -`define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 0 -`define DTLB_ENTRIES 0 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 - -// Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 1 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 32'h80000000 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h000000FF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h000003FF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 34'h80000000 -`define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 34'h02000000 -`define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 34'h10060000 -`define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 34'h10000000 -`define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 34'h0C000000 -`define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 34'h00012100 -`define SDC_RANGE 34'h0000001F - -// Bus Interface width -`define AHBW 32 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 4 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 - -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" -`define BPRED_ENABLED 0 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 1f3f3c0a7..af6ef40cf 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -29,8 +29,6 @@ `define FPGA 0 `define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 `define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 @@ -49,11 +47,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 1 -`define MEM_IROM 0 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 +`define DMEM `MEM_CACHE +`define IMEM `MEM_CACHE +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -65,7 +61,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 @@ -75,7 +70,7 @@ `define DIV_BITSPERCYCLE 4 // Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 +`define PMP_ENTRIES 64 // Address space `define RESET_VECTOR 32'h80000000 @@ -131,3 +126,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 21c307a80..4d7b0418a 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -29,8 +29,6 @@ `define FPGA 0 `define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 `define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 @@ -49,11 +47,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 0 -`define MEM_IROM 0 -`define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 +`define DMEM `MEM_TIM +`define IMEM `MEM_TIM +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -65,7 +61,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 @@ -95,13 +90,13 @@ `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 +`define GPIO_SUPPORTED 1'b0 `define GPIO_BASE 34'h10060000 `define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 +`define UART_SUPPORTED 1'b0 `define UART_BASE 34'h10000000 `define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 +`define PLIC_SUPPORTED 1'b0 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF `define SDC_SUPPORTED 1'b0 @@ -131,3 +126,5 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 + +`define REPLAY 0 diff --git a/pipelined/config/rv32tim/BTBPredictor.txt b/pipelined/config/rv32tim/BTBPredictor.txt deleted file mode 100644 index fd3eedffb..000000000 --- a/pipelined/config/rv32tim/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 diff --git a/pipelined/config/rv32tim/twoBitPredictor.txt b/pipelined/config/rv32tim/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv32tim/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv32tim/wally-config.vh b/pipelined/config/rv32tim/wally-config.vh deleted file mode 100644 index d1ecb3756..000000000 --- a/pipelined/config/rv32tim/wally-config.vh +++ /dev/null @@ -1,133 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 -`define DESIGN_COMPILER 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -`define MISA (32'h00000104) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 0 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 - -// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 1 -`define MEM_DCACHE 0 -`define MEM_IROM 1 -`define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 0 -`define DTLB_ENTRIES 0 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 - -// Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 32'h80000000 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 34'h80000000 -`define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 34'h02000000 -`define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 34'h10060000 -`define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 34'h10000000 -`define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 34'h0C000000 -`define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 34'h00012100 -`define SDC_RANGE 34'h0000001F - -// Bus Interface width -`define AHBW 32 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 4 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 - -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" -`define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 68d9696ed..f8ee8903b 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -30,8 +30,6 @@ // RV32 or RV64: XLEN = 32 or 64 `define FPGA 0 `define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 `define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 @@ -51,11 +49,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 1 -`define MEM_IROM 0 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 +`define DMEM `MEM_CACHE +`define IMEM `MEM_CACHE +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -67,7 +63,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 @@ -134,3 +129,5 @@ //`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE `define TESTSBP 1 + +`define REPLAY 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index cfe363216..ea17620c3 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -29,8 +29,6 @@ `define FPGA 0 `define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 `define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 @@ -50,11 +48,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 1 -`define MEM_IROM 0 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 +`define DMEM `MEM_CACHE +`define IMEM `MEM_CACHE +`define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 @@ -66,7 +62,6 @@ `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 @@ -135,3 +130,4 @@ `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define REPLAY 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index a532fc04b..ec497db2a 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -29,8 +29,6 @@ `define FPGA 0 `define QEMU 0 -`define BUILDROOT 0 -`define BUSYBEAR 0 `define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 @@ -42,31 +40,28 @@ // MISA RISC-V configuration per specification `define MISA (32'h00000104) `define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 +`define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 +`define ZICOUNTERS_SUPPORTED 0 // Microarchitectural Features `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DTIM 0 -`define MEM_DCACHE 1 -`define MEM_IROM 0 -`define MEM_ICACHE 1 -`define MEM_VIRTMEM 1 +`define DMEM `MEM_TIM +`define IMEM `MEM_TIM +`define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 +`define ITLB_ENTRIES 0 +`define DTLB_ENTRIES 0 // Cache configuration. Sizes should be a power of two // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_LINELENINBITS 256 -`define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_LINELENINBITS 256 @@ -76,7 +71,7 @@ `define DIV_BITSPERCYCLE 4 // Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 64 +`define PMP_ENTRIES 0 // Address space `define RESET_VECTOR 64'h0000000080000000 @@ -135,3 +130,4 @@ `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define REPLAY 0 diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh index 99269ae5b..de934ee32 100644 --- a/pipelined/config/shared/wally-constants.vh +++ b/pipelined/config/shared/wally-constants.vh @@ -50,3 +50,7 @@ `define SV39 8 `define SV48 9 +`define MEM_BUS 1 +`define MEM_TIM 2 +`define MEM_CACHE 3 + diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile index 8bcb403c7..610571691 100644 --- a/pipelined/regression/Makefile +++ b/pipelined/regression/Makefile @@ -11,29 +11,36 @@ make all: # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # Also delete bin/exe2memfile at that point - make -C ../../tests/imperas-riscv-tests - make -C ../../tests/imperas-riscv-tests XLEN=64 - cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf + make -C ../../tests/imperas-riscv-tests --jobs + make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs + #cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf + #cd ../../tests/imperas-riscv-tests; extractFunctionRadix.sh work/*/*.elf.objdump # Build riscv-arch-test 64 and 32-bit versions - make -C ../../addins/riscv-arch-test - make -C ../../addins/riscv-arch-test XLEN=32 - cd ../../addins/riscv-arch-test; elf2hex.sh + make -C ../../addins/riscv-arch-test --jobs + make -C ../../addins/riscv-arch-test XLEN=32 --jobs + #cd ../../addins/riscv-arch-test; elf2hex.sh + #cd ../../addins/riscv-arch-test; extractFunctionRadix.sh work/*/*/*.elf.objdump # extractFunctionRadix. *** # Build wally-riscv-arch-test - make -C ../../tests/wally-riscv-arch-test/ - make -C ../../tests/wally-riscv-arch-test/ XLEN=32 - cd ../../tests/wally-riscv-arch-test; elf2hex.sh + make -C ../../tests/wally-riscv-arch-test/ --jobs + make -C ../../tests/wally-riscv-arch-test/ XLEN=32 --jobs + +# build the memfiles and address files. + make -f makefile-memfile wally-sim-files --jobs + #cd ../../tests/wally-riscv-arch-test; elf2hex.sh + #cd ../../tests/wally-riscv-arch-test; extractFunctionRadix.sh work/*/*/*.elf.objdump # ***extractFunctionRadix # Only compile Imperas tests if they are installed locally. # They are usually a symlink to $RISCV/imperas-riscv-tests and only # get compiled there manually during installation - # make -C ../../addins/imperas-riscv-tests - # make -C ../../addins/imperas-riscv-tests XLEN=64 - # cd ../../addins/imperas-riscv-tests; elf2hex.sh + #make -C ../../addins/imperas-riscv-tests + #make -C ../../addins/imperas-riscv-tests XLEN=64 + #cd ../../addins/imperas-riscv-tests; elf2hex.sh + #cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump # Link Linux test vectors (fix this later***) #cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index 14185e707..53c80c17a 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -178,55 +178,55 @@ add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/i add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/BlockReplacementBits add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/genblk1/cachereplacementpolicy/EncVicWay add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/VictimWay -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/SetValid} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/ValidBits} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/WriteWordEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/ValidBits} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/SetValid} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/ValidBits} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/SetValid} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/DirtyBits} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/ValidBits} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/SetValid} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/ValidBits} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/WriteWordEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/ValidBits} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/SetValid} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/ValidBits} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/SetValid} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/DirtyBits} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/ValidBits} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/CacheWays[3]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/controller/NextState add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/ITLBMissF add wave -noupdate -group icache /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/ITLBWriteF @@ -290,81 +290,81 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipeline add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirty add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VDWriteEnableWay add wave -noupdate -group lsu -expand -group dcache /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WriteWordEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetValid add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearValid add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetDirty add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemWay[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/ReadTag} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/WayHit add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockWayMaskedM add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordM diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 5968cb4df..564973a39 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv64gc rv32gc rv32ic; do +for config in rv32e rv64gc rv32gc rv32ic ; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index a9f9e3b2e..e2df4436c 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -226,85 +226,85 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/IgnoreRequest -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetValid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ClearDirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/VDWriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WriteWordEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ClearDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/VDWriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetValid add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearValid add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/RAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WayHit} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Valid} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag diff --git a/pipelined/regression/makefile-memfile b/pipelined/regression/makefile-memfile new file mode 100644 index 000000000..030cf8d57 --- /dev/null +++ b/pipelined/regression/makefile-memfile @@ -0,0 +1,37 @@ +ROOT := ../.. +SUFFIX := work +ARCHDIR := $(ROOT)/addins/riscv-arch-test +WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test +IMPERASDIR := $(ROOT)/tests/imperas-riscv-tests +ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX) + +ELFFILES ?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf") +MEMFILES ?= $(ELFFILES:.elf=.elf.memfile) +ADDRFILES ?= $(ELFFILES:.elf=.elf.objdump.addr) + +print: + echo "files in $(ALLDIRS) are $(ELFFILES)." + echo "memfiles are $(MEMFILES)" + +.PHONY: all wally-sim-files +all: wally-sim-files + +wally-sim-files: $(MEMFILES) $(ADDRFILES) + echo "$@" + +# notes to self on how this works. +# The find command locates all of the *.elf files in directory DIR1. A list of .memfiles and +# .addr files are generated from the .elf. These are used as targets. +# % is a wildcard in a make target which is then referenced as % in the depenecies and $* +# in the recipe. +# because elf2hex requires a bit width we use findstring to figure out if the compiled directory +# is XLEN=64 or 32. This is hacky and will likely break in the future. +# the .addr is a separate target so make can split into more jobs and more parallism. +%.elf.memfile: %.elf + riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@ + +%.elf.objdump.addr: %.elf.objdump + extractFunctionRadix.sh $< + +.PHONY: clean +clean: diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index fb4aa4c76..a35684b32 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -48,17 +48,17 @@ def getBuildrootTC(short): INSTR_LIMIT = 100000 # multiple of 100000 MAX_EXPECTED = 246000000 if short: - BRcmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c <" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work-buildroot] { - vdel -all -lib work-buildroot -} -vlib work-buildroot - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt -vlog -lint +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - - -# start and run simulation -vopt work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt - -vsim workopt -suppress 8852,12070 - -run -all -run -all -exec ./slack-notifier/slack-notifier.py -quit diff --git a/pipelined/regression/wally-buildroot.do b/pipelined/regression/wally-buildroot.do deleted file mode 100644 index 2ef745477..000000000 --- a/pipelined/regression/wally-buildroot.do +++ /dev/null @@ -1,44 +0,0 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work-buildroot] { - vdel -all -lib work-buildroot -} -vlib work-buildroot - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt -vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt +acc work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt - -vsim workopt -suppress 8852,12070 - -#-- Run the Simulation -run -all -do linux-wave.do -add log -recursive /* -run -all - -exec ./slack-notifier/slack-notifier.py -#quit diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 30abbd7b4..25dc23d7b 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -32,19 +32,31 @@ vlib work_${1}_${2} # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32ic rv32ic -vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 +if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation + vopt work_${1}_${2}.testbench -work work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070 -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt -vsim -lib work_${1}_${2} testbenchopt -# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time -#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf -#vsim -coverage -lib work_$2 workopt_$2 + run -all + run -all + exec ./slack-notifier/slack-notifier.py + quit +} else { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + # start and run simulation + # remove +acc flag for faster sim during regressions if there is no need to access internal signals + vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt + # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time + #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf + #vsim -coverage -lib work_$2 workopt_$2 + + run -all + quit +} -run -all #coverage report -file wally-pipelined-coverage.txt # These aren't doing anything helpful #coverage report -memory #profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 -quit diff --git a/pipelined/regression/wally-pipelined-tim-batch.do b/pipelined/regression/wally-pipelined-tim-batch.do deleted file mode 100644 index cc9b1c251..000000000 --- a/pipelined/regression/wally-pipelined-tim-batch.do +++ /dev/null @@ -1,50 +0,0 @@ -# wally-pipelined-batch.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Usage: do wally-pipelined-batch.do -# Example: do wally-pipelined-batch.do rv32ic imperas-32i - -# Use this wally-pipelined-batch.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined-batch.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined-batch.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work_${1}_${2}] { - vdel -lib work_${1}_${2} -all -} -vlib work_${1}_${2} - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined-batch.do ../config/rv32ic rv32ic -vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt -vsim -lib work_${1}_${2} testbenchopt -# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time -#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf -#vsim -coverage -lib work_$2 workopt_$2 - -run -all -#coverage report -file wally-pipelined-coverage.txt -# These aren't doing anything helpful -#coverage report -memory -#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 -quit diff --git a/pipelined/regression/wally-pipelined-tim.do b/pipelined/regression/wally-pipelined-tim.do deleted file mode 100644 index f8244f40e..000000000 --- a/pipelined/regression/wally-pipelined-tim.do +++ /dev/null @@ -1,56 +0,0 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -#switch $argc { -# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -#} -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -vopt +acc work.testbench -G TEST=$2 -o workopt -vsim workopt - -view wave --- display input and output signals as hexidecimal values -#do ./wave-dos/peripheral-waves.do -add log -recursive /* -do wave.do - --- Run the Simulation -#run 3600 -run -all -#quit -#noview ../testbench/testbench-imperas.sv -noview ../testbench/testbench.sv -view wave diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index 620e72257..db84feb41 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -29,28 +29,41 @@ vlib work # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -#switch $argc { -# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -#} # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -vopt +acc work.testbench -G TEST=$2 -o workopt -vsim workopt +if {$2 eq "buildroot"} { + vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -view wave --- display input and output signals as hexidecimal values -#do ./wave-dos/peripheral-waves.do -add log -recursive /* -do wave.do --- Run the Simulation -#run 3600 -run -all -#quit -#noview ../testbench/testbench-imperas.sv -noview ../testbench/testbench.sv -view wave + # start and run simulation + # remove +acc flag for faster sim during regressions if there is no need to access internal signals + vopt +acc work.testbench -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o workopt + + vsim workopt -suppress 8852,12070 + + #-- Run the Simulation + run -all + do linux-wave.do + add log -recursive /* + run -all + + exec ./slack-notifier/slack-notifier.py + } else { + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt + + vsim workopt +nowarn3829 + + view wave + #-- display input and output signals as hexidecimal values + #do ./wave-dos/peripheral-waves.do + add log -recursive /* + do wave.do + + #-- Run the Simulation + #run 3600 + run -all + noview ../testbench/testbench.sv + view wave +} + diff --git a/pipelined/regression/wave-coremark.do b/pipelined/regression/wave-coremark.do index 4c1a77472..cf8837237 100644 --- a/pipelined/regression/wave-coremark.do +++ b/pipelined/regression/wave-coremark.do @@ -178,18 +178,18 @@ add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/bus/icache/ add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/BasePAdrF add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/WayHit add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/VictimWay -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/SetValid} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/ifu/bus/icache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/ValidBits} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/MemWay[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/WriteEnable} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/SetValid} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/ValidBits} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/controller/NextState add wave -noupdate -group icache /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/ITLBWriteF @@ -245,81 +245,81 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus. add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SelAdrM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/ReadDataBlockM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheMemWriteData -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WriteWordEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetValid add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearValid add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetDirty add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/MemWay[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/MemWay[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/MemWay[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/MemWay[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ReadTag} add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/WayHit add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataBlockWayMaskedM add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordM diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 743148967..27c079768 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -1,9 +1,9 @@ onerror {resume} -quietly virtual function -install /testbench/dut/core/ifu -env /testbench/dut/core/ifu { &{/testbench/dut/core/ifu/BPPredWrongM, /testbench/dut/core/ifu/InvalidateICacheM }} temp quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext +add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM @@ -55,6 +55,7 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName @@ -118,10 +119,7 @@ add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredPCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/SelBPPredF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf @@ -193,129 +191,129 @@ add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu.bus.dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMLineWriteEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWordWriteEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWayWriteEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWordEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMLineWayWriteEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMLineWriteEnable +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMWordWriteEnable +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMWayWriteEnable +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMWordEnable +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SRAMLineWayWriteEnable +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/SelReplayCPURequest add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/RAdrD} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ClearDirty} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ClearDirtyD} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu.bus.dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirty} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyD} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ClearDirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/VDWriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/MemWay[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/RW -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/NextAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/Atomic -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheStall +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WriteWordEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValid} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearDirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/VDWriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/WayHit} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheFetchLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheWriteLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/WayHit +add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheMemWriteData +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE @@ -437,7 +435,7 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/MEPC_REGW add wave -noupdate /testbench/dut/core/lsu/bus/busdp/LocalLSUBusAdr add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheFetchLine add wave -noupdate /testbench/dut/core/lsu/bus/busdp/busfsm/DCacheWriteLine -add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -expand -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusRead add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAdr add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAck @@ -478,7 +476,7 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE - add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {3836 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} +WaveRestoreCursors {{Cursor 7} {6451242 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -494,4 +492,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {3733 ns} {4093 ns} +WaveRestoreZoom {593782 ns} {7438712 ns} diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index e10979f27..f70467f4a 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -28,234 +28,189 @@ // OR OTHER DEALINGS IN THE SOFTWARE. //////////////////////////////////////////////////////////////////////////////////////////////// - `include "wally-config.vh" -module cache #(parameter integer LINELEN, - parameter integer NUMLINES, - parameter integer NUMWAYS, - parameter integer DCACHE = 1) - (input logic clk, - input logic reset, +module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( + input logic clk, + input logic reset, // cpu side - input logic CPUBusy, - input logic [1:0] RW, - input logic [1:0] Atomic, - input logic FlushCache, - input logic InvalidateCacheM, - input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. - input logic [`PA_BITS-1:0] PAdr, // physical address - input logic [`XLEN-1:0] FinalWriteData, - output logic [`XLEN-1:0] ReadDataWord, - output logic CacheCommitted, - output logic CacheStall, - + input logic CPUBusy, + input logic [1:0] RW, + input logic [1:0] Atomic, + input logic FlushCache, + input logic InvalidateCacheM, + input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. + input logic [`PA_BITS-1:0] PAdr, // physical address + input logic [`XLEN-1:0] FinalWriteData, + output logic CacheCommitted, + output logic CacheStall, // to performance counters to cpu - output logic CacheMiss, - output logic CacheAccess, - + output logic CacheMiss, + output logic CacheAccess, + output logic save, restore, // lsu control - input logic IgnoreRequest, - + input logic IgnoreRequest, // Bus fsm interface - output logic CacheFetchLine, - output logic CacheWriteLine, - input logic CacheBusAck, + output logic CacheFetchLine, + output logic CacheWriteLine, + input logic CacheBusAck, + output logic [`PA_BITS-1:0] CacheBusAdr, + input logic [LINELEN-1:0] CacheMemWriteData, + output logic [LINELEN-1:0] ReadDataLine); - output logic [`PA_BITS-1:0] CacheBusAdr, - input logic [LINELEN-1:0] CacheMemWriteData, - output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0]); - - - localparam integer LINEBYTELEN = LINELEN/8; - localparam integer OFFSETLEN = $clog2(LINEBYTELEN); - localparam integer INDEXLEN = $clog2(NUMLINES); - localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; - localparam integer WORDSPERLINE = LINELEN/`XLEN; - localparam integer LOGWPL = $clog2(WORDSPERLINE); - localparam integer LOGXLENBYTES = $clog2(`XLEN/8); - - localparam integer FlushAdrThreshold = NUMLINES - 1; + // Cache parameters + localparam LINEBYTELEN = LINELEN/8; + localparam OFFSETLEN = $clog2(LINEBYTELEN); + localparam SETLEN = $clog2(NUMLINES); + localparam SETTOP = SETLEN+OFFSETLEN; + localparam TAGLEN = `PA_BITS - SETTOP; + localparam WORDSPERLINE = LINELEN/`XLEN; + localparam LOGWPL = $clog2(WORDSPERLINE); + localparam LOGXLENBYTES = $clog2(`XLEN/8); + localparam FlushAdrThreshold = NUMLINES - 1; logic [1:0] SelAdr; - logic [INDEXLEN-1:0] RAdr; + logic [SETLEN-1:0] RAdr; logic [LINELEN-1:0] SRAMWriteData; logic SetValid, ClearValid; logic SetDirty, ClearDirty; - logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; + logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit; logic CacheHit; - logic [LINELEN-1:0] ReadDataLine; logic [WORDSPERLINE-1:0] SRAMWordEnable; - logic SRAMWordWriteEnable; logic SRAMLineWriteEnable; logic [NUMWAYS-1:0] SRAMLineWayWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable; - - + logic [NUMWAYS-1:0] SRAMWordWayWriteEnable; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; logic VictimDirty; - logic [2**LOGWPL-1:0] MemPAdrDecoded; - logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0]; logic [TAGLEN-1:0] VictimTag; - - logic [INDEXLEN-1:0] FlushAdr; - logic [INDEXLEN-1:0] FlushAdrP1; + logic [SETLEN-1:0] FlushAdr; + logic [SETLEN-1:0] FlushAdrP1; logic FlushAdrCntEn; logic FlushAdrCntRst; logic FlushAdrFlag; - logic FlushWayFlag; - + logic FlushWayFlag; logic [NUMWAYS-1:0] FlushWay; logic [NUMWAYS-1:0] NextFlushWay; logic FlushWayCntEn; logic FlushWayCntRst; - - logic VDWriteEnable; logic SelEvict; logic LRUWriteEn; - logic [NUMWAYS-1:0] VDWriteEnableWay; logic SelFlush; + logic ResetOrFlushAdr, ResetOrFlushWay; + logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw; + logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved; + logic [NUMWAYS-1:0] SelectedWay; + logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; + + ///////////////////////////////////////////////////////////////////////////////////////////// + // Read Path + ///////////////////////////////////////////////////////////////////////////////////////////// - // Read Path CPU (IEU) side - - mux3 #(INDEXLEN) - AdrSelMux(.d0(NextAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d1(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d2(FlushAdr), - .s(SelAdr), - .y(RAdr)); - - - - cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN), - .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) - MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, - .PAdr(PAdr), - .WriteEnable(SRAMWayWriteEnable), - .VDWriteEnable(VDWriteEnableWay), - .WriteWordEnable(SRAMWordEnable), - .TagWriteEnable(SRAMLineWayWriteEnable), - .WriteData(SRAMWriteData), - .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, - .VictimWay, .FlushWay, .SelFlush, - .ReadDataLineWayMasked, - .WayHit, .VictimDirtyWay, .VictimTagWay, - .InvalidateAll(InvalidateCacheM)); + // Choose read address (RAdr). Normally use NextAdr, but use PAdr during stalls + // and FlushAdr when handling D$ flushes + mux3 #(SETLEN) AdrSelMux( + .d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr), + .s(SelAdr), .y(RAdr)); + // Array of cache ways, along with victim, hit, dirty, and read merging logic + cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( + .clk, .reset, .RAdr, .PAdr, + .SRAMWayWriteEnable, + .SRAMWordEnable, + .TagWriteEnable(SRAMLineWayWriteEnable), + .WriteData(SRAMWriteData), + .SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay), + .SelEvict, .Victim(VictimWay), .Flush(FlushWay), + .SelFlush, + .SelectedReadDataLine(ReadDataLineWay), .WayHit(WayHitRaw), .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay), + .InvalidateAll(InvalidateCacheM)); if(NUMWAYS > 1) begin:vict - cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) - cachereplacementpolicy(.clk, .reset, - .WayHit, - .VictimWay, - .PAdr(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .RAdr, - .LRUWriteEn); - end else begin:vict - assign VictimWay = 1'b1; // one hot. - end - + cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( + .clk, .reset, .WayHit, .VictimWay, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .RAdr, .LRUWriteEn); + end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | WayHit; assign VictimDirty = | VictimDirtyWay; - - - // ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways. + // ReadDataLineWay is a 2d array of cache line len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. - or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLine)); - or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); + or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine)); + or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); - // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can - // easily build a variable input mux. - genvar index; - if(DCACHE == 1) begin: readdata - for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux - assign ReadDataLineSets[index] = ReadDataLine[((index+1)*`XLEN)-1: (index*`XLEN)]; - end - // variable input mux - assign ReadDataWord = ReadDataLineSets[PAdr[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]]; - end else begin: readdata - logic [31:0] ReadLineSetsF [LINELEN/16-1:0]; - logic [31:0] FinalInstrRawF; - for(index = 0; index < LINELEN / 16 - 1; index++) - assign ReadLineSetsF[index] = ReadDataLine[((index+1)*16)+16-1 : (index*16)]; - assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLine[LINELEN-1:LINELEN-16]}; - assign FinalInstrRawF = ReadLineSetsF[PAdr[$clog2(LINELEN / 32) + 1 : 1]]; - if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF}; - else assign ReadDataWord = FinalInstrRawF; - end - - // Write Path CPU (IEU) side - - onehotdecoder #(LOGWPL) - adrdec(.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), - .decoded(MemPAdrDecoded)); - - assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; + // Because of the sram clocked read when the ieu is stalled the read data maybe lost. + // There are two ways to resolve. 1. We can replay the read of the sram or we can save + // the data. Replay is eaiser but creates a longer critical path. + // save/restore only wayhit and readdata. + if(!`REPLAY) begin + flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved); + mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit); + end else assign WayHit = WayHitRaw; - assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; + ///////////////////////////////////////////////////////////////////////////////////////////// + // Write Path: Write Enables + ///////////////////////////////////////////////////////////////////////////////////////////// + + // *** Ross considering restructuring + // move decoder and wordwritenable into cacheway. + onehotdecoder #(LOGWPL) adrdec( + .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); + assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; // OR + - mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnable ? WayHit : '0), - .d1(VictimWay), - .s(SRAMLineWriteEnable), - .y(SRAMWayWriteEnable)); - - - + assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; // AND + assign SRAMWordWayWriteEnable = SRAMWordWriteEnable ? WayHit : '0; // AND + mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWayWriteEnable), .d1(VictimWay), + .s(SRAMLineWriteEnable), .y(SRAMWayWriteEnable)); mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), - .d1(CacheMemWriteData), - .s(SRAMLineWriteEnable), - .y(SRAMWriteData)); + .d1(CacheMemWriteData), .s(SRAMLineWriteEnable), .y(SRAMWriteData)); + mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), + .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), + .s({SelFlush, SelEvict}), + .y(CacheBusAdr)); - - mux3 #(`PA_BITS) BaseAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d1({VictimTag, PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), - .s({SelFlush, SelEvict}), - .y(CacheBusAdr)); + ///////////////////////////////////////////////////////////////////////////////////////////// + // Flush address and way generation during flush + ///////////////////////////////////////////////////////////////////////////////////////////// - - // flush address and way generation. - // increment on 2nd to last way - flopenr #(INDEXLEN) - FlushAdrReg(.clk, - .reset(reset | FlushAdrCntRst), - .en(FlushAdrCntEn), - .d(FlushAdrP1), - .q(FlushAdr)); + assign ResetOrFlushAdr = reset | FlushAdrCntRst; + flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), + .en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; + assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]); - - flopenl #(NUMWAYS) - FlushWayReg(.clk, - .load(reset | FlushWayCntRst), - .en(FlushWayCntEn), - .val({{NUMWAYS-1{1'b0}}, 1'b1}), - .d(NextFlushWay), - .q(FlushWay)); - - assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}}; - + assign ResetOrFlushWay = reset | FlushWayCntRst; + flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), + .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}), + .d(NextFlushWay), .q(FlushWay)); + assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; - //assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; - assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0]; - assign FlushWayFlag = FlushWay[NUMWAYS-1]; - - cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, - .RW, .Atomic, .CPUBusy, .IgnoreRequest, - .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, - .CacheMiss, .CacheAccess, .SelAdr, .SetValid, - .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable, - .SRAMLineWriteEnable, .SelEvict, .SelFlush, - .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, - .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, - .VDWriteEnable, .LRUWriteEn); + assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit); + assign SetValidWay = SetValid ? SelectedWay : '0; + assign ClearValidWay = ClearValid ? SelectedWay : '0; + assign SetDirtyWay = SetDirty ? SelectedWay : '0; + assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; -endmodule // dcache + ///////////////////////////////////////////////////////////////////////////////////////////// + // Cache FSM + ///////////////////////////////////////////////////////////////////////////////////////////// + + cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, + .RW, .Atomic, .CPUBusy, .IgnoreRequest, + .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, + .CacheMiss, .CacheAccess, .SelAdr, .SetValid, + .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable, + .SRAMLineWriteEnable, .SelEvict, .SelFlush, + .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, + .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, + .save, .restore, + .LRUWriteEn); +endmodule diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 7d4d2f77d..63c452862 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -32,56 +32,58 @@ module cachefsm (input logic clk, - input logic reset, + input logic reset, // inputs from IEU input logic [1:0] RW, input logic [1:0] Atomic, - input logic FlushCache, + input logic FlushCache, // hazard inputs - input logic CPUBusy, + input logic CPUBusy, // interlock fsm - input logic IgnoreRequest, + input logic IgnoreRequest, // Bus inputs - input logic CacheBusAck, + input logic CacheBusAck, // dcache internals - input logic CacheHit, - input logic VictimDirty, - input logic FlushAdrFlag, - input logic FlushWayFlag, + input logic CacheHit, + input logic VictimDirty, + input logic FlushAdrFlag, + input logic FlushWayFlag, // hazard outputs - output logic CacheStall, + output logic CacheStall, // counter outputs - output logic CacheMiss, - output logic CacheAccess, + output logic CacheMiss, + output logic CacheAccess, // Bus outputs - output logic CacheCommitted, - output logic CacheWriteLine, - output logic CacheFetchLine, + output logic CacheCommitted, + output logic CacheWriteLine, + output logic CacheFetchLine, // dcache internals output logic [1:0] SelAdr, - output logic SetValid, - output logic ClearValid, - output logic SetDirty, - output logic ClearDirty, - output logic SRAMWordWriteEnable, - output logic SRAMLineWriteEnable, - output logic SelEvict, - output logic LRUWriteEn, - output logic SelFlush, - output logic FlushAdrCntEn, - output logic FlushWayCntEn, - output logic FlushAdrCntRst, - output logic FlushWayCntRst, - output logic VDWriteEnable - - ); + output logic SetValid, + output logic ClearValid, + output logic SetDirty, + output logic ClearDirty, + output logic SRAMWordWriteEnable, + output logic SRAMLineWriteEnable, + output logic SelEvict, + output logic LRUWriteEn, + output logic SelFlush, + output logic FlushAdrCntEn, + output logic FlushWayCntEn, + output logic FlushAdrCntRst, + output logic FlushWayCntRst, + output logic save, + output logic restore); - logic AnyCPUReqM; logic [1:0] PreSelAdr; logic resetDelay; - + logic DoAMO, DoRead, DoWrite, DoFlush; + logic DoAMOHit, DoReadHit, DoWriteHit; + logic DoAMOMiss, DoReadMiss, DoWriteMiss; + logic FlushFlag; + typedef enum {STATE_READY, STATE_MISS_FETCH_WDV, @@ -103,11 +105,22 @@ module cachefsm (* mark_debug = "true" *) statetype CurrState, NextState; - assign AnyCPUReqM = |RW | (|Atomic); + assign DoFlush = FlushCache & ~IgnoreRequest; + assign DoAMO = Atomic[1] & (&RW) & ~IgnoreRequest; + assign DoAMOHit = DoAMO & CacheHit; + assign DoAMOMiss = DoAMOHit & ~CacheHit; + assign DoRead = RW[1] & ~IgnoreRequest; + assign DoReadHit = DoRead & CacheHit; + assign DoReadMiss = DoRead & ~CacheHit; + assign DoWrite = RW[0] & ~IgnoreRequest; + assign DoWriteHit = DoWrite & CacheHit; + assign DoWriteMiss = DoWrite & ~CacheHit; + + assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. - assign CacheAccess = AnyCPUReqM & CurrState == STATE_READY; - assign CacheMiss = CacheAccess & ~CacheHit; + assign CacheAccess = (DoAMO | DoRead | DoWrite) & CurrState == STATE_READY; + assign CacheMiss = CacheAccess & ~CacheHit; // special case on reset. When the fsm first exists reset the // PCNextF will no longer be pointing to the correct address. @@ -119,316 +132,113 @@ module cachefsm if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; - // next state logic and some state ouputs. always_comb begin - CacheStall = 1'b0; - PreSelAdr = 2'b00; - SetValid = 1'b0; - ClearValid = 1'b0; - SetDirty = 1'b0; - ClearDirty = 1'b0; - SRAMWordWriteEnable = 1'b0; - SRAMLineWriteEnable = 1'b0; - SelEvict = 1'b0; - LRUWriteEn = 1'b0; - SelFlush = 1'b0; - FlushAdrCntEn = 1'b0; - FlushWayCntEn = 1'b0; - FlushAdrCntRst = 1'b0; - FlushWayCntRst = 1'b0; - VDWriteEnable = 1'b0; NextState = STATE_READY; - CacheFetchLine = 1'b0; - CacheWriteLine = 1'b0; - case (CurrState) - STATE_READY: begin - - CacheStall = 1'b0; - PreSelAdr = 2'b00; - SRAMWordWriteEnable = 1'b0; - SetDirty = 1'b0; - LRUWriteEn = 1'b0; - - // TLB Miss - if(IgnoreRequest) begin - // the LSU arbiter has not yet selected the PTW. - // The CPU needs to be stalled until that happens. - // If we set CacheStall for 1 cycle before going to - // PTW ready the CPU will stall. - // The page table walker asserts it's control 1 cycle - // after the TLBs miss. - PreSelAdr = 2'b01; - NextState = STATE_READY; - end - - // Flush dcache to next level of memory - else if(FlushCache) begin - NextState = STATE_FLUSH; - FlushAdrCntRst = 1'b1; - FlushWayCntRst = 1'b1; - CacheStall = 1'b1; - end - - // amo hit - else if(Atomic[1] & (&RW) & CacheHit) begin - PreSelAdr = 2'b01; - CacheStall = 1'b0; - - if(CPUBusy) begin - NextState = STATE_CPU_BUSY_FINISH_AMO; - PreSelAdr = 2'b01; - end - else begin - SRAMWordWriteEnable = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_READY; - end - end - // read hit valid cached - else if(RW[1] & CacheHit) begin - CacheStall = 1'b0; - LRUWriteEn = 1'b1; - - if(CPUBusy) begin - NextState = STATE_CPU_BUSY; - PreSelAdr = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - // write hit valid cached - else if (RW[0] & CacheHit) begin - PreSelAdr = 2'b01; - CacheStall = 1'b0; - SRAMWordWriteEnable = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - - if(CPUBusy) begin - NextState = STATE_CPU_BUSY; - PreSelAdr = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - // read or write miss valid cached - else if((|RW) & ~CacheHit) begin - NextState = STATE_MISS_FETCH_WDV; - CacheStall = 1'b1; - CacheFetchLine = 1'b1; - end - else NextState = STATE_READY; - end - - STATE_MISS_FETCH_WDV: begin - CacheStall = 1'b1; - PreSelAdr = 2'b01; - - if (CacheBusAck) begin - NextState = STATE_MISS_FETCH_DONE; - end else begin - NextState = STATE_MISS_FETCH_WDV; - end - end - - STATE_MISS_FETCH_DONE: begin - CacheStall = 1'b1; - PreSelAdr = 2'b01; - if(VictimDirty) begin - NextState = STATE_MISS_EVICT_DIRTY; - CacheWriteLine = 1'b1; - end else begin - NextState = STATE_MISS_WRITE_CACHE_LINE; - end - end - - STATE_MISS_WRITE_CACHE_LINE: begin - SRAMLineWriteEnable = 1'b1; - CacheStall = 1'b1; - NextState = STATE_MISS_READ_WORD; - PreSelAdr = 2'b01; - SetValid = 1'b1; - ClearDirty = 1'b1; - //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write - end - - STATE_MISS_READ_WORD: begin - PreSelAdr = 2'b01; - CacheStall = 1'b1; - if (RW[0] & ~Atomic[1]) begin // handles stores and amo write. - NextState = STATE_MISS_WRITE_WORD; - end else begin - NextState = STATE_MISS_READ_WORD_DELAY; - // delay state is required as the read signal RW[1] is still high when we - // return to the ready state because the cache is stalling the cpu. - end - end - - STATE_MISS_READ_WORD_DELAY: begin - //PreSelAdr = 2'b01; - SRAMWordWriteEnable = 1'b0; - SetDirty = 1'b0; - LRUWriteEn = 1'b0; - if(&RW & Atomic[1]) begin // amo write - PreSelAdr = 2'b01; - if(CPUBusy) begin - NextState = STATE_CPU_BUSY_FINISH_AMO; - end - else begin - SRAMWordWriteEnable = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_READY; - end - end else begin - LRUWriteEn = 1'b1; - if(CPUBusy) begin - NextState = STATE_CPU_BUSY; - PreSelAdr = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - end - - STATE_MISS_WRITE_WORD: begin - SRAMWordWriteEnable = 1'b1; - SetDirty = 1'b1; - PreSelAdr = 2'b01; - LRUWriteEn = 1'b1; - if(CPUBusy) begin - NextState = STATE_CPU_BUSY; - PreSelAdr = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - - STATE_MISS_EVICT_DIRTY: begin - CacheStall = 1'b1; - PreSelAdr = 2'b01; - SelEvict = 1'b1; - if(CacheBusAck) begin - NextState = STATE_MISS_WRITE_CACHE_LINE; - end else begin - NextState = STATE_MISS_EVICT_DIRTY; - end - end - - - STATE_CPU_BUSY: begin - PreSelAdr = 2'b00; - if(CPUBusy) begin - NextState = STATE_CPU_BUSY; - PreSelAdr = 2'b01; - end - else begin - NextState = STATE_READY; - end - end - - STATE_CPU_BUSY_FINISH_AMO: begin - PreSelAdr = 2'b01; - SRAMWordWriteEnable = 1'b0; - SetDirty = 1'b0; - LRUWriteEn = 1'b0; - if(CPUBusy) begin - NextState = STATE_CPU_BUSY_FINISH_AMO; - end - else begin - SRAMWordWriteEnable = 1'b1; - SetDirty = 1'b1; - LRUWriteEn = 1'b1; - NextState = STATE_READY; - end - end - - STATE_FLUSH: begin - // intialize flush counters - SelFlush = 1'b1; - CacheStall = 1'b1; - PreSelAdr = 2'b10; - NextState = STATE_FLUSH_CHECK; - end - - STATE_FLUSH_CHECK: begin - CacheStall = 1'b1; - PreSelAdr = 2'b10; - SelFlush = 1'b1; - if(VictimDirty) begin - NextState = STATE_FLUSH_WRITE_BACK; - FlushWayCntEn = 1'b0; - CacheWriteLine = 1'b1; - end else if (FlushAdrFlag & FlushWayFlag) begin - NextState = STATE_READY; - CacheStall = 1'b0; - PreSelAdr = 2'b00; - FlushWayCntEn = 1'b0; - end else if(FlushWayFlag) begin - NextState = STATE_FLUSH_INCR; - FlushAdrCntEn = 1'b1; - - FlushWayCntEn = 1'b1; - end else begin - FlushWayCntEn = 1'b1; - NextState = STATE_FLUSH_CHECK; - end - end - - STATE_FLUSH_INCR: begin - CacheStall = 1'b1; - PreSelAdr = 2'b10; - SelFlush = 1'b1; - FlushWayCntRst = 1'b1; - NextState = STATE_FLUSH_CHECK; - end - - STATE_FLUSH_WRITE_BACK: begin - CacheStall = 1'b1; - PreSelAdr = 2'b10; - SelFlush = 1'b1; - if(CacheBusAck) begin - NextState = STATE_FLUSH_CLEAR_DIRTY; - end else begin - NextState = STATE_FLUSH_WRITE_BACK; - end - end - - STATE_FLUSH_CLEAR_DIRTY: begin - CacheStall = 1'b1; - ClearDirty = 1'b1; - VDWriteEnable = 1'b1; - SelFlush = 1'b1; - PreSelAdr = 2'b10; - FlushWayCntEn = 1'b0; - if(FlushAdrFlag & FlushWayFlag) begin - NextState = STATE_READY; - CacheStall = 1'b0; - PreSelAdr = 2'b00; - end else if (FlushWayFlag) begin - NextState = STATE_FLUSH_INCR; - FlushAdrCntEn = 1'b1; - - FlushWayCntEn = 1'b1; - end else begin - NextState = STATE_FLUSH_CHECK; - FlushWayCntEn = 1'b1; - end - end - - default: begin - NextState = STATE_READY; - end + STATE_READY: if(DoFlush) NextState = STATE_FLUSH; + else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; + else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY; + else if (DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY; + else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV; + else NextState = STATE_READY; + STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE; + else NextState = STATE_MISS_FETCH_WDV; + STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; + else NextState = STATE_MISS_WRITE_CACHE_LINE; + STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; + STATE_MISS_READ_WORD: if (DoWrite & ~DoAMO) NextState = STATE_MISS_WRITE_WORD; + else NextState = STATE_MISS_READ_WORD_DELAY; + STATE_MISS_READ_WORD_DELAY: if(DoAMO & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; + else if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; + else NextState = STATE_MISS_EVICT_DIRTY; + STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_CPU_BUSY_FINISH_AMO: if(CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; + else NextState = STATE_READY; + STATE_FLUSH: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; + else if (FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY; + else NextState = STATE_FLUSH_WRITE_BACK; + STATE_FLUSH_CLEAR_DIRTY: if(FlushAdrFlag & FlushWayFlag) NextState = STATE_READY; + else if (FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + default: NextState = STATE_READY; endcase end assign CacheCommitted = CurrState != STATE_READY; + assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) | + (CurrState == STATE_MISS_FETCH_WDV) | + (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_MISS_READ_WORD) | + (CurrState == STATE_MISS_EVICT_DIRTY) | + (CurrState == STATE_FLUSH) | + (CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) | + (CurrState == STATE_FLUSH_INCR) | + (CurrState == STATE_FLUSH_WRITE_BACK) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); + assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; + assign ClearValid = '0; + assign SetDirty = (CurrState == STATE_READY & DoAMO) | + (CurrState == STATE_READY & DoWrite) | + (CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) | + (CurrState == STATE_MISS_WRITE_WORD); + assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY); + assign SRAMWordWriteEnable = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) | + (CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) | + (CurrState == STATE_MISS_WRITE_WORD); + assign SRAMLineWriteEnable = (CurrState == STATE_MISS_WRITE_CACHE_LINE); + assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY); + assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) | + (CurrState == STATE_MISS_READ_WORD_DELAY) | + (CurrState == STATE_MISS_WRITE_WORD); + assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | + (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY); + assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayFlag & ~FlushAdrFlag) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag); + assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); + assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush); + assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR); + assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss)); + assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) | + (CurrState == STATE_FLUSH_CHECK & VictimDirty); + assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY; + assign save = ((CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit) & CPUBusy) | + (CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | DoRead) & CPUBusy) | + (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; + // **** can this be simplified? + assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequest) | + (CurrState == STATE_READY & DoAMOHit) | + (CurrState == STATE_READY & DoReadHit & (CPUBusy & `REPLAY)) | + (CurrState == STATE_READY & DoWriteHit) | + (CurrState == STATE_MISS_FETCH_WDV) | + (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_MISS_READ_WORD) | + (CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | (CPUBusy & `REPLAY))) | + (CurrState == STATE_MISS_WRITE_WORD) | + (CurrState == STATE_MISS_EVICT_DIRTY) | + (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | + (CurrState == STATE_CPU_BUSY_FINISH_AMO)) ? 2'b01 : + ((CurrState == STATE_FLUSH) | + (CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) | + (CurrState == STATE_FLUSH_INCR) | + (CurrState == STATE_FLUSH_WRITE_BACK) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag))) ? 2'b10 : + 2'b00; + + endmodule // cachefsm - diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index 04a53b6cb..c9bad7af9 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -39,9 +39,6 @@ module cachereplacementpolicy input logic LRUWriteEn ); - // *** Only implements 2, 4, and 8 way - // I would like parametersize this in the future. - logic [NUMWAYS-2:0] LRUEn, LRUMask; logic [$clog2(NUMWAYS)-1:0] EncVicWay; logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; @@ -52,56 +49,38 @@ module cachereplacementpolicy logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] PAdrD; logic [INDEXLEN-1:0] RAdrD; logic LRUWriteEnD; - - /* verilator lint_off BLKLOOPINIT */ - always_ff @(posedge clk) begin - if (reset) begin - RAdrD <= '0; - PAdrD <= '0; - LRUWriteEnD <= 0; - NewReplacementD <= '0; - for(int index = 0; index < NUMLINES; index++) - ReplacementBits[index] <= '0; - end else begin - RAdrD <= RAdr; - PAdrD <= PAdr; - LRUWriteEnD <= LRUWriteEn; - NewReplacementD <= NewReplacement; - if (LRUWriteEnD) begin - ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD; - end - end - end - /* verilator lint_on BLKLOOPINIT */ + initial begin + assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported"); + end + + // Pipeline Delay Registers + flopr #(INDEXLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD); + flopr #(INDEXLEN) PAdrDelayReg(clk, reset, PAdr, PAdrD); + flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD); + flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD); + + // Replacement Bits: Register file + // Needs to be resettable for simulation, but could omit reset for synthesis *** + always_ff @(posedge clk) + if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0; + else if (LRUWriteEnD) ReplacementBits[PAdrD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacementD; assign LineReplacementBits = ReplacementBits[RAdrD]; genvar index; - if(NUMWAYS == 2) begin : TwoWay - + if(NUMWAYS == 2) begin : PseudoLRU assign LRUEn[0] = 1'b0; - assign NewReplacement[0] = WayHit[1]; - assign VictimWay[1] = ~LineReplacementBits[0]; assign VictimWay[0] = LineReplacementBits[0]; - - end else if (NUMWAYS == 4) begin : FourWay - - - // VictimWay is a function only of the current value of the LRU. - // binary encoding - //assign VictimWay[0] = LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0]; - //assign VictimWay[1] = LineReplacementBits[2]; - - // 1 hot encoding - //| WayHit | LRU 2 | LRU 1 | LRU 0 | - //|--------+-------+-------+-------| - //| 0000 | - | - | - | - //| 0001 | 1 | - | 1 | - //| 0010 | 1 | - | 0 | - //| 0100 | 0 | 1 | - | - //| 1000 | 0 | 0 | - | + end else if (NUMWAYS == 4) begin : PseudoLRU + // 1 hot encoding for VictimWay; LRU = LineReplacementBits + //| LRU 2 | LRU 1 | LRU 0 | VictimWay + //+-------+-------+-------+----------- + //| 1 | - | 1 | 0001 + //| 1 | - | 0 | 0010 + //| 0 | 1 | - | 0100 + //| 0 | 0 | - | 1000 assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0]; assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0]; @@ -117,33 +96,11 @@ module cachereplacementpolicy assign LRUMask[2] = WayHit[1] | WayHit[0]; assign LRUMask[1] = WayHit[2]; assign LRUMask[0] = WayHit[0]; - -/* -----\/----- EXCLUDED -----\/----- - // selects - assign LRUEn[2] = 1'b1; - assign LRUEn[1] = WayHit[3]; - assign LRUEn[0] = WayHit[3] | WayHit[2]; - - // mask - assign LRUMask[0] = WayHit[1]; - assign LRUMask[1] = WayHit[3]; - assign LRUMask[2] = WayHit[3] | WayHit[2]; ------/\----- EXCLUDED -----/\----- */ - - for(index = 0; index < NUMWAYS-1; index++) -assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index]; - -/* -----\/----- EXCLUDED -----\/----- - assign EncVicWay[1] = LineReplacementBits[2]; - assign EncVicWay[0] = LineReplacementBits[2] ? LineReplacementBits[0] : LineReplacementBits[1]; - - onehotdecoder #(2) - waydec(.bin(EncVicWay), - .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]})); ------/\----- EXCLUDED -----/\----- */ - - end else if (NUMWAYS == 8) begin : EightWay + mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, LRUMask, LRUEn, NewReplacement); + end + /* *** 8-way not yet working - look for a general way to write this for all NUMWAYS + else if (NUMWAYS == 8) begin : PseudoLRU // selects assign LRUEn[6] = 1'b1; @@ -164,7 +121,7 @@ assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBi assign LRUMask[0] = WayHit[0]; for(index = 0; index < NUMWAYS-1; index++) -assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index]; + assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index]; assign EncVicWay[2] = LineReplacementBits[6]; assign EncVicWay[1] = LineReplacementBits[6] ? LineReplacementBits[5] : LineReplacementBits[2]; @@ -176,7 +133,7 @@ assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBi waydec(.bin(EncVicWay), .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3], VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]})); - end + end */ endmodule diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 33c2b0492..09fcbfa29 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// DCacheMem (Memory for the Data Cache) +// cacheway // // Written: ross1728@gmail.com July 07, 2021 // Implements the data, tag, valid, dirty, and replacement bits. @@ -31,117 +31,106 @@ `include "wally-config.vh" module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, - parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) - (input logic clk, - input logic reset, + parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) ( + input logic clk, + input logic reset, - input logic [$clog2(NUMLINES)-1:0] RAdr, - input logic [`PA_BITS-1:0] PAdr, - input logic WriteEnable, - input logic VDWriteEnable, - input logic [LINELEN/`XLEN-1:0] WriteWordEnable, - input logic TagWriteEnable, - input logic [LINELEN-1:0] WriteData, - input logic SetValid, - input logic ClearValid, - input logic SetDirty, - input logic ClearDirty, - input logic SelEvict, - input logic VictimWay, - input logic InvalidateAll, - input logic SelFlush, - input logic FlushWay, + input logic [$clog2(NUMLINES)-1:0] RAdr, + input logic [`PA_BITS-1:0] PAdr, + input logic SRAMWayWriteEnable, + input logic [LINELEN/`XLEN-1:0] SRAMWordEnable, + input logic TagWriteEnable, + input logic [LINELEN-1:0] WriteData, + input logic SetValid, + input logic ClearValid, + input logic SetDirty, + input logic ClearDirty, + input logic SelEvict, + input logic Victim, + input logic InvalidateAll, + input logic SelFlush, + input logic Flush, - output logic [LINELEN-1:0] ReadDataLineWayMasked, - output logic WayHit, - output logic VictimDirtyWay, - output logic [TAGLEN-1:0] VictimTagWay - ); + output logic [LINELEN-1:0] SelectedReadDataLine, + output logic WayHit, + output logic VictimDirty, + output logic [TAGLEN-1:0] VictimTag); logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] DirtyBits; - logic [LINELEN-1:0] ReadDataLineWay; + logic [LINELEN-1:0] ReadDataLine; logic [TAGLEN-1:0] ReadTag; logic Valid; logic Dirty; - logic SelectedWay; - logic [TAGLEN-1:0] VicDirtyWay; - logic [TAGLEN-1:0] FlushThisWay; + logic SelData; + logic SelTag; logic [$clog2(NUMLINES)-1:0] RAdrD; logic SetValidD, ClearValidD; logic SetDirtyD, ClearDirtyD; - logic WriteEnableD, VDWriteEnableD; - - - + logic SRAMWayWriteEnableD; + ///////////////////////////////////////////////////////////////////////////////////////////// + // Tag Array + ///////////////////////////////////////////////////////////////////////////////////////////// + + sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk), + .Adr(RAdr), .ReadData(ReadTag), + .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable)); + + // AND portion of distributed tag multiplexer + assign SelTag = SelFlush ? Flush : Victim; + assign VictimTag = SelTag ? ReadTag : '0; // AND part of AOMux + assign VictimDirty = SelTag & Dirty & Valid; + + ///////////////////////////////////////////////////////////////////////////////////////////// + // Data Array + ///////////////////////////////////////////////////////////////////////////////////////////// + + // *** Potential optimization: if byte write enables are available, could remove subwordwrites genvar words; for(words = 0; words < LINELEN/`XLEN; words++) begin: word - sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) - CacheDataMem(.clk(clk), .Addr(RAdr), - .ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ), - .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), - .WriteEnable(WriteEnable & WriteWordEnable[words])); + sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr), + .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), + .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), + .WriteEnable(SRAMWayWriteEnable & SRAMWordEnable[words])); end - sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) - CacheTagMem(.clk(clk), - .Addr(RAdr), - .ReadData(ReadTag), - .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), - .WriteEnable(TagWriteEnable)); - + // AND portion of distributed read multiplexers assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); - assign SelectedWay = SelFlush ? FlushWay : - SelEvict ? VictimWay : WayHit; - assign ReadDataLineWayMasked = SelectedWay ? ReadDataLineWay : '0; // first part of AO mux. - - assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid : - VictimWay & Dirty & Valid; - - assign VicDirtyWay = VictimWay ? ReadTag : '0; - assign FlushThisWay = FlushWay ? ReadTag : '0; - assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay; - - - always_ff @(posedge clk) begin - if (reset) - ValidBits <= {NUMLINES{1'b0}}; - else if (InvalidateAll) - ValidBits <= {NUMLINES{1'b0}}; - else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b1; - else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b0; - end - - always_ff @(posedge clk) begin - RAdrD <= RAdr; - SetValidD <= SetValid; - ClearValidD <= ClearValid; - WriteEnableD <= WriteEnable; - VDWriteEnableD <= VDWriteEnable; - end + assign SelData = SelFlush ? Flush : (SelEvict ? Victim : WayHit); + assign SelectedReadDataLine = SelData ? ReadDataLine : '0; // AND part of AO mux. + ///////////////////////////////////////////////////////////////////////////////////////////// + // Valid Bits + ///////////////////////////////////////////////////////////////////////////////////////////// + always_ff @(posedge clk) begin // Valid bit array, + if (reset | InvalidateAll) ValidBits <= #1 '0; + else if (SetValidD) ValidBits[RAdrD] <= #1 1'b1; + else if (ClearValidD) ValidBits[RAdrD] <= #1 1'b0; + end + // *** consider revisiting whether these delays are the best option? + flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); + flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, SRAMWayWriteEnable}, + {SetValidD, ClearValidD, SRAMWayWriteEnableD}); assign Valid = ValidBits[RAdrD]; + ///////////////////////////////////////////////////////////////////////////////////////////// + // Dirty Bits + ///////////////////////////////////////////////////////////////////////////////////////////// + // Dirty bits - if(DIRTY_BITS) begin:dirty + if (DIRTY_BITS) begin:dirty always_ff @(posedge clk) begin - if (reset) DirtyBits <= {NUMLINES{1'b0}}; - else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1; - else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0; - end - always_ff @(posedge clk) begin - SetDirtyD <= SetDirty; - ClearDirtyD <= ClearDirty; + if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; + else if (SetDirtyD) DirtyBits[RAdrD] <= #1 1'b1; + else if (ClearDirtyD) DirtyBits[RAdrD] <= #1 1'b0; end + flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD}); assign Dirty = DirtyBits[RAdrD]; - end else begin:dirty - assign Dirty = 1'b0; - end + end else assign Dirty = 1'b0; - -endmodule // DCacheMemWay +endmodule diff --git a/pipelined/src/cache/dcache_ptw_interaction_README.txt b/pipelined/src/cache/dcache_ptw_interaction_README.txt deleted file mode 100644 index 47e2af5d2..000000000 --- a/pipelined/src/cache/dcache_ptw_interaction_README.txt +++ /dev/null @@ -1,90 +0,0 @@ -Intractions betwen the dcache and hardware page table walker are complex. -In particular the complications arise when a fault occurs concurrently with a memory operation. - -At the begining of every memory operation there are 8 combinations of three signals; -ITBL miss, DTLB miss, and a memory operation. By looking at each combination we -can understand exactly the correct sequence of operations and if the operation -should continue. - -It is important to note ITLB misses and faults DO NOT flush a memory operation -in the memory stage. This is the core reason for the complexity. - -| Type | ITLB miss | DTLB miss | mem op | | -|-------+-----------+-----------+--------+--------------| -| 0 | 0 | 0 | 0 | | -| 1 | 0 | 0 | 1 | | -| 2 | 0 | 1 | 0 | Not possible | -| 3 | 0 | 1 | 1 | | -| 4 | 1 | 0 | 0 | | -| 5 | 1 | 0 | 1 | | -| 6 | 1 | 1 | 0 | Not possible | -| 7 | 1 | 1 | 1 | | - - -The above table classifies the operations into 8 categories. -2 of the 8 are not possible because a DTLB miss implies a memory operation. -Each (I/D)TLB miss results in either a write to the corresponding TLB or a TLB fault. -To complicate things it is possilbe to have concurrent ITLB and DTLB misses, which -both can result in either a write or a fault. The table belows shows the possible -scenarios and the sequence of operations. - - -| Type | action 1 | action 2 | action 3 | keep stall? | -|------+------------------+-----------------+-----------------+-------------| -| 1 | D$ handles memop | | | Yes | -| 3a | DTLB Write | D$ finish memop | | Yes | -| 3b | DTLB Fault | Abort memop | | No | -| 4a | ITLB write | | | No | -| 4b | ITLB Fault | | | No | -| 5a | ITLB Write | D$ finish memop | | Yes | -| 5b | ITLB Fault | D$ finish memop | | Yes | -| 7a | DTLB Write | ITLB write | D$ finish memop | Yes | -| 7b | DTLB Write | ITLB Fault | D$ finish memop | Yes | -| 7c | DTLB Fault | Abort all | | No | - -Type 1 is a memory operation which either hits in the DTLB or is a physical address. The -Dcache handles the operation. - -Type 3a is a memory operation with a DTLB miss. The Dcache enters a special set of states -designed to handle the page table walker (HTPW). Secondly the HPTW takes control over the -LSU via a set of multiplexors in the LSU Arbiter, driving the Dcache with addresses of the -page table. Interally to the HPTW an FSM checks each node of the Page Table and eventually -signals either a TLB write or a TLB Fault. In Type 3a the DTLB is written with the leaf -page table entry and returns control of the Dcache back to the IEU. Now the Dcache finishes -the memory operation using the physical address provided by the TLB. Note it is crucial -the dcache replay the memory access into the cache's SRAM memory. As the HPTW sends it -requests through the Dcache the original memory operation's SRAM lookup will be lost. - -Type 3b is similar to the 3a type in that is starts with the same conditions; however the -at the end of the page table walk a fault is detched. Rather than update the TLB the CPU -and the dcache need to be informed about the fault and abort the memory operation. Unlike -Type 3a the dcache returns directly to STATE_READY and lowers the stall. - -Type 4a is the simpliest form of TLB miss as it is an ITLB miss with no memory operation. -The Dcache switches in to the special set of page table states and the HPTW takes control -of the Dcache. Like with Type 3a the HPTW sends data request through the Dcache and eventually -reads a leaf page table entry (PTE). At this time the HPTW writes the PTE to the ITLB and -removes the stall as there is not memory operation to do. - -Type 4b is also an ITLB miss. As with 4a the Dcache switches into page table walker mode and reads -until it finds a leaf or in this case a fault. The fault is deteched and the Dcaches switches back -to normal mode. - -Type 5a is a Type 4a with a current memory operation. The Dcache first switches to walker mode. - -Other traps. -A new problem has emerged. What happens when an interrupt occurs during a page table walk? -The dcache has an output called CommittedM which tells the CPU if the memory operation is -committed into the memory system. It would be wrong to pin the interrupt to a memory operation -when it is already or partially committed to the memory system. Instead the next instruction -has to be pinned to the interrupt. The complexity occurs with the ITLB miss; types 4, 5 and 7. - -Type 4: The ITLB misses and starts using the dcache to fetch the page table. There is no memory -operation. Depending on where in the walk the operations could be aborted. If the tlb is not yet -updated then the walk could be aborted. However if the TLB is updated then the interrupt must be -delayed until the next instruction. - -What is the meaning of CommittedM? -This signal informs the CPU if a memory operation is not started or if it is between started -and done. Once a memory op is started it should not be interrupted. This is used to prevent the -CPU from generating an interrupt after the operation is partially or completely done. diff --git a/pipelined/src/cache/sram1rw.sv b/pipelined/src/cache/sram1rw.sv index 263e21e07..921c0af47 100644 --- a/pipelined/src/cache/sram1rw.sv +++ b/pipelined/src/cache/sram1rw.sv @@ -34,25 +34,22 @@ // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words module sram1rw #(parameter DEPTH=128, WIDTH=256) ( - input logic clk, - // port 1 is read only - input logic [$clog2(DEPTH)-1:0] Addr, - output logic [WIDTH-1:0] ReadData, - - // port 2 is write only - input logic [WIDTH-1:0] WriteData, - input logic WriteEnable -); + input logic clk, + input logic [$clog2(DEPTH)-1:0] Adr, + input logic [WIDTH-1:0] WriteData, + input logic WriteEnable, + output logic [WIDTH-1:0] ReadData); - logic [DEPTH-1:0][WIDTH-1:0] StoredData; // *** inconsistency in packed vs. unpacked - logic [$clog2(DEPTH)-1:0] AddrD; - logic [WIDTH-1:0] WriteDataD; - logic WriteEnableD; - + logic [WIDTH-1:0] StoredData[DEPTH-1:0]; + logic [$clog2(DEPTH)-1:0] AddrD; + logic [WIDTH-1:0] WriteDataD; + logic WriteEnableD; + //*** model as single port + // *** merge with simpleram always_ff @(posedge clk) begin - AddrD <= Addr; - WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. + AddrD <= Adr; + WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay. Implement alternative cache stall to avoid this. Eliminates a bunch of delay flops elsewhere WriteEnableD <= WriteEnable; if (WriteEnableD) begin StoredData[AddrD] <= #1 WriteDataD; @@ -60,7 +57,12 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) ( end assign ReadData = StoredData[AddrD]; - +/* + always_ff @(posedge clk) begin + ReadData <= RAM[Adr]; + if (WriteEnable) RAM[Adr] <= WriteData; + end + */ endmodule diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv new file mode 100644 index 000000000..111ec506f --- /dev/null +++ b/pipelined/src/cache/subcachelineread.sv @@ -0,0 +1,69 @@ +/////////////////////////////////////////// +// subcachelineread +// +// Written: Ross Thompson ross1728@gmail.com February 04, 2022 +// Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes. +// +// Purpose: Controller for the dcache fsm +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( + input logic clk, + input logic reset, + input logic [`PA_BITS-1:0] PAdr, + input logic save, restore, + input logic [LINELEN-1:0] ReadDataLine, + output logic [WORDLEN-1:0] ReadDataWord); + + localparam WORDSPERLINE = LINELEN/MUXINTERVAL; + localparam PADLEN = WORDLEN-MUXINTERVAL; + // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can + // easily build a variable input mux. + // *** move this to LSU and IFU, also remove mux from busdp into LSU. + // *** give this a module name to match block diagram + logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad; + logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0]; + logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved; + + if (PADLEN > 0) begin + logic [PADLEN-1:0] Pad; + assign Pad = '0; + assign ReadDataLinePad = {Pad, ReadDataLine}; + end else assign ReadDataLinePad = ReadDataLine; + + + genvar index; + for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux + assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)]; + end + // variable input mux + assign ReadDataWordRaw = ReadDataLineSets[PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]]; + if(!`REPLAY) begin + flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved); + mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved, + restore, ReadDataWord); + end else assign ReadDataWord = ReadDataWordRaw; +endmodule diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv index 43b873567..3ad367bd5 100644 --- a/pipelined/src/generic/flop/simpleram.sv +++ b/pipelined/src/generic/flop/simpleram.sv @@ -40,18 +40,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) ( logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)]; - /* verilator lint_off WIDTH */ - if (`XLEN == 64) begin:ramrw - always_ff @(posedge clk) begin - rd <= RAM[a[31:3]]; - if (we) RAM[a[31:3]] <= #1 wd; - end - end else begin - always_ff @(posedge clk) begin:ramrw - rd <= RAM[a[31:2]]; - if (we) RAM[a[31:2]] <= #1 wd; - end + // discard bottom 2 or 3 bits of address offset within word or doubleword + localparam adrlsb = (`XLEN==64) ? 3 : 2; + logic [31:adrlsb] adrmsbs; + assign adrmsbs = a[31:adrlsb]; + + always_ff @(posedge clk) begin + rd <= RAM[adrmsbs]; + if (we) RAM[adrmsbs] <= #1 wd; end - /* verilator lint_on WIDTH */ endmodule diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index 99bf3a64a..bde552ab5 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -166,7 +166,7 @@ module controller( // unswizzle control bits // squash control signals if coming from an illegal compressed instruction // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. - assign IllegalERegAdrD = `E_SUPPORTED & RegWriteD & InstrD[11]; + assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; assign IllegalBaseInstrFaultD = ControlsD[0] | IllegalERegAdrD; assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, @@ -187,7 +187,7 @@ module controller( // Fences // Ordinary fence is presently a nop // FENCE.I flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented - if (`ZIFENCEI_SUPPORTED & `MEM_ICACHE) begin:fencei + if (`ZIFENCEI_SUPPORTED & (`IMEM == `MEM_CACHE)) begin:fencei logic FenceID; assign FenceID = FenceD & (Funct3D == 3'b001); // is it a FENCE.I instruction? assign InvalidateICacheD = FenceID; diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 0c1ff3e32..aa43a5b19 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -125,7 +125,7 @@ module datapath ( // Writeback stage pipeline register and logic flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW); flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW); - flopen #(`XLEN) ReadDataWReg(.clk, .en(~StallW), .d(ReadDataM), .q(ReadDataW)); + flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW); mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW); // floating point interactions: fcvt, fp stores @@ -133,8 +133,7 @@ module datapath ( mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); end else begin:fpmux - assign ResultM = IEUResultM; - assign WriteDataE = ForwardedSrcBE; + assign ResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE; end // handle Store Conditional result if atomic extension supported diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index e6407a894..2dfb0626d 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -50,7 +50,7 @@ module regfile ( // reset is intended for simulation only, not synthesis - always_ff @(negedge clk) // or posedge reset) + always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset if (reset) for(i=1; i= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS) else $error("DCACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS) else $error("ICACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (`ICACHE_NUMWAYS == 1 | `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented"); + assert (`ICACHE_NUMWAYS == 1 | (`IMEM != `MEM_CACHE)) else $warning("Multiple Instruction Cache ways not yet implemented"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2"); assert (`RAM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); @@ -836,10 +836,10 @@ module DCacheFlushFSM copyShadow #(.tagstart(tagstart), .loglinebytelen(loglinebytelen)) copyShadow(.clk, .start, - .tag(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].CacheTagMem.StoredData[index]), - .valid(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].ValidBits[index]), - .dirty(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].DirtyBits[index]), - .data(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]), + .tag(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].CacheTagMem.StoredData[index]), + .valid(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].ValidBits[index]), + .dirty(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].DirtyBits[index]), + .data(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), .index(index), .cacheWord(cacheWord), .CacheData(CacheData[way][index][cacheWord]), diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 06f2cf2e9..0a6fca7f4 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -4,7 +4,7 @@ // Written: nboorstin@g.hmc.edu 2021 // Modified: // -// Purpose: Testbench for buildroot or busybear linux +// Purpose: Testbench for Buildroot Linux // // A component of the Wally configurable RISC-V project. // @@ -186,8 +186,8 @@ module testbench; `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q `define MEPC `CSR_BASE.csrm.MEPCreg.q `define SEPC `CSR_BASE.csrs.csrs.SEPCreg.q - `define MCOUNTEREN `CSR_BASE.csrm.counters.MCOUNTERENreg.q - `define SCOUNTEREN `CSR_BASE.csrs.csrs.scounteren.SCOUNTERENreg.q + `define MCOUNTEREN `CSR_BASE.csrm.MCOUNTERENreg.q + `define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q `define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q `define MTVEC `CSR_BASE.csrm.MTVECreg.q diff --git a/pipelined/testbench/testbench-tim.sv b/pipelined/testbench/testbench-tim.sv deleted file mode 100644 index 64d989292..000000000 --- a/pipelined/testbench/testbench-tim.sv +++ /dev/null @@ -1,476 +0,0 @@ -/////////////////////////////////////////// -// testbench.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: Wally Testbench and helper modules -// Applies test programs from the riscv-arch-test and Imperas suites -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" -`include "tests.vh" - -module testbench; - parameter TESTSPERIPH = 0; // set to 0 for regression - parameter TESTSPRIV = 0; // set to 0 for regression - parameter DEBUG=0; - parameter TEST="none"; - - logic clk; - logic reset_ext, reset; - - parameter SIGNATURESIZE = 5000000; - - int test, i, errors, totalerrors; - logic [31:0] sig32[0:SIGNATURESIZE]; - logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; - logic [`XLEN-1:0] testadr; - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - logic [31:0] InstrW; - logic [`XLEN-1:0] meminit; - - -string tests[]; -logic [3:0] dummy; - - string ProgramAddrMapFile, ProgramLabelMapFile; - logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic [31:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - logic [`XLEN-1:0] PCW; - - logic DCacheFlushDone, DCacheFlushStart; - - flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); - - // check assertions for a legal configuration - riscvassertions riscvassertions(); - - // pick tests based on modes supported - initial begin - $display("TEST is %s", TEST); - //tests = '{}; - if (`XLEN == 64) begin // RV64 - case (TEST) - "arch64i": tests = arch64i; - "arch64priv": tests = arch64priv; - "arch64c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; - else tests = {arch64c}; - "arch64m": if (`M_SUPPORTED) tests = arch64m; - "arch64d": if (`D_SUPPORTED) tests = arch64d; - "imperas64i": tests = imperas64i; - "imperas64p": tests = imperas64p; -// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu; - "imperas64f": if (`F_SUPPORTED) tests = imperas64f; - "imperas64d": if (`D_SUPPORTED) tests = imperas64d; - "imperas64m": if (`M_SUPPORTED) tests = imperas64m; - "imperas64a": if (`A_SUPPORTED) tests = imperas64a; - "imperas64c": if (`C_SUPPORTED) tests = imperas64c; - else tests = imperas64iNOc; - "testsBP64": tests = testsBP64; - "wally64i": tests = wally64i; // *** redo - "wally64priv": tests = wally64priv;// *** redo - "imperas64periph": tests = imperas64periph; - endcase - end else begin // RV32 - case (TEST) - "arch32i": tests = arch32i; - "arch32priv": tests = arch32priv; - "arch32c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; - else tests = {arch32c}; - "arch32m": if (`M_SUPPORTED) tests = arch32m; - "arch32f": if (`F_SUPPORTED) tests = arch32f; - "imperas32i": tests = imperas32i; - "imperas32p": tests = imperas32p; -// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu; - "imperas32f": if (`F_SUPPORTED) tests = imperas32f; - "imperas32m": if (`M_SUPPORTED) tests = imperas32m; - "imperas32a": if (`A_SUPPORTED) tests = imperas32a; - "imperas32c": if (`C_SUPPORTED) tests = imperas32c; - else tests = imperas32iNOc; - "wally32i": tests = wally32i; // *** redo - "wally32priv": tests = wally32priv; // *** redo - "imperas32periph": tests = imperas32periph; - endcase - end - if (tests.size() == 0) begin - $display("TEST %s not supported in this configuration", TEST); - $stop; - end - end - - string signame, memfilename, pathname; - - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; - logic UARTSin, UARTSout; - - logic SDCCLK; - logic SDCCmdIn; - logic SDCCmdOut; - logic SDCCmdOE; - logic [3:0] SDCDatIn; - - logic HREADY; - logic HSELEXT; - - - // instantiate device to be tested - assign GPIOPinsIn = 0; - assign UARTSin = 1; - assign HREADYEXT = 1; - assign HRESPEXT = 0; - assign HRDATAEXT = 0; - - wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, - .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); - - // Track names of instructions - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.FinalInstrRawF, - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - dut.core.ifu.InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - - // initialize tests - localparam integer MemStartAddr = `RAM_BASE>>(1+`XLEN/32); - localparam integer MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32); - - initial - begin - test = 1; - totalerrors = 0; - testadr = 0; - // fill memory with defined values to reduce Xs in simulation - // Quick note the memory will need to be initialized. The C library does not - // guarantee the initialized reads. For example a strcmp can read 6 byte - // strings, but uses a load double to read them in. If the last 2 bytes are - // not initialized the compare results in an 'x' which propagates through - // the design. - if (`XLEN == 32) meminit = 32'hFEDC0123; - else meminit = 64'hFEDCBA9876543210; - // *** broken because DTIM also drives RAM - if (`TESTSBP) begin - for (i=MemStartAddr; i= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); - assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - end -endmodule - - -/* verilator lint_on STMTDLY */ -/* verilator lint_on WIDTH */ - -module DCacheFlushFSM - (input logic clk, - input logic reset, - input logic start, - output logic done); - - genvar adr; - - logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; - - if(`MEM_DCACHE) begin - localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN; - localparam integer lognumlines = $clog2(numlines); - localparam integer loglinebytelen = $clog2(linebytelen); - localparam integer lognumways = $clog2(numways); - localparam integer tagstart = lognumlines + loglinebytelen; - - - - genvar index, way, cacheWord; - logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0]; - for(index = 0; index < numlines; index++) begin - for(way = 0; way < numways; way++) begin - for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin - copyShadow #(.tagstart(tagstart), - .loglinebytelen(loglinebytelen)) - copyShadow(.clk, - .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]), - .valid(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]), - .dirty(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]), - .index(index), - .cacheWord(cacheWord), - .CacheData(CacheData[way][index][cacheWord]), - .CacheAdr(CacheAdr[way][index][cacheWord]), - .CacheTag(CacheTag[way][index][cacheWord]), - .CacheValid(CacheValid[way][index][cacheWord]), - .CacheDirty(CacheDirty[way][index][cacheWord])); - end - end - end - - integer i, j, k; - - always @(posedge clk) begin - if (start) begin #1 - #1 - for(i = 0; i < numlines; i++) begin - for(j = 0; j < numways; j++) begin - for(k = 0; k < numwords; k++) begin - if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin - ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; - end - end - end - end - end - end - - - end - flop #(1) doneReg(.clk, .d(start), .q(done)); -endmodule - -module copyShadow - #(parameter tagstart, loglinebytelen) - (input logic clk, - input logic start, - input logic [`PA_BITS-1:tagstart] tag, - input logic valid, dirty, - input logic [`XLEN-1:0] data, - input logic [32-1:0] index, - input logic [32-1:0] cacheWord, - output logic [`XLEN-1:0] CacheData, - output logic [`PA_BITS-1:0] CacheAdr, - output logic [`XLEN-1:0] CacheTag, - output logic CacheValid, - output logic CacheDirty); - - - always_ff @(posedge clk) begin - if(start) begin - CacheTag = tag; - CacheValid = valid; - CacheDirty = dirty; - CacheData = data; - CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8)); - end - end - -endmodule - diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index cd9a22880..3117c1112 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -49,8 +49,6 @@ module testbench; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; - logic [`XLEN-1:0] meminit; - string tests[]; logic [3:0] dummy; @@ -92,7 +90,7 @@ logic [3:0] dummy; "arch64d": if (`D_SUPPORTED) tests = arch64d; "imperas64i": tests = imperas64i; "imperas64p": tests = imperas64p; -// "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu; +// "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64m": if (`M_SUPPORTED) tests = imperas64m; @@ -102,7 +100,8 @@ logic [3:0] dummy; "testsBP64": tests = testsBP64; "wally64i": tests = wally64i; // *** redo "wally64priv": tests = wally64priv;// *** redo - "imperas64periph": tests = imperas64periph; + "imperas64periph": tests = imperas64periph; + "coremark": tests = coremark; endcase end else begin // RV32 case (TEST) @@ -115,13 +114,14 @@ logic [3:0] dummy; "arch32f": if (`F_SUPPORTED) tests = arch32f; "imperas32i": tests = imperas32i; "imperas32p": tests = imperas32p; -// "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu; +// "imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu; "imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32m": if (`M_SUPPORTED) tests = imperas32m; "imperas32a": if (`A_SUPPORTED) tests = imperas32a; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; "wally32i": tests = wally32i; // *** redo + "wally32e": tests = wally32e; "wally32priv": tests = wally32priv; // *** redo "imperas32periph": tests = imperas32periph; endcase @@ -161,7 +161,7 @@ logic [3:0] dummy; // Track names of instructions instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.FinalInstrRawF, + dut.core.ifu.FinalInstrRawF[31:0], dut.core.ifu.InstrD, dut.core.ifu.InstrE, dut.core.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); @@ -181,22 +181,20 @@ logic [3:0] dummy; // strings, but uses a load double to read them in. If the last 2 bytes are // not initialized the compare results in an 'x' which propagates through // the design. - if (`XLEN == 32) meminit = 32'hFEDC0123; - else meminit = 64'hFEDCBA9876543210; - // *** broken because DTIM also drives RAM - if (`TESTSBP) begin - for (i=MemStartAddr; i= 4 & sig32[i-4] === 'bx) begin + if (i == 4) begin i = SIGNATURESIZE+1; // flag empty file $display(" Error: empty test file"); end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency @@ -247,17 +250,21 @@ logic [3:0] dummy; testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8); /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin - //$display("signature[%h] = %h", i, signature[i]); - // *** have to figure out how to exclude shadowram when not using a dcache. - if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] & + logic [`XLEN-1:0] sig; + if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadr+i]; + else sig = dut.uncore.ram.ram.RAM[testadr+i]; +// $display("signature[%h] = %h sig = %h", i, signature[i], sig); + if (signature[i] !== sig & //if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] & - (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin - if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin + (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1? + if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin +// if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin // report errors unless they are garbage at the end of the sim // kind of hacky test for garbage right now + $display("sig4 = %h ne %b", signature[i+4], signature[i+4] !== 'bx); errors = errors+1; - $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", - tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]); + $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DMEM) = %h, signature = %h", + tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); // tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.RAM[testadr+i], signature[i]); $stop;//***debug end @@ -281,8 +288,11 @@ logic [3:0] dummy; else begin //pathname = tvpaths[tests[0]]; memfilename = {pathname, tests[test], ".elf.memfile"}; - $readmemh(memfilename, dut.uncore.ram.ram.RAM); - //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM); + //$readmemh(memfilename, dut.uncore.ram.ram.RAM); + if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM); + else $readmemh(memfilename, dut.uncore.ram.ram.RAM); + if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; $display("Read memfile %s", memfilename); @@ -330,30 +340,30 @@ endmodule module riscvassertions; initial begin assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); - assert (`S_SUPPORTED | `MEM_VIRTMEM == 0) else $error("Virtual memory requires S mode support"); + assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (`DMEM != `MEM_CACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (`IMEM != `MEM_CACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `MEM_VIRTMEM == 0)) else $error("PMP_ENTRIES and MEM_VIRTMEM must be zero if ZICSR not supported."); + assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); - assert (`MEM_DTIM == 0 | `MEM_VIRTMEM ==0) else $error("DTIM doesn't play nicely with virtual memory"); - assert (`MEM_IROM == 0 | `MEM_VIRTMEM ==0) else $error("IROM doesn't play nicely with virtual memory"); +// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); + assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); end endmodule @@ -371,7 +381,7 @@ module DCacheFlushFSM logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; - if(`MEM_DCACHE) begin + if(`DMEM == `MEM_CACHE) begin localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; @@ -396,10 +406,10 @@ module DCacheFlushFSM .loglinebytelen(loglinebytelen)) copyShadow(.clk, .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]), - .valid(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].ValidBits[index]), - .dirty(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].DirtyBits[index]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]), + .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), + .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), + .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), + .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), .index(index), .cacheWord(cacheWord), .CacheData(CacheData[way][index][cacheWord]), diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 424f2282b..9cce5847f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -26,17 +26,24 @@ `define IMPERASTEST "0" `define RISCVARCHTEST "1" `define WALLYTEST "2" -`define MYIMPERASTEST "3" +`define MYIMPERASTEST "3" +`define COREMARK "4" // *** remove MYIMPERASTEST cases when ported string tvpaths[] = '{ "../../addins/imperas-riscv-tests/work/", "../../addins/riscv-arch-test/work/", "../../tests/wally-riscv-arch-test/work/", - "../../tests/imperas-riscv-tests/work/" + "../../tests/imperas-riscv-tests/work/", + "../../benchmarks/riscv-coremark/work/" }; // *** make sure these are somewhere + string coremark[] = '{ + `COREMARK, + "coremark.bare.riscv", "100000" + }; + string imperas64a[] = '{ `MYIMPERASTEST, "rv64a/WALLY-AMO", "2110", @@ -94,739 +101,739 @@ string tvpaths[] = '{ string imperas32f[] = '{ `IMPERASTEST, "rv32i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FADD-S-RDN-01", "002010", - "rv32i_m/F/FADD-S-RMM-01", "002010", - "rv32i_m/F/FADD-S-RNE-01", "002010", - "rv32i_m/F/FADD-S-RTZ-01", "002010", - "rv32i_m/F/FADD-S-RUP-01", "002010", - "rv32i_m/F/FCLASS-S-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-W-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-RUP-01", "002010", - "rv32i_m/F/FEQ-S-01", "002010", - "rv32i_m/F/FLE-S-01", "002010", - "rv32i_m/F/FLT-S-01", "002010", - "rv32i_m/F/FLW-01", "002120", - "rv32i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMADD-S-RDN-01", "002010", - "rv32i_m/F/FMADD-S-RMM-01", "002010", - "rv32i_m/F/FMADD-S-RNE-01", "002010", - "rv32i_m/F/FMADD-S-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-RUP-01", "002010", - "rv32i_m/F/FMAX-S-01", "002010", - "rv32i_m/F/FMIN-S-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMSUB-S-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-RUP-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMUL-S-RDN-01", "002010", - "rv32i_m/F/FMUL-S-RMM-01", "002010", - "rv32i_m/F/FMUL-S-RNE-01", "002010", - "rv32i_m/F/FMUL-S-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-RUP-01", "002010", - "rv32i_m/F/FMV-W-X-01", "002010", - "rv32i_m/F/FMV-X-W-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMADD-S-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-RUP-01", "002010", - "rv32i_m/F/FSGNJN-S-01", "002010", - "rv32i_m/F/FSGNJ-S-01", "002010", - "rv32i_m/F/FSGNJX-S-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FSQRT-S-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-RUP-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FSUB-S-RDN-01", "002010", - "rv32i_m/F/FSUB-S-RMM-01", "002010", - "rv32i_m/F/FSUB-S-RNE-01", "002010", - "rv32i_m/F/FSUB-S-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-RUP-01", "002010", - "rv32i_m/F/FSW-01", "002010" + "rv32i_m/F/FADD-S-DYN-RMM-01", "002010", + "rv32i_m/F/FADD-S-DYN-RNE-01", "002010", + "rv32i_m/F/FADD-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FADD-S-DYN-RUP-01", "002010", + "rv32i_m/F/FADD-S-RDN-01", "002010", + "rv32i_m/F/FADD-S-RMM-01", "002010", + "rv32i_m/F/FADD-S-RNE-01", "002010", + "rv32i_m/F/FADD-S-RTZ-01", "002010", + "rv32i_m/F/FADD-S-RUP-01", "002010", + "rv32i_m/F/FCLASS-S-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-S-W-RDN-01", "002010", + "rv32i_m/F/FCVT-S-W-RMM-01", "002010", + "rv32i_m/F/FCVT-S-W-RNE-01", "002010", + "rv32i_m/F/FCVT-S-W-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-W-RUP-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-S-WU-RDN-01", "002010", + "rv32i_m/F/FCVT-S-WU-RMM-01", "002010", + "rv32i_m/F/FCVT-S-WU-RNE-01", "002010", + "rv32i_m/F/FCVT-S-WU-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-WU-RUP-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-W-S-RDN-01", "002010", + "rv32i_m/F/FCVT-W-S-RMM-01", "002010", + "rv32i_m/F/FCVT-W-S-RNE-01", "002010", + "rv32i_m/F/FCVT-W-S-RTZ-01", "002010", + "rv32i_m/F/FCVT-W-S-RUP-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-WU-S-RDN-01", "002010", + "rv32i_m/F/FCVT-WU-S-RMM-01", "002010", + "rv32i_m/F/FCVT-WU-S-RNE-01", "002010", + "rv32i_m/F/FCVT-WU-S-RTZ-01", "002010", + "rv32i_m/F/FCVT-WU-S-RUP-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", + // "rv32i_m/F/FDIV-S-RDN-01", "002010", + // "rv32i_m/F/FDIV-S-RMM-01", "002010", + // "rv32i_m/F/FDIV-S-RNE-01", "002010", + // "rv32i_m/F/FDIV-S-RTZ-01", "002010", + // "rv32i_m/F/FDIV-S-RUP-01", "002010", + "rv32i_m/F/FEQ-S-01", "002010", + "rv32i_m/F/FLE-S-01", "002010", + "rv32i_m/F/FLT-S-01", "002010", + "rv32i_m/F/FLW-01", "002120", + "rv32i_m/F/FMADD-S-DYN-RDN-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RMM-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RNE-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RUP-01", "002010", + "rv32i_m/F/FMADD-S-RDN-01", "002010", + "rv32i_m/F/FMADD-S-RMM-01", "002010", + "rv32i_m/F/FMADD-S-RNE-01", "002010", + "rv32i_m/F/FMADD-S-RTZ-01", "002010", + "rv32i_m/F/FMADD-S-RUP-01", "002010", + "rv32i_m/F/FMAX-S-01", "002010", + "rv32i_m/F/FMIN-S-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RDN-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RMM-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RNE-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RUP-01", "002010", + "rv32i_m/F/FMSUB-S-RDN-01", "002010", + "rv32i_m/F/FMSUB-S-RMM-01", "002010", + "rv32i_m/F/FMSUB-S-RNE-01", "002010", + "rv32i_m/F/FMSUB-S-RTZ-01", "002010", + "rv32i_m/F/FMSUB-S-RUP-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RDN-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RMM-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RNE-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RUP-01", "002010", + "rv32i_m/F/FMUL-S-RDN-01", "002010", + "rv32i_m/F/FMUL-S-RMM-01", "002010", + "rv32i_m/F/FMUL-S-RNE-01", "002010", + "rv32i_m/F/FMUL-S-RTZ-01", "002010", + "rv32i_m/F/FMUL-S-RUP-01", "002010", + "rv32i_m/F/FMV-W-X-01", "002010", + "rv32i_m/F/FMV-X-W-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RDN-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RMM-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RNE-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RUP-01", "002010", + "rv32i_m/F/FNMADD-S-RDN-01", "002010", + "rv32i_m/F/FNMADD-S-RMM-01", "002010", + "rv32i_m/F/FNMADD-S-RNE-01", "002010", + "rv32i_m/F/FNMADD-S-RTZ-01", "002010", + "rv32i_m/F/FNMADD-S-RUP-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01", "002010", + "rv32i_m/F/FNMSUB-S-RDN-01", "002010", + "rv32i_m/F/FNMSUB-S-RMM-01", "002010", + "rv32i_m/F/FNMSUB-S-RNE-01", "002010", + "rv32i_m/F/FNMSUB-S-RTZ-01", "002010", + "rv32i_m/F/FNMSUB-S-RUP-01", "002010", + "rv32i_m/F/FSGNJN-S-01", "002010", + "rv32i_m/F/FSGNJ-S-01", "002010", + "rv32i_m/F/FSGNJX-S-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", + // "rv32i_m/F/FSQRT-S-RDN-01", "002010", + // "rv32i_m/F/FSQRT-S-RMM-01", "002010", + // "rv32i_m/F/FSQRT-S-RNE-01", "002010", + // "rv32i_m/F/FSQRT-S-RTZ-01", "002010", + // "rv32i_m/F/FSQRT-S-RUP-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RDN-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RMM-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RNE-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RUP-01", "002010", + "rv32i_m/F/FSUB-S-RDN-01", "002010", + "rv32i_m/F/FSUB-S-RMM-01", "002010", + "rv32i_m/F/FSUB-S-RNE-01", "002010", + "rv32i_m/F/FSUB-S-RTZ-01", "002010", + "rv32i_m/F/FSUB-S-RUP-01", "002010", + "rv32i_m/F/FSW-01", "002010" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FADD-S-RDN-01", "002010", - "rv64i_m/F/FADD-S-RMM-01", "002010", - "rv64i_m/F/FADD-S-RNE-01", "002010", - "rv64i_m/F/FADD-S-RTZ-01", "002010", - "rv64i_m/F/FADD-S-RUP-01", "002010", - "rv64i_m/F/FCLASS-S-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-L-S-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-RUP-01", "002010", - "rv64i_m/F/FEQ-S-01", "002010", - "rv64i_m/F/FLE-S-01", "002010", - "rv64i_m/F/FLT-S-01", "002010", - "rv64i_m/F/FLW-01", "002210", - "rv64i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMADD-S-RDN-01", "002010", - "rv64i_m/F/FMADD-S-RMM-01", "002010", - "rv64i_m/F/FMADD-S-RNE-01", "002010", - "rv64i_m/F/FMADD-S-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-RUP-01", "002010", - "rv64i_m/F/FMAX-S-01", "002010", - "rv64i_m/F/FMIN-S-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMSUB-S-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-RUP-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMUL-S-RDN-01", "002010", - "rv64i_m/F/FMUL-S-RMM-01", "002010", - "rv64i_m/F/FMUL-S-RNE-01", "002010", - "rv64i_m/F/FMUL-S-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-RUP-01", "002010", - "rv64i_m/F/FMV-W-X-01", "002010", - "rv64i_m/F/FMV-X-W-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMADD-S-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-RUP-01", "002010", - "rv64i_m/F/FSGNJN-S-01", "002010", - "rv64i_m/F/FSGNJ-S-01", "002010", - "rv64i_m/F/FSGNJX-S-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FSQRT-S-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-RUP-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FSUB-S-RDN-01", "002010", - "rv64i_m/F/FSUB-S-RMM-01", "002010", - "rv64i_m/F/FSUB-S-RNE-01", "002010", - "rv64i_m/F/FSUB-S-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-RUP-01", "002010", - "rv64i_m/F/FSW-01", "002010" + "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", + "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", + "rv64i_m/F/FADD-S-DYN-RNE-01", "002010", + "rv64i_m/F/FADD-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FADD-S-DYN-RUP-01", "002010", + "rv64i_m/F/FADD-S-RDN-01", "002010", + "rv64i_m/F/FADD-S-RMM-01", "002010", + "rv64i_m/F/FADD-S-RNE-01", "002010", + "rv64i_m/F/FADD-S-RTZ-01", "002010", + "rv64i_m/F/FADD-S-RUP-01", "002010", + "rv64i_m/F/FCLASS-S-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-L-S-RDN-01", "002010", + "rv64i_m/F/FCVT-L-S-RMM-01", "002010", + "rv64i_m/F/FCVT-L-S-RNE-01", "002010", + "rv64i_m/F/FCVT-L-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-L-S-RUP-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-LU-S-RDN-01", "002010", + "rv64i_m/F/FCVT-LU-S-RMM-01", "002010", + "rv64i_m/F/FCVT-LU-S-RNE-01", "002010", + "rv64i_m/F/FCVT-LU-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-LU-S-RUP-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-L-RDN-01", "002010", + "rv64i_m/F/FCVT-S-L-RMM-01", "002010", + "rv64i_m/F/FCVT-S-L-RNE-01", "002010", + "rv64i_m/F/FCVT-S-L-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-L-RUP-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-LU-RDN-01", "002010", + "rv64i_m/F/FCVT-S-LU-RMM-01", "002010", + "rv64i_m/F/FCVT-S-LU-RNE-01", "002010", + "rv64i_m/F/FCVT-S-LU-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-LU-RUP-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-W-RDN-01", "002010", + "rv64i_m/F/FCVT-S-W-RMM-01", "002010", + "rv64i_m/F/FCVT-S-W-RNE-01", "002010", + "rv64i_m/F/FCVT-S-W-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-W-RUP-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-WU-RDN-01", "002010", + "rv64i_m/F/FCVT-S-WU-RMM-01", "002010", + "rv64i_m/F/FCVT-S-WU-RNE-01", "002010", + "rv64i_m/F/FCVT-S-WU-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-WU-RUP-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-W-S-RDN-01", "002010", + "rv64i_m/F/FCVT-W-S-RMM-01", "002010", + "rv64i_m/F/FCVT-W-S-RNE-01", "002010", + "rv64i_m/F/FCVT-W-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-W-S-RUP-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-WU-S-RDN-01", "002010", + "rv64i_m/F/FCVT-WU-S-RMM-01", "002010", + "rv64i_m/F/FCVT-WU-S-RNE-01", "002010", + "rv64i_m/F/FCVT-WU-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-WU-S-RUP-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", + // "rv64i_m/F/FDIV-S-RDN-01", "002010", + // "rv64i_m/F/FDIV-S-RMM-01", "002010", + // "rv64i_m/F/FDIV-S-RNE-01", "002010", + // "rv64i_m/F/FDIV-S-RTZ-01", "002010", + // "rv64i_m/F/FDIV-S-RUP-01", "002010", + "rv64i_m/F/FEQ-S-01", "002010", + "rv64i_m/F/FLE-S-01", "002010", + "rv64i_m/F/FLT-S-01", "002010", + "rv64i_m/F/FLW-01", "002210", + "rv64i_m/F/FMADD-S-DYN-RDN-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RMM-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RNE-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RUP-01", "002010", + "rv64i_m/F/FMADD-S-RDN-01", "002010", + "rv64i_m/F/FMADD-S-RMM-01", "002010", + "rv64i_m/F/FMADD-S-RNE-01", "002010", + "rv64i_m/F/FMADD-S-RTZ-01", "002010", + "rv64i_m/F/FMADD-S-RUP-01", "002010", + "rv64i_m/F/FMAX-S-01", "002010", + "rv64i_m/F/FMIN-S-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RDN-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RMM-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RNE-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RUP-01", "002010", + "rv64i_m/F/FMSUB-S-RDN-01", "002010", + "rv64i_m/F/FMSUB-S-RMM-01", "002010", + "rv64i_m/F/FMSUB-S-RNE-01", "002010", + "rv64i_m/F/FMSUB-S-RTZ-01", "002010", + "rv64i_m/F/FMSUB-S-RUP-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RMM-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RNE-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RUP-01", "002010", + "rv64i_m/F/FMUL-S-RDN-01", "002010", + "rv64i_m/F/FMUL-S-RMM-01", "002010", + "rv64i_m/F/FMUL-S-RNE-01", "002010", + "rv64i_m/F/FMUL-S-RTZ-01", "002010", + "rv64i_m/F/FMUL-S-RUP-01", "002010", + "rv64i_m/F/FMV-W-X-01", "002010", + "rv64i_m/F/FMV-X-W-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RDN-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RMM-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RNE-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RUP-01", "002010", + "rv64i_m/F/FNMADD-S-RDN-01", "002010", + "rv64i_m/F/FNMADD-S-RMM-01", "002010", + "rv64i_m/F/FNMADD-S-RNE-01", "002010", + "rv64i_m/F/FNMADD-S-RTZ-01", "002010", + "rv64i_m/F/FNMADD-S-RUP-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01", "002010", + "rv64i_m/F/FNMSUB-S-RDN-01", "002010", + "rv64i_m/F/FNMSUB-S-RMM-01", "002010", + "rv64i_m/F/FNMSUB-S-RNE-01", "002010", + "rv64i_m/F/FNMSUB-S-RTZ-01", "002010", + "rv64i_m/F/FNMSUB-S-RUP-01", "002010", + "rv64i_m/F/FSGNJN-S-01", "002010", + "rv64i_m/F/FSGNJ-S-01", "002010", + "rv64i_m/F/FSGNJX-S-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", + // "rv64i_m/F/FSQRT-S-RDN-01", "002010", + // "rv64i_m/F/FSQRT-S-RMM-01", "002010", + // "rv64i_m/F/FSQRT-S-RNE-01", "002010", + // "rv64i_m/F/FSQRT-S-RTZ-01", "002010", + // "rv64i_m/F/FSQRT-S-RUP-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RDN-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RMM-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RNE-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RUP-01", "002010", + "rv64i_m/F/FSUB-S-RDN-01", "002010", + "rv64i_m/F/FSUB-S-RMM-01", "002010", + "rv64i_m/F/FSUB-S-RNE-01", "002010", + "rv64i_m/F/FSUB-S-RTZ-01", "002010", + "rv64i_m/F/FSUB-S-RUP-01", "002010", + "rv64i_m/F/FSW-01", "002010" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01", "002010", - "rv64i_m/D/FADD-D-DYN-RMM-01", "002010", - "rv64i_m/D/FADD-D-DYN-RNE-01", "002010", - "rv64i_m/D/FADD-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FADD-D-DYN-RUP-01", "002010", - "rv64i_m/D/FADD-D-RDN-01", "002010", - "rv64i_m/D/FADD-D-RMM-01", "002010", - "rv64i_m/D/FADD-D-RNE-01", "002010", - "rv64i_m/D/FADD-D-RTZ-01", "002010", - "rv64i_m/D/FADD-D-RUP-01", "002010", - "rv64i_m/D/FCLASS-D-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-L-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-RUP-01", "002010", - "rv64i_m/D/FCVT-D-S-01", "002010", - "rv64i_m/D/FCVT-D-W-01", "002010", - "rv64i_m/D/FCVT-D-WU-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-L-D-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-RUP-01", "002010", - "rv64i_m/D/FEQ-D-01", "002010", - "rv64i_m/D/FLD-01", "002520", - "rv64i_m/D/FLE-D-01", "002010", - "rv64i_m/D/FLT-D-01", "002010", - "rv64i_m/D/FMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMADD-D-RDN-01", "003010", - "rv64i_m/D/FMADD-D-RMM-01", "003010", - "rv64i_m/D/FMADD-D-RNE-01", "003010", - "rv64i_m/D/FMADD-D-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-RUP-01", "003010", - "rv64i_m/D/FMAX-D-01", "002010", - "rv64i_m/D/FMIN-D-01", "002010", - "rv64i_m/D/FMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMSUB-D-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-RUP-01", "003010", - "rv64i_m/D/FMUL-D-DYN-RDN-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RMM-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RNE-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RUP-01", "002010", - "rv64i_m/D/FMUL-D-RDN-01", "002010", - "rv64i_m/D/FMUL-D-RMM-01", "002010", - "rv64i_m/D/FMUL-D-RNE-01", "002010", - "rv64i_m/D/FMUL-D-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-RUP-01", "002010", - "rv64i_m/D/FMV-D-X-01", "002010", - "rv64i_m/D/FMV-X-D-01", "002010", - "rv64i_m/D/FNMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMADD-D-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-RUP-01", "003010", - "rv64i_m/D/FSD-01", "002010", - "rv64i_m/D/FSGNJ-D-01", "002010", - "rv64i_m/D/FSGNJN-D-01", "002010", - "rv64i_m/D/FSGNJX-D-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FSQRT-D-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-RUP-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RDN-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RMM-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RNE-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RUP-01", "002010", - "rv64i_m/D/FSUB-D-RDN-01", "002010", - "rv64i_m/D/FSUB-D-RMM-01", "002010", - "rv64i_m/D/FSUB-D-RNE-01", "002010", - "rv64i_m/D/FSUB-D-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-RUP-01", "002010" + "rv64i_m/D/FADD-D-DYN-RDN-01", "002010", + "rv64i_m/D/FADD-D-DYN-RMM-01", "002010", + "rv64i_m/D/FADD-D-DYN-RNE-01", "002010", + "rv64i_m/D/FADD-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FADD-D-DYN-RUP-01", "002010", + "rv64i_m/D/FADD-D-RDN-01", "002010", + "rv64i_m/D/FADD-D-RMM-01", "002010", + "rv64i_m/D/FADD-D-RNE-01", "002010", + "rv64i_m/D/FADD-D-RTZ-01", "002010", + "rv64i_m/D/FADD-D-RUP-01", "002010", + "rv64i_m/D/FCLASS-D-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-D-L-RDN-01", "002010", + "rv64i_m/D/FCVT-D-L-RMM-01", "002010", + "rv64i_m/D/FCVT-D-L-RNE-01", "002010", + "rv64i_m/D/FCVT-D-L-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-L-RUP-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-D-LU-RDN-01", "002010", + "rv64i_m/D/FCVT-D-LU-RMM-01", "002010", + "rv64i_m/D/FCVT-D-LU-RNE-01", "002010", + "rv64i_m/D/FCVT-D-LU-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-LU-RUP-01", "002010", + "rv64i_m/D/FCVT-D-S-01", "002010", + "rv64i_m/D/FCVT-D-W-01", "002010", + "rv64i_m/D/FCVT-D-WU-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-L-D-RDN-01", "002010", + "rv64i_m/D/FCVT-L-D-RMM-01", "002010", + "rv64i_m/D/FCVT-L-D-RNE-01", "002010", + "rv64i_m/D/FCVT-L-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-L-D-RUP-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-LU-D-RDN-01", "002010", + "rv64i_m/D/FCVT-LU-D-RMM-01", "002010", + "rv64i_m/D/FCVT-LU-D-RNE-01", "002010", + "rv64i_m/D/FCVT-LU-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-LU-D-RUP-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-S-D-RDN-01", "002010", + "rv64i_m/D/FCVT-S-D-RMM-01", "002010", + "rv64i_m/D/FCVT-S-D-RNE-01", "002010", + "rv64i_m/D/FCVT-S-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-S-D-RUP-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-W-D-RDN-01", "002010", + "rv64i_m/D/FCVT-W-D-RMM-01", "002010", + "rv64i_m/D/FCVT-W-D-RNE-01", "002010", + "rv64i_m/D/FCVT-W-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-W-D-RUP-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-WU-D-RDN-01", "002010", + "rv64i_m/D/FCVT-WU-D-RMM-01", "002010", + "rv64i_m/D/FCVT-WU-D-RNE-01", "002010", + "rv64i_m/D/FCVT-WU-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-WU-D-RUP-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", + // "rv64i_m/D/FDIV-D-RDN-01", "002010", + // "rv64i_m/D/FDIV-D-RMM-01", "002010", + // "rv64i_m/D/FDIV-D-RNE-01", "002010", + // "rv64i_m/D/FDIV-D-RTZ-01", "002010", + // "rv64i_m/D/FDIV-D-RUP-01", "002010", + "rv64i_m/D/FEQ-D-01", "002010", + "rv64i_m/D/FLD-01", "002520", + "rv64i_m/D/FLE-D-01", "002010", + "rv64i_m/D/FLT-D-01", "002010", + "rv64i_m/D/FMADD-D-DYN-RDN-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RMM-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RNE-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RUP-01", "003010", + "rv64i_m/D/FMADD-D-RDN-01", "003010", + "rv64i_m/D/FMADD-D-RMM-01", "003010", + "rv64i_m/D/FMADD-D-RNE-01", "003010", + "rv64i_m/D/FMADD-D-RTZ-01", "003010", + "rv64i_m/D/FMADD-D-RUP-01", "003010", + "rv64i_m/D/FMAX-D-01", "002010", + "rv64i_m/D/FMIN-D-01", "002010", + "rv64i_m/D/FMSUB-D-DYN-RDN-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RMM-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RNE-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RUP-01", "003010", + "rv64i_m/D/FMSUB-D-RDN-01", "003010", + "rv64i_m/D/FMSUB-D-RMM-01", "003010", + "rv64i_m/D/FMSUB-D-RNE-01", "003010", + "rv64i_m/D/FMSUB-D-RTZ-01", "003010", + "rv64i_m/D/FMSUB-D-RUP-01", "003010", + "rv64i_m/D/FMUL-D-DYN-RDN-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RMM-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RNE-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RUP-01", "002010", + "rv64i_m/D/FMUL-D-RDN-01", "002010", + "rv64i_m/D/FMUL-D-RMM-01", "002010", + "rv64i_m/D/FMUL-D-RNE-01", "002010", + "rv64i_m/D/FMUL-D-RTZ-01", "002010", + "rv64i_m/D/FMUL-D-RUP-01", "002010", + "rv64i_m/D/FMV-D-X-01", "002010", + "rv64i_m/D/FMV-X-D-01", "002010", + "rv64i_m/D/FNMADD-D-DYN-RDN-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RMM-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RNE-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RUP-01", "003010", + "rv64i_m/D/FNMADD-D-RDN-01", "003010", + "rv64i_m/D/FNMADD-D-RMM-01", "003010", + "rv64i_m/D/FNMADD-D-RNE-01", "003010", + "rv64i_m/D/FNMADD-D-RTZ-01", "003010", + "rv64i_m/D/FNMADD-D-RUP-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01", "003010", + "rv64i_m/D/FNMSUB-D-RDN-01", "003010", + "rv64i_m/D/FNMSUB-D-RMM-01", "003010", + "rv64i_m/D/FNMSUB-D-RNE-01", "003010", + "rv64i_m/D/FNMSUB-D-RTZ-01", "003010", + "rv64i_m/D/FNMSUB-D-RUP-01", "003010", + "rv64i_m/D/FSD-01", "002010", + "rv64i_m/D/FSGNJ-D-01", "002010", + "rv64i_m/D/FSGNJN-D-01", "002010", + "rv64i_m/D/FSGNJX-D-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", + // "rv64i_m/D/FSQRT-D-RDN-01", "002010", + // "rv64i_m/D/FSQRT-D-RMM-01", "002010", + // "rv64i_m/D/FSQRT-D-RNE-01", "002010", + // "rv64i_m/D/FSQRT-D-RTZ-01", "002010", + // "rv64i_m/D/FSQRT-D-RUP-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RDN-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RMM-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RNE-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RUP-01", "002010", + "rv64i_m/D/FSUB-D-RDN-01", "002010", + "rv64i_m/D/FSUB-D-RMM-01", "002010", + "rv64i_m/D/FSUB-D-RNE-01", "002010", + "rv64i_m/D/FSUB-D-RTZ-01", "002010", + "rv64i_m/D/FSUB-D-RUP-01", "002010" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01", "004010", - "rv64i_m/M/DIVU-01", "004010", - "rv64i_m/M/DIVUW-01", "003010", - "rv64i_m/M/DIVW-01", "003010", - "rv64i_m/M/MUL-01", "004010", - "rv64i_m/M/MULH-01", "004010", - "rv64i_m/M/MULHSU-01", "004010", - "rv64i_m/M/MULHU-01", "004010", - "rv64i_m/M/MULW-01", "003010", - "rv64i_m/M/REM-01", "004010", - "rv64i_m/M/REMU-01", "004010", - "rv64i_m/M/REMUW-01", "003010", - "rv64i_m/M/REMW-01", "003010" + "rv64i_m/M/DIV-01", "004010", + "rv64i_m/M/DIVU-01", "004010", + "rv64i_m/M/DIVUW-01", "003010", + "rv64i_m/M/DIVW-01", "003010", + "rv64i_m/M/MUL-01", "004010", + "rv64i_m/M/MULH-01", "004010", + "rv64i_m/M/MULHSU-01", "004010", + "rv64i_m/M/MULHU-01", "004010", + "rv64i_m/M/MULW-01", "003010", + "rv64i_m/M/REM-01", "004010", + "rv64i_m/M/REMU-01", "004010", + "rv64i_m/M/REMUW-01", "003010", + "rv64i_m/M/REMW-01", "003010" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01", "003010", - "rv64i_m/C/C-ADDI-01", "003010", - "rv64i_m/C/C-ADDI16SP-01", "003010", - "rv64i_m/C/C-ADDI4SPN-01", "003010", - "rv64i_m/C/C-ADDIW-01", "003010", - "rv64i_m/C/C-ADDW-01", "003010", - "rv64i_m/C/C-AND-01", "003010", - "rv64i_m/C/C-ANDI-01", "003010", - "rv64i_m/C/C-BEQZ-01", "004010", - "rv64i_m/C/C-BNEZ-01", "004010", - "rv64i_m/C/C-J-01", "003010", - "rv64i_m/C/C-JALR-01", "004010", - "rv64i_m/C/C-JR-01", "004010", - "rv64i_m/C/C-LD-01", "003520", - "rv64i_m/C/C-LDSP-01", "003520", - "rv64i_m/C/C-LI-01", "003010", - "rv64i_m/C/C-LUI-01", "002010", - "rv64i_m/C/C-LW-01", "003210", - "rv64i_m/C/C-LWSP-01", "003210", - "rv64i_m/C/C-MV-01", "003010", - "rv64i_m/C/C-OR-01", "003010", - "rv64i_m/C/C-SD-01", "003010", - "rv64i_m/C/C-SDSP-01", "003010", - "rv64i_m/C/C-SLLI-01", "003010", - "rv64i_m/C/C-SRAI-01", "003010", - "rv64i_m/C/C-SRLI-01", "003010", - "rv64i_m/C/C-SUB-01", "003010", - "rv64i_m/C/C-SUBW-01", "003010", - "rv64i_m/C/C-SW-01", "003010", - "rv64i_m/C/C-SWSP-01", "003010", - "rv64i_m/C/C-XOR-01", "003010", - "rv64i_m/C/I-C-EBREAK-01", "002000", - "rv64i_m/C/I-C-NOP-01", "002000" + "rv64i_m/C/C-ADD-01", "003010", + "rv64i_m/C/C-ADDI-01", "003010", + "rv64i_m/C/C-ADDI16SP-01", "003010", + "rv64i_m/C/C-ADDI4SPN-01", "003010", + "rv64i_m/C/C-ADDIW-01", "003010", + "rv64i_m/C/C-ADDW-01", "003010", + "rv64i_m/C/C-AND-01", "003010", + "rv64i_m/C/C-ANDI-01", "003010", + "rv64i_m/C/C-BEQZ-01", "004010", + "rv64i_m/C/C-BNEZ-01", "004010", + "rv64i_m/C/C-J-01", "003010", + "rv64i_m/C/C-JALR-01", "004010", + "rv64i_m/C/C-JR-01", "004010", + "rv64i_m/C/C-LD-01", "003520", + "rv64i_m/C/C-LDSP-01", "003520", + "rv64i_m/C/C-LI-01", "003010", + "rv64i_m/C/C-LUI-01", "002010", + "rv64i_m/C/C-LW-01", "003210", + "rv64i_m/C/C-LWSP-01", "003210", + "rv64i_m/C/C-MV-01", "003010", + "rv64i_m/C/C-OR-01", "003010", + "rv64i_m/C/C-SD-01", "003010", + "rv64i_m/C/C-SDSP-01", "003010", + "rv64i_m/C/C-SLLI-01", "003010", + "rv64i_m/C/C-SRAI-01", "003010", + "rv64i_m/C/C-SRLI-01", "003010", + "rv64i_m/C/C-SUB-01", "003010", + "rv64i_m/C/C-SUBW-01", "003010", + "rv64i_m/C/C-SW-01", "003010", + "rv64i_m/C/C-SWSP-01", "003010", + "rv64i_m/C/C-XOR-01", "003010", + "rv64i_m/C/I-C-EBREAK-01", "002000", + "rv64i_m/C/I-C-NOP-01", "002000" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01", "002000" + "rv64i_m/I/I-MISALIGN_JMP-01", "002000" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/ADD-01", "004010", - "rv64i_m/I/ADDI-01", "003010", - "rv64i_m/I/ADDIW-01", "003010", - "rv64i_m/I/ADDW-01", "003010", - "rv64i_m/I/AND-01", "004010", - "rv64i_m/I/ANDI-01", "003010", - "rv64i_m/I/AUIPC-01", "003010", - "rv64i_m/I/BEQ-01", "005010", - "rv64i_m/I/BGE-01", "005010", - "rv64i_m/I/BGEU-01", "005010", - "rv64i_m/I/BLT-01", "005010", - "rv64i_m/I/BLTU-01", "005010", - "rv64i_m/I/BNE-01", "005010", - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/I-EBREAK-01", "002010", - "rv64i_m/I/I-ECALL-01", "002010", - "rv64i_m/I/I-ENDIANESS-01", "002010", - "rv64i_m/I/I-IO-01", "002050", -// "rv64i_m/I/I-MISALIGN_JMP-01", "002000", - "rv64i_m/I/I-MISALIGN_LDST-01", "002010", - "rv64i_m/I/I-NOP-01", "002000", - "rv64i_m/I/I-RF_size-01", "002000", - "rv64i_m/I/I-RF_width-01", "002000", - "rv64i_m/I/I-RF_x0-01", "002010", - "rv64i_m/I/JAL-01", "004010", - "rv64i_m/I/JALR-01", "005010", - "rv64i_m/I/LB-01", "004120", - "rv64i_m/I/LBU-01", "004120", - "rv64i_m/I/LD-01", "004520", - "rv64i_m/I/LH-01", "004150", - "rv64i_m/I/LHU-01", "004150", - "rv64i_m/I/LUI-01", "002010", - "rv64i_m/I/LW-01", "004210", - "rv64i_m/I/LWU-01", "004210", - "rv64i_m/I/OR-01", "004010", - "rv64i_m/I/ORI-01", "003010", - "rv64i_m/I/SB-01", "004010", - "rv64i_m/I/SD-01", "004010", - "rv64i_m/I/SH-01", "004010", - "rv64i_m/I/SLL-01", "003010", - "rv64i_m/I/SLLI-01", "003010", - "rv64i_m/I/SLLIW-01", "003010", - "rv64i_m/I/SLLW-01", "003010", - "rv64i_m/I/SLT-01", "004010", - "rv64i_m/I/SLTI-01", "003010", - "rv64i_m/I/SLTIU-01", "003010", - "rv64i_m/I/SLTU-01", "004010", - "rv64i_m/I/SRA-01", "003010", - "rv64i_m/I/SRAI-01", "003010", - "rv64i_m/I/SRAIW-01", "003010", - "rv64i_m/I/SRAW-01", "003010", - "rv64i_m/I/SRL-01", "003010", - "rv64i_m/I/SRLI-01", "003010", - "rv64i_m/I/SRLIW-01", "003010", - "rv64i_m/I/SRLW-01", "003010", - "rv64i_m/I/SUB-01", "004010", - "rv64i_m/I/SUBW-01", "003010", - "rv64i_m/I/SW-01", "004010", - "rv64i_m/I/XOR-01", "004010", - "rv64i_m/I/XORI-01", "003010" + "rv64i_m/I/I-DELAY_SLOTS-01", "002010", + "rv64i_m/I/ADD-01", "004010", + "rv64i_m/I/ADDI-01", "003010", + "rv64i_m/I/ADDIW-01", "003010", + "rv64i_m/I/ADDW-01", "003010", + "rv64i_m/I/AND-01", "004010", + "rv64i_m/I/ANDI-01", "003010", + "rv64i_m/I/AUIPC-01", "003010", + "rv64i_m/I/BEQ-01", "005010", + "rv64i_m/I/BGE-01", "005010", + "rv64i_m/I/BGEU-01", "005010", + "rv64i_m/I/BLT-01", "005010", + "rv64i_m/I/BLTU-01", "005010", + "rv64i_m/I/BNE-01", "005010", + "rv64i_m/I/I-DELAY_SLOTS-01", "002010", + "rv64i_m/I/I-EBREAK-01", "002010", + "rv64i_m/I/I-ECALL-01", "002010", + "rv64i_m/I/I-ENDIANESS-01", "002010", + "rv64i_m/I/I-IO-01", "002050", +// "rv64i_m/I/I-MISALIGN_JMP-01", "002000", + "rv64i_m/I/I-MISALIGN_LDST-01", "002010", + "rv64i_m/I/I-NOP-01", "002000", + "rv64i_m/I/I-RF_size-01", "002000", + "rv64i_m/I/I-RF_width-01", "002000", + "rv64i_m/I/I-RF_x0-01", "002010", + "rv64i_m/I/JAL-01", "004010", + "rv64i_m/I/JALR-01", "005010", + "rv64i_m/I/LB-01", "004120", + "rv64i_m/I/LBU-01", "004120", + "rv64i_m/I/LD-01", "004520", + "rv64i_m/I/LH-01", "004150", + "rv64i_m/I/LHU-01", "004150", + "rv64i_m/I/LUI-01", "002010", + "rv64i_m/I/LW-01", "004210", + "rv64i_m/I/LWU-01", "004210", + "rv64i_m/I/OR-01", "004010", + "rv64i_m/I/ORI-01", "003010", + "rv64i_m/I/SB-01", "004010", + "rv64i_m/I/SD-01", "004010", + "rv64i_m/I/SH-01", "004010", + "rv64i_m/I/SLL-01", "003010", + "rv64i_m/I/SLLI-01", "003010", + "rv64i_m/I/SLLIW-01", "003010", + "rv64i_m/I/SLLW-01", "003010", + "rv64i_m/I/SLT-01", "004010", + "rv64i_m/I/SLTI-01", "003010", + "rv64i_m/I/SLTIU-01", "003010", + "rv64i_m/I/SLTU-01", "004010", + "rv64i_m/I/SRA-01", "003010", + "rv64i_m/I/SRAI-01", "003010", + "rv64i_m/I/SRAIW-01", "003010", + "rv64i_m/I/SRAW-01", "003010", + "rv64i_m/I/SRL-01", "003010", + "rv64i_m/I/SRLI-01", "003010", + "rv64i_m/I/SRLIW-01", "003010", + "rv64i_m/I/SRLW-01", "003010", + "rv64i_m/I/SUB-01", "004010", + "rv64i_m/I/SUBW-01", "003010", + "rv64i_m/I/SW-01", "004010", + "rv64i_m/I/XOR-01", "004010", + "rv64i_m/I/XORI-01", "003010" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01", "002010", - "rv32i_m/M/DIVU-01", "002010", - "rv32i_m/M/MUL-01", "002010", - "rv32i_m/M/MULH-01", "002010", - "rv32i_m/M/MULHSU-01", "002010", - "rv32i_m/M/MULHU-01", "002010", - "rv32i_m/M/REM-01", "002010", - "rv32i_m/M/REMU-01", "002010" + "rv32i_m/M/DIV-01", "002010", + "rv32i_m/M/DIVU-01", "002010", + "rv32i_m/M/MUL-01", "002010", + "rv32i_m/M/MULH-01", "002010", + "rv32i_m/M/MULHSU-01", "002010", + "rv32i_m/M/MULHU-01", "002010", + "rv32i_m/M/REM-01", "002010", + "rv32i_m/M/REMU-01", "002010" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01", "002010", - "rv32i_m/C/C-ADDI-01", "002010", - "rv32i_m/C/C-ADDI16SP-01", "002010", - "rv32i_m/C/C-ADDI4SPN-01", "002010", - "rv32i_m/C/C-AND-01", "002010", - "rv32i_m/C/C-ANDI-01", "002010", - "rv32i_m/C/C-BEQZ-01", "003010", - "rv32i_m/C/C-BNEZ-01", "003010", - "rv32i_m/C/C-J-01", "002010", - "rv32i_m/C/C-JAL-01", "002010", - "rv32i_m/C/C-JALR-01", "003010", - "rv32i_m/C/C-JR-01", "003010", - "rv32i_m/C/C-LI-01", "002010", - "rv32i_m/C/C-LUI-01", "002010", - "rv32i_m/C/C-LW-01", "002120", - "rv32i_m/C/C-LWSP-01", "002120", - "rv32i_m/C/C-MV-01", "002010", - "rv32i_m/C/C-OR-01", "002010", - "rv32i_m/C/C-SLLI-01", "002010", - "rv32i_m/C/C-SRAI-01", "002010", - "rv32i_m/C/C-SRLI-01", "002010", - "rv32i_m/C/C-SUB-01", "002010", - "rv32i_m/C/C-SW-01", "002010", - "rv32i_m/C/C-SWSP-01", "002010", - "rv32i_m/C/C-XOR-01", "002010", - "rv32i_m/C/I-C-EBREAK-01", "002000", - "rv32i_m/C/I-C-NOP-01", "002000" + "rv32i_m/C/C-ADD-01", "002010", + "rv32i_m/C/C-ADDI-01", "002010", + "rv32i_m/C/C-ADDI16SP-01", "002010", + "rv32i_m/C/C-ADDI4SPN-01", "002010", + "rv32i_m/C/C-AND-01", "002010", + "rv32i_m/C/C-ANDI-01", "002010", + "rv32i_m/C/C-BEQZ-01", "003010", + "rv32i_m/C/C-BNEZ-01", "003010", + "rv32i_m/C/C-J-01", "002010", + "rv32i_m/C/C-JAL-01", "002010", + "rv32i_m/C/C-JALR-01", "003010", + "rv32i_m/C/C-JR-01", "003010", + "rv32i_m/C/C-LI-01", "002010", + "rv32i_m/C/C-LUI-01", "002010", + "rv32i_m/C/C-LW-01", "002120", + "rv32i_m/C/C-LWSP-01", "002120", + "rv32i_m/C/C-MV-01", "002010", + "rv32i_m/C/C-OR-01", "002010", + "rv32i_m/C/C-SLLI-01", "002010", + "rv32i_m/C/C-SRAI-01", "002010", + "rv32i_m/C/C-SRLI-01", "002010", + "rv32i_m/C/C-SUB-01", "002010", + "rv32i_m/C/C-SW-01", "002010", + "rv32i_m/C/C-SWSP-01", "002010", + "rv32i_m/C/C-XOR-01", "002010", + "rv32i_m/C/I-C-EBREAK-01", "002000", + "rv32i_m/C/I-C-NOP-01", "002000" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01", "002000" + "rv32i_m/I/I-MISALIGN_JMP-01", "002000" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01", "002010", - "rv32i_m/I/ADDI-01", "002010", - "rv32i_m/I/AND-01", "002010", - "rv32i_m/I/ANDI-01", "002010", - "rv32i_m/I/AUIPC-01", "002010", - "rv32i_m/I/BEQ-01", "003010", - "rv32i_m/I/BGE-01", "003010", - "rv32i_m/I/BGEU-01", "003010", - "rv32i_m/I/BLT-01", "003010", - "rv32i_m/I/BLTU-01", "003010", - "rv32i_m/I/BNE-01", "003010", - "rv32i_m/I/I-DELAY_SLOTS-01", "002010", - "rv32i_m/I/I-EBREAK-01", "002010", - "rv32i_m/I/I-ECALL-01", "002010", - "rv32i_m/I/I-ENDIANESS-01", "002010", - "rv32i_m/I/I-IO-01", "002030", -// "rv32i_m/I/I-MISALIGN_JMP-01", "002000", - "rv32i_m/I/I-MISALIGN_LDST-01", "002010", - "rv32i_m/I/I-NOP-01", "002000", - "rv32i_m/I/I-RF_size-01", "002000", - "rv32i_m/I/I-RF_width-01", "002000", - "rv32i_m/I/I-RF_x0-01", "002010", - "rv32i_m/I/JAL-01", "003010", - "rv32i_m/I/JALR-01", "003010", - "rv32i_m/I/LB-01", "003030", - "rv32i_m/I/LBU-01", "003030", - "rv32i_m/I/LH-01", "003060", - "rv32i_m/I/LHU-01", "003060", - "rv32i_m/I/LUI-01", "002010", - "rv32i_m/I/LW-01", "003120", - "rv32i_m/I/OR-01", "002010", - "rv32i_m/I/ORI-01", "002010", - "rv32i_m/I/SB-01", "003010", - "rv32i_m/I/SH-01", "003010", - "rv32i_m/I/SLL-01", "002010", - "rv32i_m/I/SLLI-01", "002010", - "rv32i_m/I/SLT-01", "002010", - "rv32i_m/I/SLTI-01", "002010", - "rv32i_m/I/SLTIU-01", "002010", - "rv32i_m/I/SLTU-01", "002010", - "rv32i_m/I/SRA-01", "002010", - "rv32i_m/I/SRAI-01", "002010", - "rv32i_m/I/SRL-01", "002010", - "rv32i_m/I/SRLI-01", "002010", - "rv32i_m/I/SUB-01", "002010", - "rv32i_m/I/SW-01", "003010", - "rv32i_m/I/XOR-01", "002010", - "rv32i_m/I/XORI-01", "002010" + "rv32i_m/I/ADD-01", "002010", + "rv32i_m/I/ADDI-01", "002010", + "rv32i_m/I/AND-01", "002010", + "rv32i_m/I/ANDI-01", "002010", + "rv32i_m/I/AUIPC-01", "002010", + "rv32i_m/I/BEQ-01", "003010", + "rv32i_m/I/BGE-01", "003010", + "rv32i_m/I/BGEU-01", "003010", + "rv32i_m/I/BLT-01", "003010", + "rv32i_m/I/BLTU-01", "003010", + "rv32i_m/I/BNE-01", "003010", + "rv32i_m/I/I-DELAY_SLOTS-01", "002010", + "rv32i_m/I/I-EBREAK-01", "002010", + "rv32i_m/I/I-ECALL-01", "002010", + "rv32i_m/I/I-ENDIANESS-01", "002010", + "rv32i_m/I/I-IO-01", "002030", +// "rv32i_m/I/I-MISALIGN_JMP-01", "002000", + "rv32i_m/I/I-MISALIGN_LDST-01", "002010", + "rv32i_m/I/I-NOP-01", "002000", + "rv32i_m/I/I-RF_size-01", "002000", + "rv32i_m/I/I-RF_width-01", "002000", + "rv32i_m/I/I-RF_x0-01", "002010", + "rv32i_m/I/JAL-01", "003010", + "rv32i_m/I/JALR-01", "003010", + "rv32i_m/I/LB-01", "003030", + "rv32i_m/I/LBU-01", "003030", + "rv32i_m/I/LH-01", "003060", + "rv32i_m/I/LHU-01", "003060", + "rv32i_m/I/LUI-01", "002010", + "rv32i_m/I/LW-01", "003120", + "rv32i_m/I/OR-01", "002010", + "rv32i_m/I/ORI-01", "002010", + "rv32i_m/I/SB-01", "003010", + "rv32i_m/I/SH-01", "003010", + "rv32i_m/I/SLL-01", "002010", + "rv32i_m/I/SLLI-01", "002010", + "rv32i_m/I/SLT-01", "002010", + "rv32i_m/I/SLTI-01", "002010", + "rv32i_m/I/SLTIU-01", "002010", + "rv32i_m/I/SLTU-01", "002010", + "rv32i_m/I/SRA-01", "002010", + "rv32i_m/I/SRAI-01", "002010", + "rv32i_m/I/SRL-01", "002010", + "rv32i_m/I/SRLI-01", "002010", + "rv32i_m/I/SUB-01", "002010", + "rv32i_m/I/SW-01", "003010", + "rv32i_m/I/XOR-01", "002010", + "rv32i_m/I/XORI-01", "002010" }; string testsBP64[] = '{ @@ -1468,10 +1475,10 @@ string imperas32f[] = '{ string wally64i[] = '{ `WALLYTEST, "rv64i_m/I/WALLY-ADD", "002010", - "rv64i_m/I/WALLY-SLT", "002010", - "rv64i_m/I/WALLY-SLTU", "002010", - "rv64i_m/I/WALLY-SUB", "002010", - "rv64i_m/I/WALLY-XOR", "002010" + "rv64i_m/I/WALLY-SLT", "002010", + "rv64i_m/I/WALLY-SLTU", "002010", + "rv64i_m/I/WALLY-SUB", "002010", + "rv64i_m/I/WALLY-XOR", "002010" }; string wally64priv[] = '{ @@ -1480,20 +1487,63 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-MMU-SV48", "30A0", "rv64i_m/privilege/WALLY-PMP", "30A0", "rv64i_m/privilege/WALLY-PMA", "30A0", - "rv64i_m/privilege/WALLY-minfo-01", "30A0" + "rv64i_m/privilege/WALLY-minfo-01", "30A0", + "rv64i_m/privilege/WALLY-CSR-permission-s-01", "40A0", + "rv64i_m/privilege/WALLY-CSR-permission-u-01", "40A0" }; string wally64periph[] = '{ `WALLYTEST }; + string wally32e[] = '{ + `WALLYTEST, + "rv32i_m/I/E-beq-01", "03b010", + "rv32i_m/I/E-add-01", "005010", + "rv32i_m/I/E-addi-01", "004010", + "rv32i_m/I/E-and-01", "005010", + "rv32i_m/I/E-andi-01", "004010", + "rv32i_m/I/E-auipc-01", "002010", + "rv32i_m/I/E-bge-01", "034010", + "rv32i_m/I/E-bgeu-01", "047010", + "rv32i_m/I/E-blt-01", "038010", + "rv32i_m/I/E-bltu-01", "03e010", + "rv32i_m/I/E-bne-01", "038010", + "rv32i_m/I/E-jal-01", "e02010", + "rv32i_m/I/E-jalr-01", "002010", + "rv32i_m/I/E-lb-align-01", "002010", + "rv32i_m/I/E-lbu-align-01", "002010", + "rv32i_m/I/E-lh-align-01", "002010", + "rv32i_m/I/E-lhu-align-01", "002010", + "rv32i_m/I/E-lui-01", "002010", + "rv32i_m/I/E-lw-align-01", "002010", + "rv32i_m/I/E-or-01", "005010", + "rv32i_m/I/E-ori-01", "004010", + "rv32i_m/I/E-sb-align-01", "002010", + "rv32i_m/I/E-sh-align-01", "002010", + "rv32i_m/I/E-sll-01", "002010", + "rv32i_m/I/E-slli-01", "002010", + "rv32i_m/I/E-slt-01", "005010", + "rv32i_m/I/E-slti-01", "004010", + "rv32i_m/I/E-sltiu-01", "004010", + "rv32i_m/I/E-sltu-01", "005010", + "rv32i_m/I/E-sra-01", "002010", + "rv32i_m/I/E-srai-01", "002010", + "rv32i_m/I/E-srl-01", "002010", + "rv32i_m/I/E-srli-01", "002010", + "rv32i_m/I/E-sub-01", "005010", + "rv32i_m/I/E-sw-align-01", "002010", + "rv32i_m/I/E-xor-01", "005010", + "rv32i_m/I/E-xori-01", "004010" + }; + string wally32i[] = '{ `WALLYTEST, "rv32i_m/I/WALLY-ADD", "002010", - "rv32i_m/I/WALLY-SLT", "002010", - "rv32i_m/I/WALLY-SLTU", "002010", - "rv32i_m/I/WALLY-SUB", "002010", - "rv32i_m/I/WALLY-XOR", "002010" + "rv32i_m/I/WALLY-SLT", "002010", + "rv32i_m/I/WALLY-SLTU", "002010", + "rv32i_m/I/WALLY-SUB", "002010", + "rv32i_m/I/WALLY-XOR", "002010" }; string wally32priv[] = '{ diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index e4441ef36..f5d7f0ece 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -3,7 +3,7 @@ set CURRENT_DIR [exec pwd] set search_path [list "./" ] -set s8lib ../addins/sky130_osu_sc_t18/18T_ms/lib +set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib lappend search_path $s8lib # Synthetic libraries @@ -12,7 +12,7 @@ set synthetic_library [list dw_foundation.sldb] # Set OKSTATE standard cell libraries set target_library [list] -lappend target_library sky130_osu_sc_18T_ms_TT_1P8_25C.ccs.db +lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db # Set Link Library set link_library "$target_library $synthetic_library" diff --git a/synthDC/hdl/wally-shared.vh b/synthDC/hdl/wally-shared.vh new file mode 100644 index 000000000..277814f80 --- /dev/null +++ b/synthDC/hdl/wally-shared.vh @@ -0,0 +1,62 @@ +////////////////////////////////////////// +// wally-shared.vh +// +// Written: david_harris@hmc.edu 7 June 2021 +// +// Purpose: Shared and default configuration values common to all designs +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// include shared constants +`include "wally-constants.vh" + +// macros to define supported modes +// NOTE: No hardware support fo Q yet + +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) + +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + + +// logarithm of XLEN, used for number of index bits to select +`define LOG_XLEN (`XLEN == 32 ? 5 : 6) + +// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) +`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) + +// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits +`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32) +`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8) +`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23) + +// Disable spurious Verilator warnings + +/* verilator lint_off STMTDLY */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index a52abaa91..23a305937 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -6,11 +6,11 @@ # Config set hdl_src "../pipelined/src" -eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/} -eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/} -eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/} -eval file copy [glob ${hdl_src}/*/*.sv] {hdl/} -eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/} +eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {hdl/} +eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {reports/} +eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} +eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} +eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} # Verilog files set my_verilog_files [glob hdl/*] @@ -47,7 +47,7 @@ reset_design # Set Frequency in [MHz] or [ps] set my_clock_pin clk -set my_clk_freq_MHz 10 +set my_clk_freq_MHz 500 set my_period [expr 1000 / $my_clk_freq_MHz] set my_uncertainty [expr .1 * $my_period] @@ -76,14 +76,14 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] set_propagated_clock [get_clocks $my_clk] # Setting constraints on input ports -set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk +set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk # Set input/output delay set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_output_delay 0.0 -max -clock $my_clk [all_outputs] # Setting load constraint on output ports -set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs] +set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] # Set the wire load model set_wire_load_mode "top" @@ -111,7 +111,7 @@ write_file -format ddc -hierarchy -o $filename # Compile statements - either compile or compile_ultra # compile -scan -incr -map_effort low -# compile_ultra -no_seq_output_inversion -no_boundary_optimization +compile_ultra -no_seq_output_inversion -no_boundary_optimization # Eliminate need for assign statements (yuck!) set verilogout_no_tri true diff --git a/tests/linux-testgen/buildroot-config-src/make-buildroot.sh b/tests/linux-testgen/buildroot-config-src/make-buildroot.sh deleted file mode 100755 index 841db1ba4..000000000 --- a/tests/linux-testgen/buildroot-config-src/make-buildroot.sh +++ /dev/null @@ -1,3 +0,0 @@ -cp main.config ../buildroot/.config -cd ../buildroot -make diff --git a/tests/wally-riscv-arch-test/CHANGELOG.md b/tests/wally-riscv-arch-test/CHANGELOG.md deleted file mode 100644 index cf6144267..000000000 --- a/tests/wally-riscv-arch-test/CHANGELOG.md +++ /dev/null @@ -1,413 +0,0 @@ -# CHANGELOG - -## [2.5.3] - 2021-10-15 - - fix the lower case `i` in the `RVTEST_CASE` macros used in the shift operation tests. - -## [2.5.2] - 2021-10-14 - - update format for aes32 and sm4 instructions - - update reference signature for sha256 and sm3 instructions in rv64i_m/K_unratified - - delete zip and unzip tests in rv64i_m/K_unratified - - update tests for aes64ks1i, sm4ed and sm4ks to use byte_count with overlap = "Y" to improve the coverage of S-boxes - -## [2.5.1] - 2021-10-07 - - added styles files to the F coverage report directories. - -## [2.5.0] - 2021-10-01 - - Added rv32f tests, references, coverage files and data propagation reports - - fixed broken links in READMEs across the repo. - - corrected string "EBREAK" in io string macro to "ECALL" for ecall.S tests. #207 - - fixed typo `.alive` --> `.align` in `riscv-target/example_target/model_test.h`. - -## [2.4.7] - 2021-10-01 - - Fix for the issue #206 - -## [2.4.6] - 2021-08-02 - - Added rv32e tests in riscv-test-suite - -## [2.4.5] - 2021-07-29 - - fix for issue #195 - -## [2.4.4] - 2021-07-19 - - Annotating tags during releases - -## [2.4.3] - 2021-05-20 - - added new 64-bit K crypto tests as per the test-plan presented by the scalar crypto task group - [here](https://github.com/riscv/riscv-crypto/blob/d89dfee25780f79c162da4eb69cd9076dd701c88/tests/compliance/test-plan-scalar.adoc) - - added new 32-bit K crypto tests as per the above mentioned test-plan. - - added coverage and data propagation reports for the above tests. - - updated README in riscv-test-suite - - added missing semi-colon in example target Makefile.include files - -## [2.4.2] - 2021-04-20 - - changed all occurances of SPTBR to the new name SATP - -## [2.4.1] - 2021-04-01 - - updated issue number in TestFormatSpec to be consistent with doc history - - adding a contribution guideline - - updated comment on usage of RISCV_DEVICE in Makefile.include - - updated licenses that are currently used by tests - - renamed K tests to K_unratified - - updated ci to build and upload pdf for testformatspec - -## [2.4.0] - 2021-03-26 -2021-03-26 Duncan Graham - - Added new K Crypto (scalar) (0.8.1) tests from Imperas - -## [2.3.1] - 2021-03-20 -### Changed - - Compliance Task Group changed to Architecture Test SIG in all docs and comments - - replacing old riscv-compliance link with new riscv-arch-test links - - fixed ci for release -### Removed - - spec/TestFormatSpec.pdf is removed since its old. Keeping only adoc file - - removing obsolete and commented out portions from doc/README - -## [2.3] - 2021-03-11 -### Added - - updated maintainers list in root-level readme - - updated the links to riscof, isac and ctg repos and docs in root-level readme - - adding CI to update versions automatically -### Removed - - replaced spike target with a REAMDE pointing to riscv-isa-sim/arch_test_target/README.md - -## [2.2] - 2021-01-28 - 2021-01-22 Tobias Wölfel - * Add missing base ISA check in riscv-test-suite - - 2021-01-20 Xiretza - * Deduplicate makefiles in riscv-test-suite - * Makefile: Fix ordering of simulate and verify targets to allow multi-job runs (make -j) - * Makefile.include: Document RISCV_TEST - * Makefile: use $(TARGETDIR) variable for postverify target instead of hard-coded path - - 2021-01-16 S Pawan Kumar - * Fixed NARGS macro defintion to work correctly. - - 2021-01-15 Xiretza - * style: Add a missing space to the "OK" message in verify.sh - - 2020-12-17 Neel Gala - * remove env folder symlinks from all riscv-test-suite src folders - * fixed assertion macros for ovpsim - * renamed RVTEST_ASSERT to RVMODEL_ASSERT in the Makefile and ovpsim macros - * tests updated with right set of "correctvals" - - 2020-11-24 Neel Gala - * added MIGRATION.adoc in doc directory to indicate how old framework targets can work with - changes made as part of this PR - * updated doc/README.adoc to avoid the word "compliance" and updated the section on porting a new - target to the framework. - * Added an example_target directory to host dummy files which can be used as a starting point for - porting targets. This was provided by MarcKarasek. - * migrated/ported existing targets (except codasip and sifive-formal) to the new framework - changes. - * in riscv-test-env/p/riscv_test.h changed names of RVTEST_[CODE/DATA]_[BEGIN/END] to - RVTEST_[CODE/DATA]_[BEGIN/END]_OLD respectively to avoid conflicts with the new framework macros. - * in riscv-test-env/p/riscv_test.h re-strutucture RVTEST_DATA_BEGIN_OLD/END to ensure that all - target specific data contents are introduced in RVTEST_DATA_END after the signature. - * added new file riscv-test-suite/env/arch_test.h which contains the macros used by the new set of - tests. A symlink to this in the riscv-test-env directory is also created. The arch_test also - includes aliases for the old macros. - * encoding.h moved to riscv-test-suite/env and a symlink to this file exists in riscv-test-env. - This was done to ensure that the arch_test.h and encoding.h are not to be modified by the - targets - * Added riscv-test-stats which includes coverage and data propagation reports for the tests - available in the riscv-test-suite directory. - * upddted the directory structure of the riscv-test-suite as per definition found in the - TestFormatSpec document. - * new set of tests with better coverage for rv[32/64][I,M,C, Zifencei] added. Almost all tests - were generated using the open source riscv_ctg tool. A few tests like fence, fencei, ebreak, - ecall, etc were handwritten/modified to follow the new macro conventions. - * Updated TestFormatSpec to avoid the word compliance and also updated the definitions of macros - and signatures - * created a root-level Makefile.include to decouple the Makefile and target specific settings. - * Added riscv-target and Makefile.include to the .gitignore file to stop tracking target specific - changes. - * Added special targets for compile(build), simulate(run) and verify in the Makefiles of each - test-suite. - * the existing riscv-targets have been either updated for the new framework or migrated to the - framework. - - 2020-10-15 Simon Davidmann - * riscvOVPsim enhanced and moved to its own respository: github.com/riscv-ovpsim - - 2020-04-24 Allen Baum - * fixed the I-SB-01.S and I-SH-01.S tests and associated reference signatures to account - of tests with negative offsets (which causes stores outside the signature area) - - 2020-03-19 Neel Gala - * restructuring the riscv-test-suite to indicate clearly what is deprecated, wip and usable - tests. - * based on the above fixed the directory structure for riscv-targets where-ever applicable. Only - tested riscvOVPsim and spike. - * fixed script bugs for spike as well - * renamed rv32i/I-IO.S to rv32i/I-IO-01.S along with necessary changes to the reference files - and Makefrag - * renamed mbadaddr csr to mtval as raised in issue #31 - * C.SWSP-01.S test updated to fix issue #37 - - 2020-03-18 Neel Gala - * fixed doc/README.adoc with correct version to pass the sanity-check in the doc/Makefile - - 2020-02-07 Prashanth Mundkur - * Support F extension on RV32 sail-riscv-c. - - 2019-12-01 Allen Baum - * modified macro names to conformn to riscof naming convention of model specific vs. pre-defined - * add more complete list of macros, their uses, parameters, and whether they are required or optional - * minor structural changes (moving sentences, renumbering) and typo fixes - * clarified impact of debug macros - * clarified how SIGUPD and BASEUPD must be used - * remove section about test taxonomy, binary tests, emulated ops - * clarify/fix boundary between test target and framework responsibilities - (split test target into test target and test shell) - * remove To Be discussed items that have been discussed - * remove default case condition; if conditions are unchanged, part of same case - * minor grammatical changes related to the above - - 2019-10-16 Allen Baum - * spec/TestFormatSpec.adoc: changed the format of the signature to fixed physical address size, fixed 32b data size extracted from COMPLIANCE_DATA_BEGIN/END range. - - * more gramatical fixes, clarifications added - * added To Be Discussed items regarding emulated instruction and binary tests - - 2019-09-11 Allen Baum - * spec/TestFormatSpec.adoc: more grammar and typo corrections and changes - clarified and added To Be Discussed issues - - 2019-09-11 Allen Baum - * spec/TestFormatSpec.adoc: many grammar and typo corrections and changes - removed many "to Be Discussed items and made them official - Added wording to clarify spec intent (work in progress/goal rather than final) - Added macros to ease test authoring: RVTEST_SIGBASE, RVTEST_SIGUPDATE, RVTEST_CASE - Added detail on proposals for connection to framework (how framework selects tests). - Expanded definition of signature format - Changed the (proposed) directory structure and naming convention to eliminate ambiguities, add consistancy and slightly better match existing structure - Added many "future work" items related to the above - Added examples and comments to code examples to indicate how proposed macros would be used - * .gitignore: added condition to ignore Mac file system artifacts - - - 2019-11-05 Lee Moore - * Restructured RV32I to move Zicsr and Zifencei into their own suites - - 2019-10-14 Lee Moore - * Added Ability to run a single test by using the Make Variable RISCV_TEST - for example, to only run the test I-ADD-01 from the rv32i suite - make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 - * Added Top Level Variable to Makefile RISCV_TARGET_FLAGS, - in the case of the RISCV_TARGET this can be passed and appended to the invocation - commandline configuration, for example to pass a command line flag to the RISCV_TARGET - to perform tracing. The value of this flag will be target specific - make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 RISCV_TARGET_FLAGS="--trace" - This is has also been added to all other targets to allow target configuration from - the commandline - - 2019-10-07 Philipp Wagner - * When executing the test suite, Ibex always writes an instruction - log. Update the Makefile to write it to a test-specific location - (next to all other log files). - * On Ibex, provide an additional .objdump-noalias disassembly file - with no aliases and numeric register names (instead of ABI names). - This file matches the Ibex trace and can be used to debug the test - runs. - - 2019-08-29 Robert Balas - * Added support for using RI5CY as a target. - * Added subdirectory riscv-target/ri5cy - - 2019-08-08 Lee Moore - * Added support for lowRISC/ibex RTL as a target using Verilator. - In conjunction with Philipp Wagner of lowRISC phw@lowrisc.org - - 2019-07-18 Paul Donahue - * Fix typos/grammar and use correct architectural terms. - - 2019-06-21 Ben Selfridge - * Added support for using the the GRIFT simulator as a target. - * Added subdirectory riscv-target/grift - * updated README.md and doc/README.adoc - - 2019-05-23 Prashanth Mundkur - * Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets. - * added subdirectories riscv-target/sail-riscv-c and riscv-target/sail-riscv-ocaml - * updated README.md and doc/README.adoc - - 2019-04-05 Allen Baum - * spec/TestFormatSpec.adoc: Adding details, minor corrections, ToBeDiscussed - items and clarifications to the specification of the future compliance test - suite. Also removing restrictions on having absolate addresses in signature - - 2019-02-21 Lee Moore - * Fixed bug in RVTEST_IO_ASSERT_GPR_EQ which was not preserving register t0 - * Corrected commit I-LUI-01.S, register target changed but missed assertion - - 2019-02-21 Deborah Soung - * added RiscvFormalSpec as a target with its own unique environment - - 2019-02-15 Radek Hajek - * updated rv32i tests to support all registers (x31) with assertions - * updated spec/TestFormatSpec.adoc example ISA test with new assertions - - 2019-02-05 Deborah Soung - * [Issue #33] fixing rv32si/ma_fetch.S test - * [Issue #32] fixing breakpoint test - - 2019-02-01 Lee Moore - * updated Infrastructure macros to support non-volatile registers - * updated riscvOVPsim - - 2019-01-29 Deborah Soung - * Added Rocket Chip generated cores as a target - * riscv-target/rocket/compliance_io.h created - * riscv-target/rocket/compliance_test.h created - * riscv-target/rocket/*/Makefile.include created for existing test suites - * README.adoc updated with instructions for using Rocket cores as targets - - 2019-01-22 Premysl Vaclavik - * feature: initial version of Compliance Test Format Specification - * This new document outlines how we should like the compliance - system to work going forward. By contrast the doc/README.adoc file - describes the current system as it is. - * Approved at Compliance TG meeting of 9 Jan 2019. - - 2019-01-02 Radek Hajek - * unified macros in all compliance tests - - 2018-12-20 Lee Moore - * fixed riscvOVPsim - - 2018-11-22 Simon Davidmann - * added information on test suite status - - 2018-11-21 Olof Kindgren - * Added support for using external target directories with $TARGETDIR - - 2018-11-21 Neel Gala - * riscv-test-suite/rv_/references/_.reference_output: changed signature - format for all tests to include only 4-bytes per line starting with the - most significant byte on the left. - * riscv-target/spike/device/rv_/Makefile.include: Added a patch for - spike-device Makefiles where the old-signature format is post-processed - to generate a signature in the new format at the end of each test. - * riscv-target/riscvOVPsim/device/rv_/Makefile.include: same patch as above. - * Makefile: default target for Makefile is now to run all tests supported by - the target mentioned defined by RISCV_TARGET variable. - - 2018-10-11 Simon Davidmann - * Ported github riscv/riscv-tests for RV32 processors to this compliance env - * rv32ua rv32uc rv32ud rv32uf rv32ud rv32ui - - 2018-09-10 Lee Moore - * Added tests to RV32I to improve coverage, usage of Imperas Mutating Fault Simulator to - identify untested usage cases - * Macro renames to support GPR, (S)FPR, (D)FPR - * Added test suite RV32IM to test 32 bit Multiply and Divide instructions - * Added test suite RV32IMC to test 32 bit Compressed instructions - * Added test suite RV64I to test 64 bit Integer instructions - * Added test suite RV64IM to test 64 bit Multiply and Divide instructions - - - 2018-06-15 Radek Hajek - - Modifications to support Codasip simulator. - - The simulator is renamed as Codasip-simulator (was - Codasip-IA-simulator), compliance_test.h has been moved to target - directories and a COMPILE_TARGET has been added to Makefile to - allow use of LLVM. - - * Makefile: Include Codasip simulator target. - * riscv-target/codasip-IA-simulator/compliance_io.h: Renamed as - riscv-target/Codasip-simulator/compliance_io.h. - * riscv-target/Codasip-simulator/compliance_io.h: Renamed from - riscv-target/codasip-IA-simulator/compliance_io. - * riscv-target/Codasip-simulator/compliance_test.h: Created. - * riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include: - Renamed as - riscv-target/Codasip-simulator/device/rv32i/Makefile.include - * riscv-target/Codasip-simulator/device/rv32i/Makefile.include: - Renamed from - riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include. - * riscv-test-env/compliance_test.h: Renamed as - riscv-target/riscvOVPsim/compliance_test.h. - * riscv-target/riscvOVPsim/compliance_test.h: Renamed from - riscv-test-env/compliance_test.h. - * riscv-target/riscvOVPsim/device/rv32i/Makefile.include: Updated - for new environment. - * riscv-target/spike/compliance_test.h: Created. - * riscv-target/spike/device/rv32i/Makefile.include: Updated for - new environment. - * riscv-test-suite/rv32i/Makefile: Likewise. - - 2018-06-10 Jeremy Bennett - - Put placeholders in empty directories to make sure they show in - the GitHub hierarchy. - - * riscv-test-suite/rv32i/.gitignore: Created. - * riscv-test-suite/rv32m/.gitignore: Created. - - 2018-06-10 Jeremy Bennett - - * README.md: Make references to files in the repo into links. - - 2018-06-09 Jeremy Bennett - - * .gitignore: Ignore editor backup files. - - 2018-06-09 Jeremy Bennett - - * README.md: Add better link to documentation README.md. - - 2018-06-08 Jeremy Bennett - - * README.md: Move AsciiDoc details into new README.md in the doc - directory. - - 2018-06-08 Jeremy Bennett - - * README.md: Fix typo in link to AsciiDoc cheat sheet - - 2018-06-08 Jeremy Bennett - - * COPYING.BSD: Created. - * COPYING.CC: Created. - * README.md: Add git process, licensing and engineering process. - - 2018-06-08 Jeremy Bennett - - * README.md: Correct details for running the compliance tests and - directory for OVPsim. - - 2018-06-08 Jeremy Bennett - - Clean restructuring to just the work of interest. - - * thought-experiments: Directory removed. - * .gitignore: Merged with TestStructure/.gitignore - * Makefile: Renamed from TestStructure/Makefile. - * TestStructure/Makefile: Renamed as Makefile. - * README.md: Merged with TestStructure/README.md. - * TestStructure/.gitignore: Deleted and contents moved into - .gitignore. - * TestStructure/README.md: Deleted and contents moved into - README.md. - * TestStructure/doc: Directory deleted. - * TestStructure/riscv-target: Directory moved to riscv-target. - * riscv-target: Directory moved from TestStructure/riscv-target - * TestStructure/riscv-test-env: Directory moved to riscv-test-env. - * riscv-test-env: Directory moved from - TestStructure/riscv-test-env. - * TestStructure/riscv-test-suite: Directory moved to - riscv-test-suite. - * riscv-test-suite: Directory moved from - TestStructure/riscv-test-suite. - * thought-experiments: Directory deleted. - - 2018-05-21 Jeremy Bennett - - Initial commit to populate the repository. - - * ChangeLog: Created. - * README.md: Created. diff --git a/tests/wally-riscv-arch-test/CONTRIBUTION.md b/tests/wally-riscv-arch-test/CONTRIBUTION.md deleted file mode 100644 index 01f4424c7..000000000 --- a/tests/wally-riscv-arch-test/CONTRIBUTION.md +++ /dev/null @@ -1,66 +0,0 @@ -# Contributing to RISC-V Architecture Tests - -Your inputs are welcome and greatly appreciated! We want to make contributing to this project as easy and transparent as possible, whether it's: - -- Reporting a bug -- Discussing the current state of the code -- Submitting a fix -- Proposing new features -- Becoming a maintainer - -## We develop with Github -We use github to host code, to track issues and feature requests, as well as accept pull requests. - -## We use a simple git flow where all code changes happen through Pull Requests - -Pull requests are the best way to propose changes to the codebase. We actively welcome your pull requests: - -1. Fork the repo and create your branch from `master`. -2. If you have added new tests, please ensure they adhere to the latest TestFormatSpec and that you have run them on the RVI approved reference - models (if support in those models is available). -3. If you have updated any test-macros make sure to update the documentation as well. -4. If you have updated the docs, ensure that they render correctly in the respective format. -5. Make sure to create an entry in the CHANGELOG.md. Please refer to the section on versioning below - to choose an appropriate version number. -6. Ensure the existing tests are not broken and still pass on the the RVI approved reference models. -7. Please include a comment with the SPDX license identifier in all source files, for example: - ``` - // SPDX-License-Identifier: BSD-3-Clause - ``` -8. Issue that pull request! - -## Versioning - -When issuing pull requests, an entry in the CHANGELOG.md is mandatory. The arch-test-repo adheres to -the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must -be followed while assigning a new version number : - -- Patch-updates: all doc updates (like typos, more clarification,etc) and updates to unratified extensions. -- Minor-updates: Updates to ratified extensions OR migration of extensions to ratified OR changes in docs regarding policies or spec. -- Major-updates: Changes to the framework flow (backward compatible or incompatible). - -Note: You can have either a patch or minor or major update. -Note: In case of a conflict, the maintainers will decide the final version to be assigned. - -## Any contributions you make will be under the permissive open-source License -In short, when you submit code changes, your submissions are understood to be under a permissive open source license like BSD-3, Apache-2.0 and CC, etc that covers the project. Feel free to contact the maintainers if that's a concern. - -## Report bugs using Github's [issues](https://github.com/riscv/riscv-arch-test/issues) -We use GitHub issues to track public bugs. Report a bug by [opening a new issue](https://github.com/riscv/riscv-arch-test/issues/new); it's that easy! - -## Write bug reports with detail, background, and sample code - -**Great Bug Reports** tend to have: - -- A quick summary and/or background -- Steps to reproduce - - Be specific! - - Give sample code if you can. -- What you expected would happen -- What actually happens -- Notes (possibly including why you think this might be happening, or stuff you tried that didn't work) - -## License -By contributing, you agree that your contributions will be licensed under its permissive open source -licenses. - diff --git a/tests/wally-riscv-arch-test/Makefile b/tests/wally-riscv-arch-test/Makefile index eef7857b8..168f03c3c 100644 --- a/tests/wally-riscv-arch-test/Makefile +++ b/tests/wally-riscv-arch-test/Makefile @@ -87,7 +87,7 @@ simulate: run -C $(SUITEDIR) verify: simulate - riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values + riscv-test-env/verify.sh postverify: ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),) diff --git a/tests/wally-riscv-arch-test/README.md b/tests/wally-riscv-arch-test/README.md deleted file mode 100644 index 9fd5a8b8b..000000000 --- a/tests/wally-riscv-arch-test/README.md +++ /dev/null @@ -1,74 +0,0 @@ -# RISC-V Architecture Test SIG - - -This is a repository for the work of the RISC-V Foundation Architecture Test SIG. The repository owners are: - -- Neel Gala (InCore Semiconductors) -- Marc Karasek (Inspire Semiconductors) - -Details of the RISC-V Foundation, the work of its task groups, and how to become a member can be found at [riscv.org](https://riscv.org/). - -For more details and documentation on the current testing framework see: [doc/README.adoc](doc/README.adoc) - -For more details on the test format spec see: [spec/TestFormatSpec.adoc](spec/TestFormatSpec.adoc) - -For contributions and reporting issues please refer to [CONTRIBUTION.md](CONTRIBUTION.md) - -## Test Disclaimers - -The following are the exhaustive list of disclaimers that can be used as waivers by target owners -when reporting the status of pass/fail on the execution of the architectural suite on their respective targets. - -1. The references uploaded for the following misaligned load/store tests will match targets which do - not support misaligned load/stores in hardware. Targets with hardware misaligned support for - load/stores will fail these tests. - - 1. rv32i_m/privilege/src/misalign-[lb[u],lh[u],lw,sh,sb,sw]-01.S - 2. rv64i_m/privilege/src/misalign-[lb[u],lh[u],lw[u],ld,sb,sh,sw,sd]-01.S - -2. The references uploaded for the following misaligned instruction tests will match targets which - have compressed extension support enabled by default. Targets without the compressed extension - support will fail the following tests: - 1. rv[32/64]i_m/privilege/src/misalign-b[ge[u],lt[u],eq,ne]-01.S - 2. rv[32/64]i_m/privilege/src/misalign[1,2]-jalr-01.S - -3. The machine mode trap handler used in the privilege tests assumes one of the following conditions. - Targets not satisfying any of the following conditions are bound to fail the entire - rv32i_m/privilege and rv64i_m/privilege tests: - 1. The target must have implemented mtvec which is completely writable by the test in machine mode. - 2. The target has initialized mtvec, before entering the test (via RVMODEL_BOOT), to point to a memory location which has both read and write permissions. - -## Contribution process - -Please refer to to [CONTRIBUTION.md](CONTRIBUTION.md) for guidelines on contributions. - -## Licensing - -In general: -- code is licensed under one of the following: - - the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`); - - the Apache License (SPDX license identifier `Apache-2.0`); while -- documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`). - -The files [`COPYING.BSD`](./COPYING.BSD), [`COPYING.APACHE`](./COPYING.APACHE) and [`COPYING.CC`](./COPYING.CC) in the top level directory contain the complete text of these licenses. - -## Engineering practice - -- Documentation uses the structured text format _AsciiDoc_. See [`doc/README.adoc`](doc/README.adoc) for more details. - -- Some directories use `ChangeLog` files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message. - -- Please include a comment with the SPDX license identifier in all source files, for example: -``` -// SPDX-License-Identifier: BSD-3-Clause -``` - -## Quick Links: - -- RISCOF \[[DOCS](https://riscof.readthedocs.io/en/latest/)\] \[[REPO](https://github.com/riscv-software-src/riscof)\]: This is the next version of the architectural test framework currently under development -- RISCV-ISAC \[[DOCS](https://riscv-isac.readthedocs.io/en/latest/index.html)\] \[[REPO](https://github.com/riscv-software-src/riscv-isac)\] : This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests. -- RISCV-CTG: \[[DOCS](https://riscv-ctg.readthedocs.io/en/latest/index.html)\]\[[REPO](https://github.com/riscv-software-src/riscv-ctg)\]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository. -- [Videos](https://youtu.be/VIW1or1Oubo): This Global Forum 2020 video provides an introduction to the above mentioned tools -- [riscvOVPsim](https://github.com/riscv-ovpsim/imperas-riscv-tests): Imperas freeware RISC-V reference simulator for compliance testing -- [riscvOVPsimPlus](https://www.ovpworld.org/riscvOVPsimPlus/): Imperas enhanced freeware RISC-V reference simulator for test development and verification - diff --git a/tests/wally-riscv-arch-test/doc/.gitignore b/tests/wally-riscv-arch-test/doc/.gitignore deleted file mode 100644 index 70954a171..000000000 --- a/tests/wally-riscv-arch-test/doc/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -# Ignore editor backups -*~ -# Generated files -custom.dict -README.pdf -README.html \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/doc/ChangeLog b/tests/wally-riscv-arch-test/doc/ChangeLog deleted file mode 100644 index 6b408419b..000000000 --- a/tests/wally-riscv-arch-test/doc/ChangeLog +++ /dev/null @@ -1,147 +0,0 @@ -2019-02-21 Deborah Soung - * README.adoc: Documentation for rocket chip as target. - -2019-02-05 Deborah Soung - * README.adoc: Update documentation for rocket chip as target (fixed rv32si/ma_fetch.S). - * README.adoc: Update documentation for rocket chip as target (fixed breakpoint.S). - -2019-01-29 Deborah Soung - * README.adoc: Documentation for rocket chip as target. - -2018-11-21 Olof Kindgren - - * README.adoc (Repository structure) Added documentation for the $TARGETDIR environmental variable - -2018-11-21 Neel Gala - * README.adoc: Added new signature format spec. - -2018-06-18 Jeremy Bennett - - * README.adoc (Future work): Reflect changes made to support - Codasip simulator. - (Repository structure): Diagrammatic representation of the file - structure deleted. - -2018-06-12 Jeremy Bennett - - * .gitignore: Add custom.dict. - -2018-06-12 Jeremy Bennett - - Document issue 1.8 Draft. - - * README.adoc (Introduction): Add Future work section and bump - version. - * custom.wordlist: Add words needed for Future work section. - -2018-06-12 Jeremy Bennett - - * README.adoc: Remove special apostrophe from "licensor's". - * custom.wordlist: Updated with more words to be ignored. - -2018-06-12 Jeremy Bennett - - * README-old.md: Deleted. - * README.adoc: Include details of how to contribute and installing - the tools from the old README and reference the licence as an - appendix. - -2018-06-11 Jeremy Bennett - - This makes the document appear directly as the README of the doc - directory, so there is now no longer a need to publish to GitHub - pages. - - * .gitignore: Change name of files ignored. - * Makefile: Remove publish target. - * README.adoc: Symbolic link removed and replaced by design.adoc, - to which the CC license text has been added. - * design.adoc: Renamed as README.adoc. - * publish.sh: Deleted. - -2018-06-11 Jeremy Bennett - - * README.md: Previous version moved to README-old.md for the time - being. - * README.adoc: Created as symbolic link to design.adoc. - -2018-06-10 Jeremy Bennett - - * README.md: Note about make publish. - * design.adoc (Overall structure): Make list or instruction sets - and extensions compact representation. - -2018-06-10 Jeremy Bennett - - * publish.sh: Only publish from clean and committed master branch - to avoid difficult use of git stash. - -2018-06-10 Jeremy Bennett - - * publish.sh: Don't rely on doc directory being available on - gh-pages branch. - -2018-06-10 Jeremy Bennett - - * publish.sh: Make executable and correctly set top level - repository directory. - -2018-06-10 Jeremy Bennett - - Add a mechanism to make the latest documentation available via - GitHub pages. This means that design.html is no longer part of - the master branch, but is published by copying to index.html on - the gh-pages branch. - - * .gitignore: Ignore design.html. - * Makefile: Add publish target and delete design.html when cleaning. - * README.md: Link to GitHub pages for latest documentation. - * design.adoc: Deal with AsciiDoc apparent bug with consecutive - comment blogs. - * design.html: Deleted. - * publish.sh: Created. - -2018-06-10 Jeremy Bennett - - * README.md: Fix link to generated documentation. - * design.html: Regenerated. - -2018-06-09 Jeremy Bennett - - * Makefile: Add sanity check for version number and spell target. - * design.adoc: Fix trivial typo. - * design.html: Regenerated. - -2018-06-09 Jeremy Bennett - - * .gitignore: Don't ignore .html or .xml - * README.md: Note location of old documentation, give link to HTML - and explain how to contribute. - * custom.wordlist: Created. - * design.adoc: Cleaned up from top to bottom and spell checked. - * design.html: Generated. - -2018-06-08 Jeremy Bennett - - * Makefile: Clean up and add license header. - * README.md: Created. - * design.adoc: Add licensing and SPDX license identifier. - * legacy.adoc: Deleted. - -2018-06-04 Jeremy Bennett - - This is the first version of the document taken from Simon - Davidmann's MS Word document. The main document is design.adoc, - legacy material, currently just appendices C and D has been moved - to legacy.adoc. - - design.adoc is correct AsciiDoc. legacy.adoc is just a raw dump, - which needs cleaning up. - - The next step will be restructuring design.adoc as agreed. - - * .gitignore: Created. - * ChangeLog: Created. - * Makefile: Created. - * design.adoc: Created. - * legacy.adoc: Created. diff --git a/tests/wally-riscv-arch-test/doc/MIGRATION.adoc b/tests/wally-riscv-arch-test/doc/MIGRATION.adoc deleted file mode 100644 index d9801c661..000000000 --- a/tests/wally-riscv-arch-test/doc/MIGRATION.adoc +++ /dev/null @@ -1,88 +0,0 @@ -= Migration guide -:toc: -:icons: font -:numbered: -:source-highlighter: rouge - -This document serves as a guide to users of the architectural suite to migrate their targets from an -older version to a newer version with minimal changes. This guide thus provides a patch scheme to get -the previous versions of the targets up and running with the new versions of the framework. - -However, users are strongly encouraged to completely migrate to the newer versions, as and when -available, and avoid using these patches. - -== Migration from v0.1 to v0.2 - -This section will describe the changes required to transition your targets ported on v0.1 to v0.2 -framework. For examples please see: `riscv-target/riscvOVPsim_0p1` and `riscv-target/spike_0p1`. - -=== Change header filename - -In version v0.1 the target specific assembly macros were split across two files: `compliance_test.h` -and `compliance_io.h`. In version v0.2 these macros are to merged into a single file named -`model_test.h`. The following commands can the achieve the above: - ----- -mv compliance_test.h model_test.h -cat compliance_io.h >> model_test.h -rm compliance_io.h ----- - -=== Change device directory structure - -In version v0.1 a target would have one or multiple of the directories defined to indicate supported -extensions: `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei`. In version v0.2 the -directories of the extensions have changed in order to provide more consistency and less ambiguity. - -For version v0.2, the `device` directory first needs to have either a `rv32i_m` directory to indicate -that the target is a 32-bit machine. The extension directories, as supported by the target, are -now to be created in each of these directories using the following mapping scheme: - -. device/rv32i -> device/rv32i_m/I -. device/rv32im -> device/rv32i_m/M -. device/rv32imc -> device/rv32i_m/C -. device/rv32Zicsr -> device/rv32i_m/privilege -. device/rv32Zifencei -> device/rv32i_m/Zifencei - -The contents of the extension directories need not change, unless there are dependencies on the path -of the directory itself. The following commands will achieve the above: - ----- -cd device -mkdir rv32i_m -mv rv32i rv32i_m/I -mv rv32im rv32i_m/M -mv rv32imc rv32i_m/C -mv rv32Zicsr rv32i_m/privilege -mv rv32Zifencei rv32i_m/Zifencei ----- - -=== Changes in target macro names. - -Since some of the macros from the old framework have been re-purposed in the new v0.2 framework, -there will be name conflicts rendering the old ones useless. In order to retain the old macros, they -have been renamed with a post-fix `_OLD`. The macros that have been renamed are given below: - -. `RVTEST_CODE_BEGIN` -> `RVTEST_CODE_BEGIN_OLD` -. `RVTEST_CODE_END` -> `RVTEST_CODE_END_OLD` -. `RVTEST_DATA_BEGIN` -> `RVTEST_DATA_BEGIN_OLD` -. `RVTEST_DATA_END` -> `RVTEST_DATA_END_OLD` - -The user is thus required to make the above changes in the new `model_test.h` that was created -as part of this migration. The following commands will help achieve the above: - ----- -sed -i 's/RVTEST_CODE_BEGIN/RVTEST_CODE_BEGIN_OLD/g' model_test.h -sed -i 's/RVTEST_CODE_END/RVTEST_CODE_END_OLD/g' model_test.h -sed -i 's/RVTEST_DATA_BEGIN/RVTEST_DATA_BEGIN_OLD/g' model_test.h -sed -i 's/RVTEST_DATA_END/RVTEST_DATA_END_OLD/g' model_test.h - ----- - -note:: the RVTEST_DATA_END in v0.1 enforced a 16-byte alignment before the signature end. This -constraint has been removed. - -=== Changes in device Makefile.include files - -No changes required. - diff --git a/tests/wally-riscv-arch-test/doc/Makefile b/tests/wally-riscv-arch-test/doc/Makefile deleted file mode 100644 index 697d89cdc..000000000 --- a/tests/wally-riscv-arch-test/doc/Makefile +++ /dev/null @@ -1,82 +0,0 @@ -# Makefile for RISC-V Architectural Test SIG documentation - -# This file is part of the RISC-V Foundation Architectural Test SIG -# tool set and documentation. - -# Copyright (C) 2017 CodaSip Limited -# Copyright (C) 2018 Embecosm Limited . -# Copyright (C) 2018 Imperas Limited - -# All rights reserved. - -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: - -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of mosquitto nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. - -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. - -# SPDX-License-Identifier: BSD-3-Clause - -ROOT = README -SRC = $(ROOT).adoc -SRC_STRIPPED = $(ROOT)-stripped.adoc - -.PHONY: all -all: pdf html - -.PHONY: pdf -pdf: $(ROOT).pdf - -$(ROOT).pdf: sanity-check $(SRC) - asciidoctor-pdf -d article $(SRC) - -.PHONY: html -html: $(ROOT).html - -$(ROOT).html: sanity-check $(SRC) - asciidoctor -d article -b html $(SRC) - -# It is all too easy for the document history and title page to have diverging -# version numbers. This target checks first. - -.PHONY: sanity-check -sanity-check: - @s=$$(sed -n < $(SRC) -e '3s/Issue //p') ; \ - t=$$(sed -n < $(SRC) -e "/== Document history/,/^$$/p" | \ - grep -c "$${s}") ; \ - if [ $${t} -ne 1 ] ; \ - then \ - echo "Version number of title and document history do not match" ; \ - exit 1 ; \ - fi - -custom.dict: custom.wordlist - aspell --lang=en create master ./$@ < $< - -.PHONY: spell -spell: custom.dict $(SRC) - sed < $(SRC) > $(SRC_STRIPPED) -e 's/`[^`]\+`//gp' -e '/^----$$/,/^----$$/d' - aspell --master=en_US --mode=none --add-extra-dicts=./custom.dict \ - -c $(SRC_STRIPPED) - $(RM) $(SRC_STRIPPED) - -clean: - rm -f $(ROOT)-stripped.adoc $(ROOT).pdf $(ROOT).html custom.dict diff --git a/tests/wally-riscv-arch-test/doc/README.adoc b/tests/wally-riscv-arch-test/doc/README.adoc deleted file mode 100644 index fa7129b39..000000000 --- a/tests/wally-riscv-arch-test/doc/README.adoc +++ /dev/null @@ -1,460 +0,0 @@ -= RISC-V Architectural Testing Framework = -RISC-V Foundation Architecture Test SIG -Issue 1.16 Draft -:toc: -:icons: font -:numbered: -:source-highlighter: rouge - -//// -SPDX-License-Identifier: CC-BY-4.0 - -Document conventions: -- one line per paragraph (don't fill lines - this makes changes clearer) -- Wikipedia heading conventions (First word only capitalized) -- US spelling throughout. -- Run "make spell" before committing changes. -- Build the HTML and commit it with any changed source. -- Do not commit the PDF! -//// - -== Introduction -=== About - -This document describes the RISC-V Architectural Testing framework which is used to test if a RISC-V device's has understood and implemented the specifications correctly - -* It explains the framework around the tests, the running of individual tests, and the suites of tests. - -* It explains how to set up targets to run the tests. - -This document is made freely available under a <>. - -=== Intent of the architectural test suite - -The RISC-V Architectural Tests are an evolving set of tests that are created to help ensure that software written for a given RISC-V Profile/Specification will run on all implementations that comply with that profile. - -These tests also help ensure that the implementer has both understood and implemented the specification correctly. - -The RISC-V Architectural Test suite is a minimal filter. Passing the tests and having the results approved by RISC-V International is a prerequisite to licensing the RISC-V trademarks in connection with the design. Passing the RISC-V Architectural Tests does not mean that the design complies with the RISC-V Architecture. These are only a basic set of tests checking important aspects of the specification without focusing on details. - -The RISC-V Architectural Tests are not a substitute for rigorous design verification. - -The result that the architecture tests provide to the user is an assurance that the specification has been interpreted correctly and the implementation under test (DUT) can be declared as RISC-V Architecture Test compliant. - -=== Intended audience - -This document is intended for design and verification engineers who wish to check if their RISC-V implementation (simulation models, HDL models, etc.) is compliant to the RISC-V specification. - -For those who wish to develop new architectural tests and/or to write or adapt their own test framework are suggested to read the link:../spec/TestFormatSpec.adoc[`Test Format Spec`]. - - -=== Contribute - -You are encouraged to contribute to this repository (including changes to this document) by submitting pull requests and by commenting on pull requests submitted by other people as described in the link:../README.md[`README.md`] file in the top level directory. - -While submitting a pull request note that some directories use `ChangeLog` files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message. - -Make sure to also include a comment with the SPDX license identifier in all source files, for example: -``` -// SPDX-License-Identifier: BSD-3-Clause -``` - -NOTE: Don't forget to add your own name to the list of contributors in the document. - -== Licensing - -In general: - -* code is licensed under the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`); -* documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`). - -The files link:../COPYING.BSD[`COPYING.BSD`] and link:../COPYING.CC[`COPYING.CC`] in the top level directory contain the complete text of these licenses. - -NOTE: The riscv-ovpsim simulator is licensed under an Imperas license. There is no dependency on this and it is included as a convenience to users. - - -==== AsciiDoc - -This is a structured text format used by this document. Simple usage should be fairly self evident. - -* Comprehensive information on the format is on the http://www.methods.co.nz/asciidoc/[AsciiDoc website]. - -* Comprehensive information on the tooling on the https://asciidoctor.org/[AsciiDoctor website]. - -* You may find this https://asciidoctor.org/docs/asciidoc-syntax-quick-reference/[cheat sheet] helpful. - -==== Installing tools - -To generate the documentation as HTML you need _asciidoctor_ and to generate as -PDF you need _asciidoctor-pdf_. - -* These are the https://asciidoctor.org/docs/install-toolchain/[installation instructions for asciidoctor]. - -* These are the https://asciidoctor.org/docs/asciidoctor-pdf/#install-the-published-gem[installation instructions for asciidoctor-pdf]. - -To spell check you need _aspell_ installed. - -==== Building the documentation - -To build HTML: -[source,make] ----- -make html ----- - -To build PDF: -[source,make] ----- -make pdf ----- - -To build both: -[source,make] ----- -make ----- - -To check the spelling (excludes any listing or code phrases): -[source,make] ----- -make spell ----- - -Any custom words for spell checking should be added to link:./custom.wordlist[`custom.wordlist`]. - -=== Contributors - -This document has been created by the following people (in alphabetical order of surname). - -* Jeremy Bennett -* Mary Bennett -* Simon Davidmann -* Neel Gala -* Radek Hajek -* Lee Moore -* Milan Nostersky -* Marcela Zachariasova - -=== Document history -[cols="<1,<2,<3,<4",options="header,pagewidth",] -|================================================================================ -| _Revision_ | _Date_ | _Author_ | _Modification_ -| 1.16 Draft | 23 September 2020 | Neel Gala| Changed Compliance to Architecture/Architectural. Refined the steps to port a new target. Removed simulator and target specific docs. Added vocabulary from the Test Format Specification -| 1.15 Draft | 14 March 2019 | -Prashanth Mundkur | - -Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets. -| 1.14 Draft | 21 February 2019 | -Deborah Soung | - -Documented how to use SiFive's RISC-V ISA Formal Specification model as a target. -| 1.13 Draft | 29 January 2019 | -Deborah Soung | - -Added documentation on how to use Rocket Chip generated cores as targets. -| 1.12 Draft | 22 November 2018 | -Simon Davidmann | - -Updated notes on Test Suites. -| 1.11 Draft | 21 November 2018 | -Neel Gala | - -Added new signature format specs . -| 1.10 Draft | 20 June 2018 | - -Simon Davidmann, Lee Moore | - -Cleaned up description of updated framework and inclusion of riscvOVPsim. - -| 1.9 Draft | 12 June 2018 | - -Jeremy Bennett | - -Update Future work section to take account of Codasip changes. Remove diagrammatic directory structure. - -| 1.8 Draft | 12 June 2018 | - -Jeremy Bennett | - -Add Future work section. - -| 1.7 Draft | 12 June 2018 | - -Jeremy Bennett | - -Add CC license as an appendix. - -| 1.6 Draft | 10 June 2018 | - -Jeremy Bennett | - -Tidy up areas that are flawed in HTML version. - -| 1.5 Draft | 8 June 2018 | - -Jeremy Bennett | - -General tidy up. - -| 1.4 Draft | 8 June 2018 | - -Jeremy Bennett | - -Added license preamble. - -| 1.3 Draft | 5 June 2018 | - -Simon Davidmann | - -Updated to reflect directory structure and trace macros. - -| 1.2 Draft | 3 June 2018 | - -Jeremy Bennett | - -Converted to AsciiDoc, cleaned up and restructured. - -| 1.1 Draft | 1 June 2018 | - -Simon Davidmann -Lee Moore | - -Revised format and expand to describe framework, usage of many tests groups, -and different Targets - -|1.0 | 24 December 2017 | - -Radek Hajek -Milan Nostersky -Marcela Zachariasova | - -First version of the document. - -|================================================================================ - -== Repository structure - -The top level directory contains : - - - a `README.md` file providing high-level details about the RISC-V Architecture Testing Framework. - - top level `Makefile` for running the tests on a RISC-V implementation. - - `ChangeLog` for logging changes with respect to code. - - complete license files for the Creative Commons and BSD licenses used by the task group. - -There are then five top level directories. - -`doc`:: All the documentation for the project, written using _AsciiDoc_. - -`coverage`:: This directory contains a sub-directory structure similar to the `riscv-test-suite` directory. The coverage reports of each test-suite are available in the corresponding directories. The reports are available in the html and yaml formats. The directory also contains multiple coverpoint YAMLs which capture all the coverpoints of interest which are covered by all the tests in the `riscv-test-suite` directory. - -`riscv-target`:: Contains a further subdirectory for each target, within which are placed the `model_test.h` header for that target and a `device` directory for all the devices of that target. If the `$TARGETDIR` environment variable is set to another directory, the scripts will search this directory for targets instead. - -`riscv-test-env`:: This contains the `verify.sh` script which checks if the signatures generated the riscv-target device match the statically hosted reference signatures at the end of simulation. The directory also contains symbolic-links to the `arch_test.h` and `encoding.h` files present in the `riscv-test-suite/env` directory. - -`riscv-test-suite`:: This contains a further `env` subdirectory which contains the `arch_test.h` and the `encoding.h` file which includes common assembly macros and routines which is used across the tests in the suite. Further directories are present which contain the actual architectural tests. The names and structure of these directories is based on the link:../test-pool structure guideline highlighted above. - -`riscv-ovpsim`:: This contains a README pointing to the Imperas OVP riscvOVPsim simulator for use in architectural testing. - -== Vocabulary -=== The architectural test - -At the heart of the testing infrastructure is the detailed <> available as `.S` assembly files. The specification and format of the tests is defined in the link:./TestFormatSpec.adoc[`Test Format Specification`]. - -=== The architectural test pool - -The <> are grouped into different functional test suites targeting the different subsets of the RISC-V specification. For more details on the test-pool structure, hierarchy and conventions please refer to the link:./TestFormatSpec.adoc[`Test Format Specification`]. - -For information on the currently supported different test suites, look here: link:../riscv-test-suite/README.md[../riscv-test-suite/README.md] - -=== The test signature - -Each test in the <> generates a <>, which represents the data written into specific memory locations during the execution of the test. The signature typically will record values (or sanitised values) of the operations carried out in the test. More details on the format and nature of the signatures is available in the link:./TestFormatSpec.adoc[`Test Format Specification`] - -=== The reference signature - -In order to claim that a device/implementation has passed the RISC-V Architecture Tests, the <> obtained from the execution of the tests on the implementation need to be compared against a set of _golden_ <>. These reference signatures are currently generated by the link:https://github.com/rems-project/sail-riscv[`RISC-V SAIL`] formal model and statically hosted in the repository for each test. - -=== The test target -The <> can be either a RISC-V Instruction Set Simulator (ISS), a RISC-V emulator, a RISC-V RTL model running on an HDL simulator, a RISC-V FPGA implementation or a physical chip. Each of the target types offers specific features and represents specific interface challenges. It is a role of the <> to handle different targets while using the same <> as a test source. - -=== The target shell -The <> is the software and hardware environment around the <> that enables it to communicate with the framework, including assembling and linking tests, loading tests into memory, executing tests, and extracting the signature. The input to the <> is a .S <> file, and the output is a <>. - - -== Porting a new target - - -In this section, a short tutorial on how to add a user target to the RISC-V Architectural Test Framework is provided. - -The following steps demonstrate an example in which a target was replaced by the RISCV-ISA-SIM -(a.k.a Spike). In a similar way, any RISC-V ISA simulator or any RTL simulation model of the -RISC-V processor can be ported as a potential target for testing. - -=== Setup environment variables - -NOTE: `ROOTDIR` will always point to the riscv-arch-test repo. - -1. Clone the repository: - - --- - git clone https://github.com/riscv/riscv-arch-test.git - cd riscv-arch-test - - --- - -2. Open the `Makefile.include` available in the root folder of the repository and edit the following -variables based on your target: - - a. `TARGETDIR` : set `TARGETDIR` to point to the directory which contains a sub-folder in the same name - as the target. For example, the arch-test repo includes the targets: sail-riscv-c and spike - under the `riscv-target` folder, in which case we set the `TARGETDIR` to riscv-target as shown - below. One can set this completely arbitrary paths as suitable by the user. - - - --- - export TARGETDIR ?= $(ROOTDIR)/riscv-target - - --- - - b. `XLEN`: set XLEN to max supported XLEN. Allowed values are 32 and 64. - - --- - export XLEN ?= 64 - - --- - -c. `RISCV_TARGET`: set this variable to the name of the target. A folder of the same name must exist in -the `TARGETDIR` directory - - --- - export RISCV_TARGET ?= spike - - --- - -d. `RISCV_DEVICE`: set the `RISCV_DEVICE` environment to the extension you want to compile, simulate and verify. Leave -this blank if you want to iterate through all the supported extensions of the target. Allowed values -are the individual names of the extensions supported by your target like: I, M, C or Zifencei, etc. Multiple extensions are not be provided. - - --- - export RISCV_DEVICE ?= - - --- - -e. `RISCV_TARGET_FLAGS`: set this to a string which needs to be passed to your target's Makefile.include files - - --- - export RISCV_TARGET_FLAGS ?= - - --- - -f. `RISCV_ASSERT`: set this if you want to enable assertions on the test-suites. **Currently no tests use assertions.** - - --- - export RISCV_ASSERT ?= 0 - - --- - -g. `JOBS`: set the number of parallel jobs (along with any other arguments) you would like to -execute. Note that the target needs to be coded in such a way to support parallel execution. Some -targets use common intermediate files, rather than unique files, which makes them unsuitable for -parallel execution, these targets will need to be re-coded. - - --- - JOBS= -j1 - - --- - -3. Now inside your `TARGETDIR/RISCV_TARGET` directory you will need to create the following files: - -a. `model_test.h`: A header file containing the definition of the various target specific -assembly macros that are required to compile and simulate the tests. The list and definition of the -required target specific macros is available in the link:../spec/TestFormatSpec.adoc[Test Format -Specification] - -b. `link.ld`: A linker script to compile the tests for your target. - -c. Any other files required by the target (configuration scripts, logs, etc.) can also be placed in -this directory. - -4. Inside the `TARGETDIR/RISCV_TARGET` directory create a new folder named: `device`. If your device -is a 32-bit target then create a directory `device/rv32i_m`. If your device is a 64-bit target then -create a directory `device/rv64i_m`. If your target is configurable on the `XLEN` parameter then -both the folders need to be created. - -5. Within the `rv32i_m`/`rv64i_m` directories sub-folders in the name of the extensions supported -by the target need to be created. For eg. A target supporting the ISA RV32IMC_Zifence will have the -following directory structure: - - --- - - rv32i_m/I - - rv32i_m/M - - rv32i_m/C - - rv32i_m/privilege - - rv32i_m/Zifencei - - --- - -6. Each of the above extension directories will now need to include a file: `Makefile.include` which -defines the following Makefile variables: - -a. `RUN_TARGET`:: This variable needs to include commands and steps to execute an ELF on target device. Note here that this variable should include all the necessary steps and arguments to run that specific test-suite. For example, in case of spike for the `rv32i_m/C` test-suite the corresponding `Makefile.include` has the `--isa=rv32ic` argument as opposed to just `--isa=rv32i` for the base `rv32i_m/I` test-suite. This variable should also include other steps to extract and sanitize the signature file as well for each test. The only argument available to this variable is the compiled `elf` file. - -b. `COMPILE_TARGET`:: This variable should include the commands and steps required to compile an assembly test for the target for each extension mentioned above. Note, currently only the GCC compiler is supported. This compiler takes `march` and `mabi` arguments from the corresponding architectural suite framework. `COMPILE_TARGET` will more or less be the same across test-suites. The only argument available to `COMPILE_TARGET` is the assembly file of one architectural test. - -The following figure depicts the final directory structure of a target device that should get created at the end of the above steps: - -[#img-testStruct] -.File Structure of the Target directory -image::./file-struct.jpg[TargetStruct] - - -=== Generating Signature - -As previously mentioned the execution of each test on the target must generate a signature file. The name of the signature file should be ``. The signature file should follow the guidelines mentioned in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`]. - -In case of spike, we have ensured that the signature region is bounded by the labels: `begin_signature` and `end_signature`. This is enforced in the `RVMODEL_DATA_BEGIN` and `RVMODEL_DATA_END` macros defined in the `riscv-target/spike/model_test.h` file. Additionally, if you look closely at the `RUN_TARGET` variable defined in the `Makefile.include` files of the spike target, it includes a few bash commands to sanitize the signature produced from spike. This is done to conform the final signature file to the specification defined in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`]. - -=== Compile, simulate and verify the tests - -Once you have ported your target to the riscv-arch-test framework by following the above steps, you -are now ready to compile, simulate and verify the tests on your target - -If you would like to compile, simulate and verify all the extension tests applicable to your target -simply run `make` from the `ROOTDIR`. - -NOTE: For the above to work the `RISCV_DEVICE` in `ROOTDIR/Makefile.include` must be left empty. - -If you would like to only compile the tests for a particular extension you can use the following -command. - - make RISCV_DEVICE=M compile - make RISCV_DEVICE=C compile - -The arguments to the `RISCV_DEVICE` variable must be the extensions supported by the target. -NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary -for all targets. - -To simulate the compiled tests on your target: - - make RISCV_DEVICE=M simulate - make RISCV_DEVICE=Zifencei simulate - -NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary -for all targets. - -To verify if the generated signatures match the corresponding reference signatures. - - make RISCV_DEVICE=M verify - -NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary -for all targets. - -All the above steps create and modify files in the `work` directory created in `ROOTDIR` folder. To -clean the `workdir` simple run : - - make clean - -By default the working directory is set to `ROOTDIR/work`. This can be overwritten by assigning a -new working directory path via the command line. Note, the path must be absolute and not relative : - - make WORK=/home/me/my_path/mywork clean compile simulate diff --git a/tests/wally-riscv-arch-test/doc/custom.wordlist b/tests/wally-riscv-arch-test/doc/custom.wordlist deleted file mode 100644 index 2efdc5925..000000000 --- a/tests/wally-riscv-arch-test/doc/custom.wordlist +++ /dev/null @@ -1,73 +0,0 @@ -AsciiDoc -asciidoc -AsciiDoctor -asciidoctor -aspell -autotools -CGEN -cmake -Codasip -creativecommons -CY -Davidmann -discoverable -DUT -EF -enforceability -FPGA -GDB -Generis -github -Hajek -HDL -http -https -IC -ies -immunities -Imperas -io -IM -ISA -legalcode -licensor -licensors -licensor's -LLVM -makefile -makefiles -Marcela -md -merchantability -Nostersky -nz -pagewidth -parameterization -pdf -publicdomain -Radek -README -riscv -riscvOVPsim -RTL -rv -RVTEST -SiFive -spdx -src -subdirectory -sublicensable -synched -tbd -testbench -toc -toolchain -TVM -URI -Verilator -Verilog -waivable -WIPO -wordlist -www -Zachariasova diff --git a/tests/wally-riscv-arch-test/doc/file-struct.jpg b/tests/wally-riscv-arch-test/doc/file-struct.jpg deleted file mode 100644 index 7ddee1e84..000000000 Binary files a/tests/wally-riscv-arch-test/doc/file-struct.jpg and /dev/null differ diff --git a/tests/wally-riscv-arch-test/riscv-ovpsim/README.md b/tests/wally-riscv-arch-test/riscv-ovpsim/README.md deleted file mode 100644 index 1ee680815..000000000 --- a/tests/wally-riscv-arch-test/riscv-ovpsim/README.md +++ /dev/null @@ -1,43 +0,0 @@ -riscvOVPsim -=== -A Complete, Fully Functional, Configurable RISC-V Simulator -=== - -riscvOVPsim has moved to its own GitHub repository. - -It can now be found here: [github.com/riscv-ovpsim](https://github.com/riscv-ovpsim/imperas-riscv-tests) - -For the enhanced version, please download from [ovpworld.org/riscv-ovpsim-plus](https://www.ovpworld.org/riscvOVPsimPlus). - -The simulators implement the full and complete functionality of the RISC-V Foundation's public User and Privilege specifications. - -The simulator is command line configurable to enable/disable all current optional and processor specific options. - -The simulator is developed, licensed and maintained by [Imperas Software](http://www.imperas.com/riscv) and it is fully compliant to the OVP open standard APIs. - -As a member of the RISC-V Foundation community of software and hardware innovators collaboratively driving RISC-V adoption, Imperas has developed the riscvOVPsim simulator to assist RISC-V adopters to become compliant to the RISC-V specifications. The latest RISC-V compliance test suite and framework can be downloaded from https://www.github.com/riscv/riscv-compliance. - -riscvOVPsim includes an industrial quality model and simulator of RISC-V processors for use for compliance and test development. It has been developed for personal, academic, or commercial use, and the model is provided as open source under the Apache 2.0 license. The simulator is provided under the Open Virtual Platforms (OVP) Fixed Platform Kits license that enables download and usage. riscvOVPsim and Imperas RISC-V support is actively maintained and enhanced. To ensure you make use of the current version of riscvOVPsim versions do expire. Please download the latest version. - -![](riscvOVPsim.jpg) - -Extending riscvOVPsim and building your own models and platforms ---- -riscvOVPsim is a fixed function simulation of one configurable processor model in a fixed platform. -Full extendable platform simulations of reference designs booting FreeRTOS, Linux, SMP Linux etc. -are available as open source and are available from [www.IMPERAS.com](http://www.imperas.com), -[www.OVPworld.org](http://www.OVPworld.org). - -About Open Virtual Platforms (OVP) and Imperas Software ---- -**Open Virtual Platforms** was created in 2008 to provide an open standard set of APIs and methodology to develop virtual platforms and simulation technology. -[www.OVPworld.org](http://www.OVPworld.org/riscv). - -**Imperas Software Ltd.** is the leading independent commercial developer of virtual platforms and high-performance software simulation solutions for embedded processor and systems. Leading semiconductor and embedded software companies use Imperas simulators for their processor based simulation solutions. -[www.imperas.com](http://www.imperas.com/riscv). - -![OVP Image ](http://www.imperas.com/sites/default/files/partner-logos/ovp_0.jpg) -![Imperas Imperas](https://www.imperas.com/sites/default/files/imperas-web-logo_2.png) ---- - -This is the riscvOVPsim/README.md diff --git a/tests/wally-riscv-arch-test/riscv-ovpsim/riscvOVPsim.jpg b/tests/wally-riscv-arch-test/riscv-ovpsim/riscvOVPsim.jpg deleted file mode 100644 index cee3f98ff..000000000 Binary files a/tests/wally-riscv-arch-test/riscv-ovpsim/riscvOVPsim.jpg and /dev/null differ diff --git a/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h deleted file mode 120000 index c1b8c50bc..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h +++ /dev/null @@ -1 +0,0 @@ -../riscv-test-suite/env/arch_test.h \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-env/encoding.h b/tests/wally-riscv-arch-test/riscv-test-env/encoding.h deleted file mode 120000 index fd1833f03..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/encoding.h +++ /dev/null @@ -1 +0,0 @@ -../riscv-test-suite/env/encoding.h \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld deleted file mode 100644 index 392e74f9e..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld +++ /dev/null @@ -1,22 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x00000000; - .text.trap : { *(.text.trap) } - - . = 0x80000000; - .text.init : { *(.text.init) } - - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .data.string : { *(.data.string)} - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h deleted file mode 100644 index e452261c4..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h +++ /dev/null @@ -1,251 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_SINGLE_CORE_H -#define _ENV_PHYSICAL_SINGLE_CORE_H - -#include "../encoding.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#define RVTEST_RV64U \ - .macro init; \ - .endm - -#define RVTEST_RV64UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV32U \ - .macro init; \ - .endm - -#define RVTEST_RV32UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV64M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV64S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#define RVTEST_RV32M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV32S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#if __riscv_xlen == 64 -# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: -#else -# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: -#endif - -#define INIT_PMP \ - la t0, 1f; \ - csrw mtvec, t0; \ - li t0, -1; /* Set up a PMP to permit all accesses */ \ - csrw pmpaddr0, t0; \ - li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ - csrw pmpcfg0, t0; \ - .align 2; \ -1: - -#define INIT_SATP \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi satp, 0; \ - .align 2; \ -1: - -#define DELEGATE_NO_TRAPS \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi medeleg, 0; \ - csrwi mideleg, 0; \ - csrwi mie, 0; \ - .align 2; \ -1: - -#define RVTEST_ENABLE_SUPERVISOR \ - li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ - csrs mstatus, a0; \ - li a0, SIP_SSIP | SIP_STIP; \ - csrs mideleg, a0; \ - -#define RVTEST_ENABLE_MACHINE \ - li a0, MSTATUS_MPP; \ - csrs mstatus, a0; \ - -#define RVTEST_FP_ENABLE \ - li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ - csrs mstatus, a0; \ - csrwi fcsr, 0 - -#define RISCV_MULTICORE_DISABLE \ - csrr a0, mhartid; \ - 1: bnez a0, 1b - -#define EXTRA_TVEC_USER -#define EXTRA_TVEC_MACHINE -#define EXTRA_INIT -#define EXTRA_INIT_TIMER - -// -// undefine some unusable CSR Accesses if no PRIV Mode present -// -#if defined(PRIV_MISA_S) -# if (PRIV_MISA_S==0) -# undef INIT_SATP -# define INIT_SATP -# undef INIT_PMP -# define INIT_PMP -# undef DELEGATE_NO_TRAPS -# define DELEGATE_NO_TRAPS -# undef RVTEST_ENABLE_SUPERVISOR -# define RVTEST_ENABLE_SUPERVISOR -# endif -#endif -#if defined(PRIV_MISA_U) -# if (PRIV_MISA_U==0) -# endif -#endif -#if defined(TRAPHANDLER) -#include TRAPHANDLER -#endif - -#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ - -#define RVTEST_CODE_BEGIN_OLD \ - .section .text.init; \ - .align 6; \ - .weak stvec_handler; \ - .weak mtvec_handler; \ - .globl _start; \ -_start: \ - /* reset vector */ \ - j reset_vector; \ - .align 2; \ -trap_vector: \ - /* test whether the test came from pass/fail */ \ - csrr t5, mcause; \ - li t6, CAUSE_USER_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_SUPERVISOR_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_MACHINE_ECALL; \ - beq t5, t6, write_tohost; \ - /* if an mtvec_handler is defined, jump to it */ \ - la t5, mtvec_handler; \ - beqz t5, 1f; \ - jr t5; \ - /* was it an interrupt or an exception? */ \ - 1: csrr t5, mcause; \ - bgez t5, handle_exception; \ - INTERRUPT_HANDLER; \ -handle_exception: \ - /* we don't know how to handle whatever the exception was */ \ - other_exception: \ - /* some unhandlable exception occurred */ \ - 1: ori TESTNUM, TESTNUM, 1337; \ - write_tohost: \ - sw TESTNUM, tohost, t5; \ - j write_tohost; \ -reset_vector: \ - RISCV_MULTICORE_DISABLE; \ - INIT_SATP; \ - INIT_PMP; \ - DELEGATE_NO_TRAPS; \ - li TESTNUM, 0; \ - la t0, trap_vector; \ - csrw mtvec, t0; \ - CHECK_XLEN; \ - /* if an stvec_handler is defined, delegate exceptions to it */ \ - la t0, stvec_handler; \ - beqz t0, 1f; \ - csrw stvec, t0; \ - li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \ - (1 << CAUSE_STORE_PAGE_FAULT) | \ - (1 << CAUSE_FETCH_PAGE_FAULT) | \ - (1 << CAUSE_MISALIGNED_FETCH) | \ - (1 << CAUSE_USER_ECALL) | \ - (1 << CAUSE_BREAKPOINT); \ - csrw medeleg, t0; \ - csrr t1, medeleg; \ - bne t0, t1, other_exception; \ -1: csrwi mstatus, 0; \ - init; \ - EXTRA_INIT; \ - EXTRA_INIT_TIMER; \ - la t0, 1f; \ - csrw mepc, t0; \ - csrr a0, mhartid; \ - mret; \ -1: \ -begin_testcode: - - -//----------------------------------------------------------------------- -// End Macro -//----------------------------------------------------------------------- - -#define RVTEST_CODE_END_OLD \ -end_testcode: \ - ecall; - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- -#define RVTEST_SYNC fence -//#define RVTEST_SYNC nop - -#define RVTEST_PASS \ - RVTEST_SYNC; \ - li TESTNUM, 1; \ - SWSIG (0, TESTNUM); \ - ecall - -#define TESTNUM gp -#define RVTEST_FAIL \ - RVTEST_SYNC; \ -1: beqz TESTNUM, 1b; \ - sll TESTNUM, TESTNUM, 1; \ - or TESTNUM, TESTNUM, 1; \ - SWSIG (0, TESTNUM); \ - la x1, end_testcode; \ - jr x1; - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#define EXTRA_DATA - -#define RVTEST_DATA_BEGIN_OLD \ - .align 4; .global begin_signature; begin_signature: - -#define RVTEST_DATA_END_OLD \ - .align 4; .global end_signature; end_signature: \ - EXTRA_DATA \ - .pushsection .tohost,"aw",@progbits; \ - .align 8; .global tohost; tohost: .dword 0; \ - .align 8; .global fromhost; fromhost: .dword 0; \ - .popsection; \ - .align 8; .global begin_regstate; begin_regstate: \ - .word 128; \ - .align 8; .global end_regstate; end_regstate: \ - .word 4; - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld deleted file mode 100644 index b3e315e78..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x80000000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h deleted file mode 100644 index 38a0e86b8..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h +++ /dev/null @@ -1,11 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_MULTI_CORE_H -#define _ENV_PHYSICAL_MULTI_CORE_H - -#include "../p/riscv_test.h" - -#undef RISCV_MULTICORE_DISABLE -#define RISCV_MULTICORE_DISABLE - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld deleted file mode 100644 index b3e315e78..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x80000000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h deleted file mode 100644 index 34c2a331a..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h +++ /dev/null @@ -1,69 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H -#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H - -#include "../p/riscv_test.h" - -#define TIMER_INTERVAL 2 - -#undef EXTRA_INIT_TIMER -#define EXTRA_INIT_TIMER \ - li a0, MIP_MTIP; \ - csrs mie, a0; \ - csrr a0, mtime; \ - addi a0, a0, TIMER_INTERVAL; \ - csrw mtimecmp, a0; \ - -#if SSTATUS_XS != 0x18000 -# error -#endif -#define XS_SHIFT 15 - -#undef INTERRUPT_HANDLER -#define INTERRUPT_HANDLER \ - slli t5, t5, 1; \ - srli t5, t5, 1; \ - add t5, t5, -IRQ_M_TIMER; \ - bnez t5, other_exception; /* other interrups shouldn't happen */\ - csrr t5, mtime; \ - addi t5, t5, TIMER_INTERVAL; \ - csrw mtimecmp, t5; \ - mret; \ - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#undef EXTRA_DATA -#define EXTRA_DATA \ - .align 3; \ -regspill: \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ -evac: \ - .skip 32768; \ - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S b/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S deleted file mode 100644 index 97196620f..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S +++ /dev/null @@ -1,125 +0,0 @@ -#include "riscv_test.h" - -#if __riscv_xlen == 64 -# define STORE sd -# define LOAD ld -# define REGBYTES 8 -#else -# define STORE sw -# define LOAD lw -# define REGBYTES 4 -#endif - -#define STACK_TOP (_end + 4096) - - .section ".text.init","ax",@progbits - .globl _start -_start: - j handle_reset - - /* NMI vector */ -nmi_vector: - j wtf - -trap_vector: - j wtf - -handle_reset: - la t0, trap_vector - csrw mtvec, t0 - la sp, STACK_TOP - SIZEOF_TRAPFRAME_T - csrr t0, mhartid - slli t0, t0, 12 - add sp, sp, t0 - csrw mscratch, sp - la a0, userstart - j vm_boot - - .globl pop_tf -pop_tf: - LOAD t0,33*REGBYTES(a0) - csrw sepc,t0 - LOAD x1,1*REGBYTES(a0) - LOAD x2,2*REGBYTES(a0) - LOAD x3,3*REGBYTES(a0) - LOAD x4,4*REGBYTES(a0) - LOAD x5,5*REGBYTES(a0) - LOAD x6,6*REGBYTES(a0) - LOAD x7,7*REGBYTES(a0) - LOAD x8,8*REGBYTES(a0) - LOAD x9,9*REGBYTES(a0) - LOAD x11,11*REGBYTES(a0) - LOAD x12,12*REGBYTES(a0) - LOAD x13,13*REGBYTES(a0) - LOAD x14,14*REGBYTES(a0) - LOAD x15,15*REGBYTES(a0) - LOAD x16,16*REGBYTES(a0) - LOAD x17,17*REGBYTES(a0) - LOAD x18,18*REGBYTES(a0) - LOAD x19,19*REGBYTES(a0) - LOAD x20,20*REGBYTES(a0) - LOAD x21,21*REGBYTES(a0) - LOAD x22,22*REGBYTES(a0) - LOAD x23,23*REGBYTES(a0) - LOAD x24,24*REGBYTES(a0) - LOAD x25,25*REGBYTES(a0) - LOAD x26,26*REGBYTES(a0) - LOAD x27,27*REGBYTES(a0) - LOAD x28,28*REGBYTES(a0) - LOAD x29,29*REGBYTES(a0) - LOAD x30,30*REGBYTES(a0) - LOAD x31,31*REGBYTES(a0) - LOAD a0,10*REGBYTES(a0) - sret - - .global trap_entry -trap_entry: - csrrw sp, sscratch, sp - - # save gprs - STORE x1,1*REGBYTES(sp) - STORE x3,3*REGBYTES(sp) - STORE x4,4*REGBYTES(sp) - STORE x5,5*REGBYTES(sp) - STORE x6,6*REGBYTES(sp) - STORE x7,7*REGBYTES(sp) - STORE x8,8*REGBYTES(sp) - STORE x9,9*REGBYTES(sp) - STORE x10,10*REGBYTES(sp) - STORE x11,11*REGBYTES(sp) - STORE x12,12*REGBYTES(sp) - STORE x13,13*REGBYTES(sp) - STORE x14,14*REGBYTES(sp) - STORE x15,15*REGBYTES(sp) - STORE x16,16*REGBYTES(sp) - STORE x17,17*REGBYTES(sp) - STORE x18,18*REGBYTES(sp) - STORE x19,19*REGBYTES(sp) - STORE x20,20*REGBYTES(sp) - STORE x21,21*REGBYTES(sp) - STORE x22,22*REGBYTES(sp) - STORE x23,23*REGBYTES(sp) - STORE x24,24*REGBYTES(sp) - STORE x25,25*REGBYTES(sp) - STORE x26,26*REGBYTES(sp) - STORE x27,27*REGBYTES(sp) - STORE x28,28*REGBYTES(sp) - STORE x29,29*REGBYTES(sp) - STORE x30,30*REGBYTES(sp) - STORE x31,31*REGBYTES(sp) - - csrrw t0,sscratch,sp - STORE t0,2*REGBYTES(sp) - - # get sr, epc, badvaddr, cause - csrr t0,sstatus - STORE t0,32*REGBYTES(sp) - csrr t0,sepc - STORE t0,33*REGBYTES(sp) - csrr t0,sbadaddr - STORE t0,34*REGBYTES(sp) - csrr t0,scause - STORE t0,35*REGBYTES(sp) - - move a0, sp - j handle_trap diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld deleted file mode 100644 index b3e315e78..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x80000000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h deleted file mode 100644 index 8ca9ffd76..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h +++ /dev/null @@ -1,71 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_VIRTUAL_SINGLE_CORE_H -#define _ENV_VIRTUAL_SINGLE_CORE_H - -#include "../p/riscv_test.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#undef RVTEST_FP_ENABLE -#define RVTEST_FP_ENABLE fssr x0 - -#undef RVTEST_CODE_BEGIN -#define RVTEST_CODE_BEGIN \ - .text; \ - .global userstart; \ -userstart: \ - init - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#undef RVTEST_PASS -#define RVTEST_PASS li a0, 1; scall - -#undef RVTEST_FAIL -#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall; - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#undef RVTEST_DATA_END -#define RVTEST_DATA_END - -//----------------------------------------------------------------------- -// Supervisor mode definitions and macros -//----------------------------------------------------------------------- - -#define MAX_TEST_PAGES 63 // this must be the period of the LFSR below -#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1)) - -#define PGSHIFT 12 -#define PGSIZE (1UL << PGSHIFT) - -#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36) - -#ifndef __ASSEMBLER__ - -typedef unsigned long pte_t; -#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2) -#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2)) -#define VPN_BITS (PTIDXBITS * LEVELS) -#define VA_BITS (VPN_BITS + PGSHIFT) -#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS) -#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE) - -typedef struct -{ - long gpr[32]; - long sr; - long epc; - long badvaddr; - long cause; -} trapframe_t; -#endif - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/string.c b/tests/wally-riscv-arch-test/riscv-test-env/v/string.c deleted file mode 100644 index 4ffedc0a4..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/string.c +++ /dev/null @@ -1,114 +0,0 @@ -#include -#include -#include - -void* memcpy(void* dest, const void* src, size_t len) -{ - if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { - const uintptr_t* s = src; - uintptr_t *d = dest; - while (d < (uintptr_t*)(dest + len)) - *d++ = *s++; - } else { - const char* s = src; - char *d = dest; - while (d < (char*)(dest + len)) - *d++ = *s++; - } - return dest; -} - -void* memset(void* dest, int byte, size_t len) -{ - if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { - uintptr_t word = byte & 0xFF; - word |= word << 8; - word |= word << 16; - word |= word << 16 << 16; - - uintptr_t *d = dest; - while (d < (uintptr_t*)(dest + len)) - *d++ = word; - } else { - char *d = dest; - while (d < (char*)(dest + len)) - *d++ = byte; - } - return dest; -} - -size_t strlen(const char *s) -{ - const char *p = s; - while (*p) - p++; - return p - s; -} - -int strcmp(const char* s1, const char* s2) -{ - unsigned char c1, c2; - - do { - c1 = *s1++; - c2 = *s2++; - } while (c1 != 0 && c1 == c2); - - return c1 - c2; -} - -int memcmp(const void* s1, const void* s2, size_t n) -{ - if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) { - const uintptr_t* u1 = s1; - const uintptr_t* u2 = s2; - const uintptr_t* end = u1 + (n / sizeof(uintptr_t)); - while (u1 < end) { - if (*u1 != *u2) - break; - u1++; - u2++; - } - n -= (const void*)u1 - s1; - s1 = u1; - s2 = u2; - } - - while (n--) { - unsigned char c1 = *(const unsigned char*)s1++; - unsigned char c2 = *(const unsigned char*)s2++; - if (c1 != c2) - return c1 - c2; - } - - return 0; -} - -char* strcpy(char* dest, const char* src) -{ - char* d = dest; - while ((*d++ = *src++)) - ; - return dest; -} - -long atol(const char* str) -{ - long res = 0; - int sign = 0; - - while (*str == ' ') - str++; - - if (*str == '-' || *str == '+') { - sign = *str == '-'; - str++; - } - - while (*str) { - res *= 10; - res += *str++ - '0'; - } - - return sign ? -res : res; -} diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c b/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c deleted file mode 100644 index 8064b7baf..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c +++ /dev/null @@ -1,273 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include - -#include "riscv_test.h" - -void trap_entry(); -void pop_tf(trapframe_t*); - -volatile uint64_t tohost; -volatile uint64_t fromhost; - -static void do_tohost(uint64_t tohost_value) -{ - while (tohost) - fromhost = 0; - tohost = tohost_value; -} - -#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE) -#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE) - -#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory") - -static uint64_t lfsr63(uint64_t x) -{ - uint64_t bit = (x ^ (x >> 1)) & 1; - return (x >> 1) | (bit << 62); -} - -static void cputchar(int x) -{ - do_tohost(0x0101000000000000 | (unsigned char)x); -} - -static void cputstring(const char* s) -{ - while (*s) - cputchar(*s++); -} - -static void terminate(int code) -{ - do_tohost(code); - while (1); -} - -void wtf() -{ - terminate(841); -} - -#define stringify1(x) #x -#define stringify(x) stringify1(x) -#define assert(x) do { \ - if (x) break; \ - cputstring("Assertion failed: " stringify(x) "\n"); \ - terminate(3); \ -} while(0) - -#define l1pt pt[0] -#define user_l2pt pt[1] -#if __riscv_xlen == 64 -# define NPT 4 -#define kernel_l2pt pt[2] -# define user_l3pt pt[3] -#else -# define NPT 2 -# define user_l3pt user_l2pt -#endif -pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE))); - -typedef struct { pte_t addr; void* next; } freelist_t; - -freelist_t user_mapping[MAX_TEST_PAGES]; -freelist_t freelist_nodes[MAX_TEST_PAGES]; -freelist_t *freelist_head, *freelist_tail; - -void printhex(uint64_t x) -{ - char str[17]; - for (int i = 0; i < 16; i++) - { - str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); - x >>= 4; - } - str[16] = 0; - - cputstring(str); -} - -static void evict(unsigned long addr) -{ - assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); - addr = addr/PGSIZE*PGSIZE; - - freelist_t* node = &user_mapping[addr/PGSIZE]; - if (node->addr) - { - // check accessed and dirty bits - assert(user_l3pt[addr/PGSIZE] & PTE_A); - uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); - if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) { - assert(user_l3pt[addr/PGSIZE] & PTE_D); - memcpy((void*)addr, uva2kva(addr), PGSIZE); - } - write_csr(sstatus, sstatus); - - user_mapping[addr/PGSIZE].addr = 0; - - if (freelist_tail == 0) - freelist_head = freelist_tail = node; - else - { - freelist_tail->next = node; - freelist_tail = node; - } - } -} - -void handle_fault(uintptr_t addr, uintptr_t cause) -{ - assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); - addr = addr/PGSIZE*PGSIZE; - - if (user_l3pt[addr/PGSIZE]) { - if (!(user_l3pt[addr/PGSIZE] & PTE_A)) { - user_l3pt[addr/PGSIZE] |= PTE_A; - } else { - assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT); - user_l3pt[addr/PGSIZE] |= PTE_D; - } - flush_page(addr); - return; - } - - freelist_t* node = freelist_head; - assert(node); - freelist_head = node->next; - if (freelist_head == freelist_tail) - freelist_tail = 0; - - uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X; - user_l3pt[addr/PGSIZE] = new_pte | PTE_A | PTE_D; - flush_page(addr); - - assert(user_mapping[addr/PGSIZE].addr == 0); - user_mapping[addr/PGSIZE] = *node; - - uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); - memcpy((void*)addr, uva2kva(addr), PGSIZE); - write_csr(sstatus, sstatus); - - user_l3pt[addr/PGSIZE] = new_pte; - flush_page(addr); - - __builtin___clear_cache(0,0); -} - -void handle_trap(trapframe_t* tf) -{ - if (tf->cause == CAUSE_USER_ECALL) - { - int n = tf->gpr[10]; - - for (long i = 1; i < MAX_TEST_PAGES; i++) - evict(i*PGSIZE); - - terminate(n); - } - else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) - { - assert(tf->epc % 4 == 0); - - int* fssr; - asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr)); - - if (*(int*)tf->epc == *fssr) - terminate(1); // FP test on non-FP hardware. "succeed." - else - assert(!"illegal instruction"); - tf->epc += 4; - } - else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT) - handle_fault(tf->badvaddr, tf->cause); - else - assert(!"unexpected exception"); - - pop_tf(tf); -} - -static void coherence_torture() -{ - // cause coherence misses without affecting program semantics - unsigned int random = ENTROPY; - while (1) { - uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4); -#ifdef __riscv_atomic - if (random & 1) // perform a no-op write - asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr)); - else // perform a read -#endif - asm volatile ("lw zero, (%0)" :: "r"(paddr)); - random = lfsr63(random); - } -} - -void vm_boot(uintptr_t test_addr) -{ - unsigned int random = ENTROPY; - if (read_csr(mhartid) > 0) - coherence_torture(); - - _Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???"); - -#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0 -# error -#endif - // map user to lowermost megapage - l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - // map kernel to uppermost megapage -#if __riscv_xlen == 64 - l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; - user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - uintptr_t vm_choice = SATP_MODE_SV39; -#else - l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; - uintptr_t vm_choice = SATP_MODE_SV32; -#endif - write_csr(satp, ((uintptr_t)l1pt >> PGSHIFT) | - (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)))); - - // Set up PMPs if present, ignoring illegal instruction trap if not. - uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; - asm volatile ("la t0, 1f\n\t" - "csrrw t0, mtvec, t0\n\t" - "csrw pmpaddr0, %1\n\t" - "csrw pmpcfg0, %0\n\t" - ".align 2\n\t" - "1:" - : : "r" (pmpc), "r" (-1UL) : "t0"); - - // set up supervisor trap handling - write_csr(stvec, pa2kva(trap_entry)); - write_csr(sscratch, pa2kva(read_csr(mscratch))); - write_csr(medeleg, - (1 << CAUSE_USER_ECALL) | - (1 << CAUSE_FETCH_PAGE_FAULT) | - (1 << CAUSE_LOAD_PAGE_FAULT) | - (1 << CAUSE_STORE_PAGE_FAULT)); - // FPU on; accelerator on; allow supervisor access to user memory access - write_csr(mstatus, MSTATUS_FS | MSTATUS_XS); - write_csr(mie, 0); - - random = 1 + (random % MAX_TEST_PAGES); - freelist_head = pa2kva((void*)&freelist_nodes[0]); - freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]); - for (long i = 0; i < MAX_TEST_PAGES; i++) - { - freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE; - freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]); - random = LFSR_NEXT(random); - } - freelist_nodes[MAX_TEST_PAGES-1].next = 0; - - trapframe_t tf; - memset(&tf, 0, sizeof(tf)); - tf.epc = test_addr - DRAM_BASE; - pop_tf(&tf); -} diff --git a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh index f69a4c633..543854982 100755 --- a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh +++ b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh @@ -28,7 +28,8 @@ do echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m" continue fi - diff --ignore-case --strip-trailing-cr ${ref} ${sig} &> /dev/null + # KMG: changed diff snippet to a grep that will strip comments with '//' and '#' out of the reference file + diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^//#]*' ${ref}) ${sig} &> /dev/null if [ $? == 0 ] then echo -e "\e[32m ... OK \e[39m" diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include index 35ca54187..ae84be741 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include +++ b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include @@ -63,8 +63,9 @@ copy: $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) $(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>) $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) - $(V) echo "Copying References without simulating" - $(V) for test in $(target_tests_nosim); do cp $(ref_dir)/$$test.reference_output $(work_dir_isa)/$$test.signature.output; done + $(V) echo "Copying References without simulating for the following tests:" + $(V) echo $(target_tests_nosim) + $(V) for test in $(target_tests_nosim); do grep -o '^[^//#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done compile: $(combined_elf) run: $(target_log) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefile deleted file mode 100644 index b9410d41f..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv32e -mabi=ilp32e -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefrag deleted file mode 100644 index b7c5692a5..000000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefrag +++ /dev/null @@ -1,73 +0,0 @@ -# RISC-V Architecture Test RV32E Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV32E architectural tests - -rv32e_sc_tests = \ - add-01 \ - addi-01 \ - and-01 \ - andi-01 \ - auipc-01 \ - beq-01 \ - bge-01 \ - bgeu-01 \ - blt-01 \ - bltu-01 \ - bne-01 \ - jal-01 \ - jalr-01 \ - lb-align-01 \ - lbu-align-01 \ - lh-align-01 \ - lhu-align-01 \ - lui-01 \ - lw-align-01 \ - or-01 \ - ori-01 \ - sb-align-01 \ - sh-align-01 \ - sll-01 \ - slli-01 \ - slt-01 \ - slti-01 \ - sltiu-01 \ - sltu-01 \ - sra-01 \ - srai-01 \ - srl-01 \ - srli-01 \ - sub-01 \ - sw-align-01 \ - xor-01 \ - xori-01 - - - -rv32e_tests = $(addsuffix .elf, $(rv32e_sc_tests)) - -target_tests += $(rv32e_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag index fbd60d306..792ea2e24 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag @@ -28,11 +28,48 @@ # Description: Makefrag for RV32I architectural tests rv32i_sc_tests = \ + E-add-01 \ + E-addi-01 \ + E-and-01 \ + E-andi-01 \ + E-auipc-01 \ + E-beq-01 \ + E-bge-01 \ + E-bgeu-01 \ + E-blt-01 \ + E-bltu-01 \ + E-bne-01 \ + E-jal-01 \ + E-jalr-01 \ + E-lb-align-01 \ + E-lbu-align-01 \ + E-lh-align-01 \ + E-lhu-align-01 \ + E-lui-01 \ + E-lw-align-01 \ + E-or-01 \ + E-ori-01 \ + E-sb-align-01 \ + E-sh-align-01 \ + E-sll-01 \ + E-slli-01 \ + E-slt-01 \ + E-slti-01 \ + E-sltiu-01 \ + E-sltu-01 \ + E-sra-01 \ + E-srai-01 \ + E-srl-01 \ + E-srli-01 \ + E-sub-01 \ + E-sw-align-01 \ + E-xor-01 \ + E-xori-01 \ WALLY-ADD \ - WALLY-SUB \ - WALLY-SLT \ + WALLY-SLT \ WALLY-SLTU \ - WALLY-XOR + WALLY-SUB \ + WALLY-XOR rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/add-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/add-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output index 4d18d6a9c..b364d3f1a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/add-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output @@ -581,3 +581,4 @@ ddddddde 3333e836 e000001f f0000003 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/addi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/addi-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output index 752d52626..1052749cb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/addi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output @@ -559,3 +559,6 @@ aaaaadde aaaaaab0 c000003f fdffffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/and-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/and-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/andi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/andi-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output index 1863cd1f2..aefc28d98 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/andi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output @@ -552,3 +552,5 @@ aaaaaa80 00000002 00000002 00000555 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/auipc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/auipc-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output index ebf77d350..5f432d03a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/auipc-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output @@ -61,3 +61,4 @@ aaaa9000 33333000 00005000 ff7ff000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/beq-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/beq-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output index 92f1ee6d0..becb2fbf7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/beq-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output @@ -588,3 +588,5 @@ 00000002 00000002 00000002 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bge-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bge-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output index cf462405e..fe7d8af34 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bge-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output @@ -584,3 +584,5 @@ 00000002 00000003 00000001 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bgeu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bgeu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/blt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/blt-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output index f0e22e7c0..cdd9263f4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/blt-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output @@ -584,3 +584,5 @@ 00000002 00000002 00000002 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bltu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output index 4498f93a3..8776eb6ab 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bltu-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output @@ -725,3 +725,4 @@ 00000001 00000003 00000003 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bne-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bne-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output index 7f8a8e6c6..b537bf369 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bne-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output @@ -583,3 +583,6 @@ 00000003 00000001 00000001 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jal-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jal-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jalr-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output similarity index 96% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jalr-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output index a05f0b1d5..0793fe3ab 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jalr-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output @@ -25,3 +25,4 @@ 00000017 00000017 00000017 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lb-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output similarity index 90% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lb-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output index 246a44924..4f84c0482 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lb-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output @@ -16,3 +16,5 @@ ffffffba ffffffba ffffffba ffffffba +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lbu-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output similarity index 85% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lbu-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output index ddd4233bb..74d8f0919 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lbu-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output @@ -15,3 +15,6 @@ 000000ba 000000ba 000000ba +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lh-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lh-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lhu-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lhu-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lui-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lui-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output index def191172..0e37658c3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lui-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output @@ -61,3 +61,4 @@ aaaa9000 33333000 00005000 fff7f000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lw-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lw-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/or-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/or-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output index ea67773d1..ee838bce3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/or-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output @@ -587,3 +587,6 @@ efffffff feffffff ff7fffff ffffffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/ori-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/ori-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output index f97d23397..e092fd1af 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/ori-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output @@ -555,3 +555,6 @@ aaaaaeef aaaaabbe aaaaaaae 7fffffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sb-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output similarity index 97% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sb-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output index cd1d694f9..9c4bc8218 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sb-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output @@ -76,3 +76,5 @@ deadbe80 deadbe20 deadbe04 deadbe02 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sh-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sh-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output index fcfc68eca..7e989c340 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sh-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output @@ -69,3 +69,4 @@ dead0008 dead0004 dead0002 deadffff +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sll-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sll-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output similarity index 96% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slli-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output index 242ca0707..883654689 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slli-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output @@ -87,3 +87,6 @@ cccccc00 28000000 ffffff80 ffff0000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slt-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output index 211acb80a..eb7f04427 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slt-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output @@ -579,3 +579,6 @@ 00000000 00000001 00000000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slti-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slti-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output index 65bf06a2b..a0b62cb23 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slti-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output @@ -559,3 +559,6 @@ 00000001 00000001 00000001 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltiu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltiu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output index 8bef9035d..be272395d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltiu-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output @@ -695,3 +695,6 @@ 00000001 00000000 00000000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output index 95fdde41a..a0e45d5ab 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltu-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output @@ -720,3 +720,5 @@ 00000000 00000001 00000001 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sra-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output similarity index 97% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sra-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output index 76d4a21d6..40928fa2e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sra-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output @@ -88,3 +88,5 @@ fffffffd 00000000 fffeffff fffeffff +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srai-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srai-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output index d0482c92b..23cef3334 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srai-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output @@ -85,3 +85,4 @@ ffffffff 00000ccc ffffffff ffffffbf +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srl-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output similarity index 96% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srl-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output index 1ff02aae6..6cdc318c2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srl-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output @@ -87,3 +87,6 @@ fffffffb 00000007 0003bfff 0ffdffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srli-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sub-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sub-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sw-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sw-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xor-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xor-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output index dcd028b8d..848bc88e3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xor-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output @@ -581,3 +581,4 @@ bffffbff dfffdfff effffffe 00050000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xori-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xori-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output index 72862a594..a17012ecf 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xori-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output @@ -557,3 +557,4 @@ aaaaa99e aaaaaaac fffefdff ffff7fff +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/add-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/add-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S index 9336eccf9..4abf30fdf 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/add-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the add instruction of the RISC-V E extension for the add covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/addi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/addi-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S index 839748400..87ce8463e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/addi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the addi instruction of the RISC-V E extension for the addi covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/and-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/and-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S index 41d5e406f..dca83d0f0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/and-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the and instruction of the RISC-V E extension for the and covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/andi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/andi-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S index 3dcd009d2..2114d6aee 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/andi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the andi instruction of the RISC-V E extension for the andi covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/auipc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/auipc-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S index 87eed4cd9..517a4b8d1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/auipc-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the auipc instruction of the RISC-V E extension for the auipc covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/beq-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/beq-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S index a8a75c632..946402467 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/beq-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the beq instruction of the RISC-V E extension for the beq covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bge-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bge-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S index e468772c8..d8cd00477 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bge-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bge instruction of the RISC-V E extension for the bge covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bgeu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bgeu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S index 2b9d38768..43bf2ec72 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bgeu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bgeu instruction of the RISC-V E extension for the bgeu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/blt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/blt-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S index 886a17eba..a23350a44 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/blt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the blt instruction of the RISC-V E extension for the blt covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bltu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S index f8042b147..e6e5b69ac 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bltu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bltu instruction of the RISC-V E extension for the bltu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bne-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bne-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S index 58a333c0e..92ccd2b4f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bne-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bne instruction of the RISC-V E extension for the bne covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jal-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jal-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S index b3870318b..2fd3e9e2b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jal-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the jal instruction of the RISC-V E extension for the jal covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jalr-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jalr-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S index 2b58baf13..c8ac34760 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jalr-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the jalr instruction of the RISC-V E extension for the jalr covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lb-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S index 2b50abf21..d42f83ccd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lb-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lb instruction of the RISC-V E extension for the lb-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lbu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lbu-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S index 0e73a6815..bc2c0527d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lbu-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lbu instruction of the RISC-V E extension for the lbu-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lh-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S index 516273335..e16cb695d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lh-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lh instruction of the RISC-V E extension for the lh-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lhu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lhu-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S index 8d4c28e77..9e4427ca5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lhu-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lhu instruction of the RISC-V E extension for the lhu-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lui-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lui-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S index 81fbc741d..f1257005f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lui-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lui instruction of the RISC-V E extension for the lui covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lw-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S index a8dafa825..e1f368a9b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lw-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lw instruction of the RISC-V E extension for the lw-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/or-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/or-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S index e5032b059..193785007 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/or-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the or instruction of the RISC-V E extension for the or covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/ori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/ori-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S index fa55b6bf3..3c8078862 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/ori-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the ori instruction of the RISC-V E extension for the ori covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sb-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S index 2684e12d0..3eaf9072c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sb-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sb instruction of the RISC-V E extension for the sb-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sh-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S index 6dd42781a..86d7c2781 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sh-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sh instruction of the RISC-V E extension for the sh-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sll-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sll-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S index af03abc7f..f219b7af4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sll-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sll instruction of the RISC-V E extension for the sll covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slli-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S index 13226b35c..754c14a5d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slli-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the slli instruction of the RISC-V E extension for the slli covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slt-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S index 9a17362b8..f7c57a553 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the slt instruction of the RISC-V E extension for the slt covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slti-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slti-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S index 8c53c538c..c0a3feccd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slti-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the slti instruction of the RISC-V E extension for the slti covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltiu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltiu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S index 65b2c2a8f..79336c4f0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltiu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sltiu instruction of the RISC-V E extension for the sltiu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S index 999007f7c..b28398c3d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sltu instruction of the RISC-V E extension for the sltu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sra-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sra-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S index 98801fb44..7e3e8c253 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sra-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sra instruction of the RISC-V E extension for the sra covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srai-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srai-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S index 7e5a571ad..e87f2b740 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srai-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the srai instruction of the RISC-V E extension for the srai covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srl-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srl-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S index b392ecba8..80f27c5fd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srl-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the srl instruction of the RISC-V E extension for the srl covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srli-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S index d47f805a4..8ecc2f5dc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srli-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the srli instruction of the RISC-V E extension for the srli covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sub-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sub-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S index e09411fdc..60ce1b737 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sub-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sub instruction of the RISC-V E extension for the sub covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sw-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S index aae0ca476..71dd41b89 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sw-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sw instruction of the RISC-V E extension for the sw-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xor-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S index cb30a2617..41fa0ac9d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xor-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the xor instruction of the RISC-V E extension for the xor covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xori-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S index 00d85cb19..cc3f509f7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xori-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the xori instruction of the RISC-V E extension for the xori covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index aa30cdc79..e8c000283 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -31,7 +31,9 @@ rv64i_sc_tests = \ WALLY-MMU-SV39 \ WALLY-MMU-SV48 \ WALLY-PMP \ - WALLY-minfo-01 + WALLY-minfo-01 \ + WALLY-CSR-permission-s-01 \ + WALLY-CSR-permission-u-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output new file mode 100644 index 000000000..811bfe7ca --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to S mode from M mode +00000000 +00000002 # S mode write to mvendorid with illegal instruction +00000000 +00000002 # S mode read from mvendorid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to marchid with illegal instruction +00000000 +00000002 # S mode read from marchid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mimpid with illegal instruction +00000000 +00000002 # S mode read from mimpid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhartid with illegal instruction +00000000 +00000002 # S mode read from mhartid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mstatus with illegal instruction +00000000 +00000002 # S mode read from mstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to misa with illegal instruction +00000000 +00000002 # S mode read from misa with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to medeleg with illegal instruction +00000000 +00000002 # S mode read from medeleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mideleg with illegal instruction +00000000 +00000002 # S mode read from mideleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mie with illegal instruction +00000000 +00000002 # S mode read from mie with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mtvec with illegal instruction +00000000 +00000002 # S mode read from mtvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcounteren with illegal instruction +00000000 +00000002 # S mode read from mcounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mscratch with illegal instruction +00000000 +00000002 # S mode read from mscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mepc with illegal instruction +00000000 +00000002 # S mode read from mepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcause with illegal instruction +00000000 +00000002 # S mode read from mcause with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mtval with illegal instruction +00000000 +00000002 # S mode read from mtval with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mip with illegal instruction +00000000 +00000002 # S mode read from mip with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpcfg0 with illegal instruction +00000000 +00000002 # S mode read from pmpcfg0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpcfg2 with illegal instruction +00000000 +00000002 # S mode read from pmpcfg2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr0 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr1 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr1 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr2 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr3 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr4 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr5 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr6 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr7 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr8 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr9 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr10 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr11 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr12 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr13 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr14 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr15 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcycle with illegal instruction +00000000 +00000002 # S mode read from mcycle with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to minstret with illegal instruction +00000000 +00000002 # S mode read from minstret with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter3 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter4 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter5 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter6 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter7 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter8 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter9 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter10 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter11 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter12 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter13 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter14 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter15 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter16 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter17 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter18 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter19 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter20 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter21 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter22 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter23 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter24 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter25 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter26 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter27 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter28 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter29 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter30 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter31 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter31 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcountinhibit with illegal instruction +00000000 +00000002 # S mode read from mcountinhibit with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent3 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent4 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent5 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent6 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent7 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent8 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent9 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent10 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent11 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent12 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent13 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent14 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent15 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent16 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent17 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent18 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent19 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent20 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent21 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent22 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent23 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent24 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent25 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent26 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent27 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent28 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent29 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent30 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent31 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent31 with illegal instruction +00000000 +00000bad +00000000 +00000009 # ecall from terminating tess from S mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output new file mode 100644 index 000000000..c8cd62ab1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to U mode from M mode +00000000 +00000002 # U mode write to sstatus with illegal instruction +00000000 +00000002 # U mode read from sstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sie with illegal instruction +00000000 +00000002 # U mode read from sie with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to stvec with illegal instruction +00000000 +00000002 # U mode read from stvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to scounteren with illegal instruction +00000000 +00000002 # U mode read from scounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sscratch with illegal instruction +00000000 +00000002 # U mode read from sscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sepc with illegal instruction +00000000 +00000002 # U mode read from sepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to scause with illegal instruction +00000000 +00000002 # U mode read from scause with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to stval with illegal instruction +00000000 +00000002 # U mode read from stval with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sip with illegal instruction +00000000 +00000002 # U mode read from sip with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to satp with illegal instruction +00000000 +00000002 # U mode read from satp with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mvendorid with illegal instruction +00000000 +00000002 # U mode read from mvendorid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to marchid with illegal instruction +00000000 +00000002 # U mode read from marchid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mimpid with illegal instruction +00000000 +00000002 # U mode read from mimpid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhartid with illegal instruction +00000000 +00000002 # U mode read from mhartid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mstatus with illegal instruction +00000000 +00000002 # U mode read from mstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to misa with illegal instruction +00000000 +00000002 # U mode read from misa with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to medeleg with illegal instruction +00000000 +00000002 # U mode read from medeleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mideleg with illegal instruction +00000000 +00000002 # U mode read from mideleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mie with illegal instruction +00000000 +00000002 # U mode read from mie with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mtvec with illegal instruction +00000000 +00000002 # U mode read from mtvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcounteren with illegal instruction +00000000 +00000002 # U mode read from mcounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mscratch with illegal instruction +00000000 +00000002 # U mode read from mscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mepc with illegal instruction +00000000 +00000002 # U mode read from mepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcause with illegal instruction +00000000 +00000002 # U mode read from mcause with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mtval with illegal instruction +00000000 +00000002 # U mode read from mtval with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mip with illegal instruction +00000000 +00000002 # U mode read from mip with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpcfg0 with illegal instruction +00000000 +00000002 # U mode read from pmpcfg0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpcfg2 with illegal instruction +00000000 +00000002 # U mode read from pmpcfg2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr0 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr1 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr1 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr2 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr3 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr4 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr5 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr6 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr7 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr8 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr9 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr10 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr11 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr12 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr13 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr14 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr15 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcycle with illegal instruction +00000000 +00000002 # U mode read from mcycle with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to minstret with illegal instruction +00000000 +00000002 # U mode read from minstret with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter3 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter4 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter5 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter6 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter7 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter8 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter9 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter10 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter11 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter12 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter13 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter14 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter15 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter16 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter17 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter18 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter19 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter20 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter21 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter22 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter23 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter24 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter25 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter26 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter27 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter28 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter29 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter30 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter31 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter31 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcountinhibit with illegal instruction +00000000 +00000002 # U mode read from mcountinhibit with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent3 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent4 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent5 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent6 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent7 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent8 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent9 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent10 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent11 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent12 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent13 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent14 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent15 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent16 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent17 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent18 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent19 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent20 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent21 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent22 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent23 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent24 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent25 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent26 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent27 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent28 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent29 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent30 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent31 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent31 with illegal instruction +00000000 +00000bad +00000000 +00000008 # ecall from terminating tests in U mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output index 492379dee..b0f6ca4c7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output @@ -1,104 +1,104 @@ -0000000b +0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode 00000000 -beef0000 +beef0000 # 7 read test successes 0000dead -beef0055 +beef0055 # read 2 0880dead -beef0033 +beef0033 # read 3 0990dead -beef0077 +beef0077 # read 4 0110dead -beef0099 +beef0099 # read 5 0220dead -beef0440 +beef0440 # read 6 0330dead -beef0bb0 +beef0bb0 # read 7 0440dead -beef0000 +beef0000 # Test 12.3.1.1.4: 3 read test successes 0000dead -beef0055 +beef0055 # read 2 0880dead -beef0099 +beef0099 # read 3 0220dead -0000000d +0000000d # Test 12.3.1.2.1: 2 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.2: read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.2.3: write test with page fault 00000000 -0000000d +0000000d # Test 12.3.1.2.4: read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.5: 2 read tests with page faults 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -00000111 +00000111 # Test 12.3.1.3.1: execute test success 00000000 -00000009 +00000009 # ecall from going to U mode from S mode 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -beef0033 +beef0033 # Test 12.3.1.3.2: read test success 0990dead -00000008 +00000008 # ecall from going to S mode from U mode 00000000 -beef0077 +beef0077 # read test success 0110dead -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.3.3: read test with page fault 00000000 00000bad 00000000 -beef0440 +beef0440 # read test success 0330dead -beef0110 +beef0110 # Test 12.3.1.3.4: read test success 0440dead -0000000f +0000000f # write test with page fault 00000000 -0000000c +0000000c # Test 12.3.1.3.5: execute test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.6: write test with page fault 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.7: write test with page fault 00000000 -beef0bb0 +beef0bb0 # read test success 0440dead -00000009 +00000009 # ecall from test termination from S mode 00000000 -deadbeef +deadbeef # rest of the output space deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output index 68a13c253..1d4ff8e33 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output @@ -1,112 +1,112 @@ -0000000b +0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode 00000000 -beef0cc0 +beef0cc0 # 8 read test successes 0ee0dead -beef0000 +beef0000 # read 2 0000dead -beef0055 +beef0055 # read 3 0880dead -beef0033 +beef0033 # read 4 0990dead -beef0077 +beef0077 # read 5 0110dead -beef0099 +beef0099 # read 6 0220dead -beef0440 +beef0440 # read 7 0330dead -beef0bb0 +beef0bb0 # read 8 0440dead -beef0cc0 +beef0cc0 # Test 12.3.1.1.4: 4 read test successes 0ee0dead -beef0000 +beef0000 # read 2 0000dead -beef0055 +beef0055 # read 3 0880dead -beef0099 +beef0099 # read 4 0220dead -0000000d +0000000d # Test 12.3.1.2.1: 2 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.2: read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.2.3: write test with page fault 00000000 -0000000d +0000000d # Test 12.3.1.2.4: read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.5: 3 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # read 3 00000000 00000bad 00000000 -00000111 +00000111 # Test 12.3.1.3.1: Execute test success 00000000 -00000009 +00000009 # ecall from going to U mode from S mode 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -beef0033 +beef0033 # Test 12.3.1.3.2: read test success 0990dead -00000008 +00000008 # ecall from going to S mode from U mode 00000000 -beef0077 +beef0077 # read test success 0110dead -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read test with page fault` 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.3.3: read test with page fault 00000000 00000bad 00000000 -beef0440 +beef0440 # read test success 0330dead -beef0110 +beef0110 # Test 12.3.1.3.4: read test success 0440dead -0000000f +0000000f # write test with page fault 00000000 -0000000c +0000000c # Test 12.3.1.3.5: executable test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.6: write test with page fault 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.7: write test with page fault 00000000 -beef0bb0 +beef0bb0 # read test success 0440dead -00000009 +00000009 # ecall from test termination in S mode. 00000000 -deadbeef +deadbeef # rest of the output space deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output index 7ba4cff92..c8a68e8e2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output @@ -1,148 +1,148 @@ -beef00b4 -0000dead -beef00b5 +beef00b4 # Test 12.3.2.1: read 64 bits success in CLINT +0000dead # all of these read successes are also confirming successful writes +beef00b5 # read 32 bits success in CLINT (sign extended) ffffffff -000000b6 +000000b6 # read 16 bits success in CLINT 00000000 -ffffffb7 +ffffffb7 # read 8 bits success in CLINT (sign extended) ffffffff -00000001 +00000001 # execute test with access fault in CLINT 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 64 bits with access fault in PLIC 00000000 00000bad 00000000 -00000002 +00000002 # read 32 bits success in PLIC (confriming 32 bit write) 00000000 -00000007 +00000007 # write 16 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 16 bits with access fault in PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write 8 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 8 bits with access fault in PLIC 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in UART 00000000 -00000005 +00000005 # read 64 bits with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 32 bits with access fault in UART 00000000 -00000005 +00000005 # read 32 bits with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 16 bits with access fault in UART 00000000 -00000005 +00000005 # read 16 bits with access fault in UART 00000000 00000bad 00000000 -ffffffbf +ffffffbf # read 8 bits success in UART (confirming 8 bit write) ffffffff -00000001 +00000001 # execute test with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 64 bits with access fault in GPIO 00000000 00000bad 00000000 -beef00c1 +beef00c1 # read 32 bits success in GPIO (confirming 32 bit write) ffffffff -00000007 +00000007 # write 16 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 16 bits with access fault in GPIO 00000000 00000bad 00000000 -00000007 +00000007 # write 8 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 8 bits with access fault in GPIO 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in GPIO 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault in random memory location 00000000 -00000005 +00000005 # read test with access fault in random memory location 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in random memory location 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after BOOTROM 00000000 -00000005 +00000005 # read test with access fault just after BOOTROM 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after BOOTROM 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after CLINT 00000000 -00000005 +00000005 # read test with access fault just after CLINT 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after CLINT 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after PLIC 00000000 -00000005 +00000005 # read test with access fault just after PLIC 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after UART 00000000 -00000005 +00000005 # read test with access fault just after UART 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after UART 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after GPIO 00000000 -00000005 +00000005 # read test with access fault just after GPIO 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after GPIO 00000000 00000bad 00000000 -0000000b +0000000b # ecall from terminating tests in M mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output index 931f8a160..ea5a0cb18 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output @@ -1,58 +1,58 @@ -0fffffff +0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 +00000000 +20040000 # writeback of value written to PMPADDR1 00000000 -20040000 +2004003f # writeback of value written to PMPADDR2 00000000 -2004003f +20040080 # writeback of value written to PMPADDR3 00000000 -20040080 +20040084 # writeback of value written to PMPADDR4 00000000 -20040084 +200400c0 # writeback of value written to PMPADDR5 00000000 -200400c0 +2004013f # writeback of value written to PMPADDR6 00000000 -2004013f +2fffffff # writeback of value written to PMPADDR15 00000000 -2fffffff -00000000 -0009001f +0009001f # writeback of value written to PMPCFG0 0018900c -00000000 +00000000 # writeback of value written to PMPCFG2 1f000000 -0009001f +0009001f # old value of PMPCFG0 after failed write to locked out region 0018900c -200400c0 +200400c0 # old value of PMPADDR5 after failed write to locked out region 00000000 -00000005 +00000005 # Test 12.3.2.2.2: read test with access fault to region with L=1, R=0 00000000 00000bad 00000000 -00600dbb +00600dbb # read test success from region with L=X=W=R=0 00000000 -0000000b +0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode 00000000 -00600d15 +00600d15 # read test success from RW range (confirming previous write) 00000000 -00600d02 +00600d02 # read test success from outside the edge of a read only range 00000000 -00600d12 +00600d12 # read test success from outside the other edge of a read only range 00000000 -00000007 +00000007 # write test with access fault in read only range 00000000 -00600daa +00600daa # read success from read only range 00000000 -00000007 +00000007 # write test with access fault in no-access range 00000000 -00000005 +00000005 # read test with access fault in no-access range 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in no-execute range 00000000 00000bad 00000000 -00000111 +00000111 # execute sucess when X=1 00000000 -00000009 +00000009 # ecall from terminating tests in S mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output index 880d5dc82..e37c37626 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output @@ -1,20 +1,20 @@ -00000002 +00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mvendorid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of marchid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mimpid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mhartid 00000000 -0000000b +0000000b # ecall from terminating tests in M mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S new file mode 100644 index 000000000..ce1069834 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S @@ -0,0 +1,153 @@ +/////////////////////////////////////////// +// +// WALLY-CSR-permissions +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-MACROS-64.h" + +INIT_TESTS + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. + +# *** several of these appear not to be implemented in the assembler? +# I get "assembler messages: error: unkown CSR" with many of them. + +goto_s_mode 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# Machine information Registers +write_read_csr mvendorid, 0xbad +write_read_csr marchid, 0xbad +write_read_csr mimpid, 0xbad +write_read_csr mhartid, 0xbad +# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +write_read_csr mstatus, 0xbad +write_read_csr misa, 0xbad +write_read_csr medeleg, 0xbad +write_read_csr mideleg, 0xbad +write_read_csr mie, 0xbad +write_read_csr mtvec, 0xbad +write_read_csr mcounteren, 0xbad + +# Machine Trap Handling +write_read_csr mscratch, 0xbad +write_read_csr mepc, 0xbad +write_read_csr mcause, 0xbad +write_read_csr mtval, 0xbad +write_read_csr mip, 0xbad +# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mtval2, 0xbad + +# Machine Configuration +# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mseccgf, 0xbad + +# Machine Memory Protection +write_read_csr pmpcfg0, 0xbad +write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs + +write_read_csr pmpaddr0, 0xbad +write_read_csr pmpaddr1, 0xbad +write_read_csr pmpaddr2, 0xbad +write_read_csr pmpaddr3, 0xbad +write_read_csr pmpaddr4, 0xbad +write_read_csr pmpaddr5, 0xbad +write_read_csr pmpaddr6, 0xbad +write_read_csr pmpaddr7, 0xbad +write_read_csr pmpaddr8, 0xbad +write_read_csr pmpaddr9, 0xbad +write_read_csr pmpaddr10, 0xbad +write_read_csr pmpaddr11, 0xbad +write_read_csr pmpaddr12, 0xbad +write_read_csr pmpaddr13, 0xbad +write_read_csr pmpaddr14, 0xbad +write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +write_read_csr mcycle, 0xbad +write_read_csr minstret, 0xbad +write_read_csr mhpmcounter3, 0xbad +write_read_csr mhpmcounter4, 0xbad +write_read_csr mhpmcounter5, 0xbad +write_read_csr mhpmcounter6, 0xbad +write_read_csr mhpmcounter7, 0xbad +write_read_csr mhpmcounter8, 0xbad +write_read_csr mhpmcounter9, 0xbad +write_read_csr mhpmcounter10, 0xbad +write_read_csr mhpmcounter11, 0xbad +write_read_csr mhpmcounter12, 0xbad +write_read_csr mhpmcounter13, 0xbad +write_read_csr mhpmcounter14, 0xbad +write_read_csr mhpmcounter15, 0xbad +write_read_csr mhpmcounter16, 0xbad +write_read_csr mhpmcounter17, 0xbad +write_read_csr mhpmcounter18, 0xbad +write_read_csr mhpmcounter19, 0xbad +write_read_csr mhpmcounter20, 0xbad +write_read_csr mhpmcounter21, 0xbad +write_read_csr mhpmcounter22, 0xbad +write_read_csr mhpmcounter23, 0xbad +write_read_csr mhpmcounter24, 0xbad +write_read_csr mhpmcounter25, 0xbad +write_read_csr mhpmcounter26, 0xbad +write_read_csr mhpmcounter27, 0xbad +write_read_csr mhpmcounter28, 0xbad +write_read_csr mhpmcounter29, 0xbad +write_read_csr mhpmcounter30, 0xbad +write_read_csr mhpmcounter31, 0xbad + +# Machine Counter Setup +write_read_csr mcountinhibit, 0xbad +write_read_csr mhpmevent3, 0xbad +write_read_csr mhpmevent4, 0xbad +write_read_csr mhpmevent5, 0xbad +write_read_csr mhpmevent6, 0xbad +write_read_csr mhpmevent7, 0xbad +write_read_csr mhpmevent8, 0xbad +write_read_csr mhpmevent9, 0xbad +write_read_csr mhpmevent10, 0xbad +write_read_csr mhpmevent11, 0xbad +write_read_csr mhpmevent12, 0xbad +write_read_csr mhpmevent13, 0xbad +write_read_csr mhpmevent14, 0xbad +write_read_csr mhpmevent15, 0xbad +write_read_csr mhpmevent16, 0xbad +write_read_csr mhpmevent17, 0xbad +write_read_csr mhpmevent18, 0xbad +write_read_csr mhpmevent19, 0xbad +write_read_csr mhpmevent20, 0xbad +write_read_csr mhpmevent21, 0xbad +write_read_csr mhpmevent22, 0xbad +write_read_csr mhpmevent23, 0xbad +write_read_csr mhpmevent24, 0xbad +write_read_csr mhpmevent25, 0xbad +write_read_csr mhpmevent26, 0xbad +write_read_csr mhpmevent27, 0xbad +write_read_csr mhpmevent28, 0xbad +write_read_csr mhpmevent29, 0xbad +write_read_csr mhpmevent30, 0xbad +write_read_csr mhpmevent31, 0xbad + +END_TESTS \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S new file mode 100644 index 000000000..d7984d7f6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -0,0 +1,169 @@ +/////////////////////////////////////////// +// +// WALLY-CSR-permissions +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-MACROS-64.h" + +INIT_TESTS + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. + +goto_u_mode 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# Supervisor Trap Setup +write_read_csr sstatus, 0xbad +write_read_csr sie, 0xbad +write_read_csr stvec, 0xbad +write_read_csr scounteren, 0xbad + +# Supervisor Configuration +# write_read_csr senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? + +# Supervisor Trap Handling +write_read_csr sscratch, 0xbad +write_read_csr sepc, 0xbad +write_read_csr scause, 0xbad +write_read_csr stval, 0xbad +write_read_csr sip, 0xbad + +# Supervisor Protection and Translation +write_read_csr satp, 0xbad + +# Machine information Registers +write_read_csr mvendorid, 0xbad +write_read_csr marchid, 0xbad +write_read_csr mimpid, 0xbad +write_read_csr mhartid, 0xbad +# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +write_read_csr mstatus, 0xbad +write_read_csr misa, 0xbad +write_read_csr medeleg, 0xbad +write_read_csr mideleg, 0xbad +write_read_csr mie, 0xbad +write_read_csr mtvec, 0xbad +write_read_csr mcounteren, 0xbad + +# Machine Trap Handling +write_read_csr mscratch, 0xbad +write_read_csr mepc, 0xbad +write_read_csr mcause, 0xbad +write_read_csr mtval, 0xbad +write_read_csr mip, 0xbad +# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mtval2, 0xbad + +# Machine Configuration +# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mseccgf, 0xbad + +# Machine Memory Protection +write_read_csr pmpcfg0, 0xbad +write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs + +write_read_csr pmpaddr0, 0xbad +write_read_csr pmpaddr1, 0xbad +write_read_csr pmpaddr2, 0xbad +write_read_csr pmpaddr3, 0xbad +write_read_csr pmpaddr4, 0xbad +write_read_csr pmpaddr5, 0xbad +write_read_csr pmpaddr6, 0xbad +write_read_csr pmpaddr7, 0xbad +write_read_csr pmpaddr8, 0xbad +write_read_csr pmpaddr9, 0xbad +write_read_csr pmpaddr10, 0xbad +write_read_csr pmpaddr11, 0xbad +write_read_csr pmpaddr12, 0xbad +write_read_csr pmpaddr13, 0xbad +write_read_csr pmpaddr14, 0xbad +write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +write_read_csr mcycle, 0xbad +write_read_csr minstret, 0xbad +write_read_csr mhpmcounter3, 0xbad +write_read_csr mhpmcounter4, 0xbad +write_read_csr mhpmcounter5, 0xbad +write_read_csr mhpmcounter6, 0xbad +write_read_csr mhpmcounter7, 0xbad +write_read_csr mhpmcounter8, 0xbad +write_read_csr mhpmcounter9, 0xbad +write_read_csr mhpmcounter10, 0xbad +write_read_csr mhpmcounter11, 0xbad +write_read_csr mhpmcounter12, 0xbad +write_read_csr mhpmcounter13, 0xbad +write_read_csr mhpmcounter14, 0xbad +write_read_csr mhpmcounter15, 0xbad +write_read_csr mhpmcounter16, 0xbad +write_read_csr mhpmcounter17, 0xbad +write_read_csr mhpmcounter18, 0xbad +write_read_csr mhpmcounter19, 0xbad +write_read_csr mhpmcounter20, 0xbad +write_read_csr mhpmcounter21, 0xbad +write_read_csr mhpmcounter22, 0xbad +write_read_csr mhpmcounter23, 0xbad +write_read_csr mhpmcounter24, 0xbad +write_read_csr mhpmcounter25, 0xbad +write_read_csr mhpmcounter26, 0xbad +write_read_csr mhpmcounter27, 0xbad +write_read_csr mhpmcounter28, 0xbad +write_read_csr mhpmcounter29, 0xbad +write_read_csr mhpmcounter30, 0xbad +write_read_csr mhpmcounter31, 0xbad + +# Machine Counter Setup +write_read_csr mcountinhibit, 0xbad +write_read_csr mhpmevent3, 0xbad +write_read_csr mhpmevent4, 0xbad +write_read_csr mhpmevent5, 0xbad +write_read_csr mhpmevent6, 0xbad +write_read_csr mhpmevent7, 0xbad +write_read_csr mhpmevent8, 0xbad +write_read_csr mhpmevent9, 0xbad +write_read_csr mhpmevent10, 0xbad +write_read_csr mhpmevent11, 0xbad +write_read_csr mhpmevent12, 0xbad +write_read_csr mhpmevent13, 0xbad +write_read_csr mhpmevent14, 0xbad +write_read_csr mhpmevent15, 0xbad +write_read_csr mhpmevent16, 0xbad +write_read_csr mhpmevent17, 0xbad +write_read_csr mhpmevent18, 0xbad +write_read_csr mhpmevent19, 0xbad +write_read_csr mhpmevent20, 0xbad +write_read_csr mhpmevent21, 0xbad +write_read_csr mhpmevent22, 0xbad +write_read_csr mhpmevent23, 0xbad +write_read_csr mhpmevent24, 0xbad +write_read_csr mhpmevent25, 0xbad +write_read_csr mhpmevent26, 0xbad +write_read_csr mhpmevent27, 0xbad +write_read_csr mhpmevent28, 0xbad +write_read_csr mhpmevent29, 0xbad +write_read_csr mhpmevent30, 0xbad +write_read_csr mhpmevent31, 0xbad + +END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S index 226c93984..5c894081c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S @@ -72,7 +72,7 @@ .8byte 0x0, 0x0018FF0C0009001F, write_pmpcfg_0 # attempt to edit only pmp5cfg (pmpcfg0[47:40]) after lockout. # instruction ignored, output is 0x0018900C0009001F, NOT 0x0018FF0C0009001F .8byte 0x5, 0xFFFFFFFF, write_pmpaddr_5 # attempt to edit pmpaddr5 after lockout. -# instruction ignored, output is 0x80100300, NOT 0xFFFFFFFF +# instruction ignored, output is 0x200400c0, NOT 0xFFFFFFFF # Test 12.3.2.2.2 Machine mode access diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h index a044f737c..de54815e8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h @@ -279,29 +279,28 @@ begin_test: // label here to jump to so we dont go through the trap handler befo // Test Summary table! -// Test Name : Description : Fault output value : Normal output values -// ---------------------:-------------------------------------------:-------------------------------:------------------------------------------------------ -// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None -// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None -// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None -// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None -// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) -// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_baremetal : satp.MODE = bare metal : None : None -// goto_sv39 : satp.MODE = sv39 : None : None -// goto_sv48 : satp.MODE = sv48 : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// write_csr : write to specified CSR : CSR value before test attempt : value written to CSR -// read_csr : read from specified CSR : *** None? Mcause or fault? : value read back from CSR +// Test Name : Description : Fault output value : Normal output values +// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------ +// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None +// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None +// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None +// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None +// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) +// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_baremetal : satp.MODE = bare metal : None : None +// goto_sv39 : satp.MODE = sv39 : None : None +// goto_sv48 : satp.MODE = sv48 : None : None +// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR +// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11 - -// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value +// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value .macro write64_test ADDR VAL // attempt to write VAL to ADDR @@ -452,13 +451,14 @@ begin_test: // label here to jump to so we dont go through the trap handler befo sfence.vma x0, x0 // *** flushes global pte's as well .endm -.macro write_csr CSR VAL - // attempt to write CSR with VAL *** ASSUMES RW access to CSR in whatever privilege mode is running +.macro write_read_csr CSR VAL + // attempt to write CSR with VAL. Note: this also tests read access to CSR // Success outputs: // value read back out from CSR after writing // Fault outputs: // The previous CSR value before write attempt - // *** Is there an associated mstatus? maybe 0x2??? + // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + li x30, 0xbad // load bad value to be overwritten by csrr li x29, \VAL csrw \CSR\(), x29 csrr x30, \CSR @@ -478,9 +478,9 @@ begin_test: // label here to jump to so we dont go through the trap handler befo csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR csrr x30, \CSR bne x30, x29, 1f // 1f represents write_access - li x30, 0x11 // Write succeeded, violating read only permissions. + li x30, 0x11 // Write failed, confirming read only permissions. j 2f // j r_access_end -1: // w_access (test failed) +1: // w_access (write succeeded, violating read-only) li x30, 0xBAD 2: // r_access end sd x30, 0(x6) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index 2367a32bb..695c75222 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -25,7 +25,7 @@ INIT_TESTS -// Test 5.2.3.1: tersting Read-only access to Machine info CSRs +// Test 5.2.3.1: testing Read-only access to Machine info CSRs csr_r_access mvendorid csr_r_access marchid diff --git a/tests/wally-riscv-arch-test/spec/TestFormatSpec.adoc b/tests/wally-riscv-arch-test/spec/TestFormatSpec.adoc deleted file mode 100644 index ec67dabae..000000000 --- a/tests/wally-riscv-arch-test/spec/TestFormatSpec.adoc +++ /dev/null @@ -1,606 +0,0 @@ -= RISC-V Architecture Test Format Specification = -RISC-V Foundation Architecture Test SIG -Issue 1.2.6 Draft -:toc: -:icons: font -:numbered: -:source-highlighter: rouge - -//// -SPDX-License-Identifier: CC-BY-4.0 - -Document conventions: -- one line per paragraph (don't fill lines - this makes changes clearer) -- Wikipedia heading conventions (First word only capitalized) -- US spelling throughout. -- Run "make spell" before committing changes. -- Build the HTML and commit it with any changed source. -- Do not commit the PDF! -//// - -== Introduction -=== About - -This document contains the RISC-V <> structure and <> format specification which shall be used as a reference document for those who write or are going to write tests for the RISC-V architectural test pool and for those who are going to use the <> in their own architectural test framework. - -* It includes, as example, source code listing and detailed description of one <> - -Framework specification which includes description of how the <> are built and used for the appropriate RISC-V configurations is given in the complementary Framework Specification document. This document is made freely available under a <>. - - -=== Intended audience - -This document is intended for design and verification engineers who wish to develop new architectural tests and also for those who wish to write or adapt their own test framework. - -=== Future work - -This is a draft document; it partially documents what exists, and partially documents the longer-term goal. -As such, this document still under review and its content will change. -Its primary aim is to get a long-term stable version of the spec and to give test authors sufficient lead time to prepare test authoring tools and strategies. - -=== Contributors - -This document has been created by the following people (in alphabetical order of surname). - - -* Allen Baum -* Jeremy Bennett -* Radek Hajek -* Premysl Vaclavik - -=== Document history -[cols="<1,<2,<3,<4",options="header,pagewidth",] -|================================================================================ -| _Revision_ | _Date_ | _Author_ | _Modification_ - -| 1.2.6 Draft | 24 September 2020 | Neel Gala | Replaced Compliance with Architecture/Architectural. Minor beautification in macro definitions. - -| 1.2.5 Draft | 22 Jan 2020 | - -Allen Baum | - - * removed references to test pool reference doc, mentioned that the framework will generate it - * clarified that macros defined in a test may be used in a test - * minor clarifications, consistency changes, added page breaks - -| 1.2.4 Draft | 08 Jan 2020 | - -Allen Baum | - - * typos fixed - * added RVTEST_BASEUPD macro - * added explanations for each macro - * clarified restrictions on #ifdefs - * added comment that test cases with identical conditions should be combined into a single case - * documented that test case first parameter should match the #ifdef parameter that precedes it - -| 1.2.3 Draft | 02 Dec 2019 | - -Allen Baum | - - * modified macro names to conformn to riscof naming convention of model specific vs. pre-defined - * add more complete list of macros, their uses, parameters, and whether they are required or optional - * minor structural changes (moving sentences, renumbering) and typo fixes - * clarified impact of debug macros - * clarified how SIGUPD and BASEUPD must be used, fixed parameter description - -| 1.2.2 Draft | 21 Nov 2019 | - -Allen Baum | - - * remove section about test taxonomy, binary tests, emulated ops - * clarify/fix boundary between test target and framework responsibilities - (split test target into test target and test shell) - * remove To Be discussed items that have been discussed - * remove default case condition; if conditions are unchaged, part of same case - * minor grammatical changes related to the above - -| 1.2.1 Draft | 19 Nov 2019 | - -Allen Baum | - - * spec/TestFormatSpec.adoc: changed the format of the signature to fixed 32b data size only extracted from COMPLIANCE_DATA_BEGIN/END range. - * made test suite subdirectories upper case, with sub-extensions camel case - * updated example to match most recent riscof implement macros - * fix format so Appendix is now in TOC - * moved note about multiple test cases in a test closer to definition - * fixed cut/paste error in example of test pool - * more gramatical fixes, clarifications added - * added To Be Discussed items regarding emulated instruction and binary tests - * added graphic of test suite/test_pool/test/test_case hierarchy - - -| 1.2.1 Draft | 12 Oct 2019 | - -Allen Baum | - -minor grammar, wording, syntax corrections, added detail and clarification from suggestions by Paul Donahue - -| 1.2 Draft | 12 Sep 2019 | - -Allen Baum | - -minor grammar, wording, syntax corrections, added detail and clarification -Added detail regarding the 2 approaches for test selection: central database, or embedded conditions embedded in macros -Added detail of proposed standard macros RVTEST_SIGBASE, RVTEST_SIGUPD, RVTEST_CASE -More explanation of spec status in initial _future work_ paragraph (i.e. goal, not yet accomplished) -Removed many "to Be Discussed items and made them official -Removed options, made POR for test selection and standard macros RVTEST_SIGBASE, RVTEST_SIGUPD, RVTEST_CASE -Removed prohibition on absolute addresses -Clarified which test suites a test should be in where they are dependent on multiple extensions -Clarified use of includes and macros (and documented exsiting deviations) -Clarified use of YAML files -Added detail to description and uses of common compliance test pool reference document - -| 1.1 Draft | 15 Feb 2019 | - -Radek Hajek | - -Appendix A: example assertions update - -| 1.0 Draft | 10 Dec 2018 | - -Radek Hajek, Premysl Vaclavik | - -First version of the document under this file name. Document may contain some segments of the README.adoc from the compatibility reasons. - -|================================================================================ -<<< -== Foreword -The architectural test pool shall become a complete set of architectural tests which will allow developers to build an architectural test suite for any legal RISC-V configuration. The architectural tests will be very likely written by various authors and therefore it is very important to define the architectural test pool structure and architectural test form, which will be obligatory for all tests. Unification of tests will guarantee optimal architectural test pool management and also better quality and readability of the tests. Last but not least, it will simplify the process of adding new tests into the existing architectural test pool and the formal revision process. - -== Vocabulary -=== The architectural test -The architectural test is a nonfunctional testing technique which is done to validate whether the system developed meets the prescribed standard or not. In this particular case the golden reference is the RISC-V ISA standard. - -For purpose of this document we understand that the architectural test is a single test which represents the minimum test code that can be compiled and run. It is written in assembler code and its product is a <>. A architectural test may consist of several <>. - -=== The RISC-V architectural test pool -The RISC-V architectural test pool consists of all approved <> that can be assembled by the test framework, forming the <>. The RISC-V architectural test pool must be test target independent (so, should correctly run on any compliant target). Note that this nonfunctional testing is not a substitute for verification or device test. - -=== The RISC-V architectural test suite -The RISC-V architectural test suite is a group of tests selected from the <> to test adherence for the specific RISC-V configuration. Test results are obtained in the form of a <>. Selection of tests is performed based on the target's asserted configuration, and the spec, Execution Environment or platform requirements. Compliant processor or processor models shall exhibit the same test suite signature as the golden reference test suite signature for the specific configuration being tested. - -=== The test case -A _test case_ is part of the architectural test that tests just one feature of the specification. - ----- -Note: a single test can contain multiple test cases, each of which can have its own test inclusion condition (as defined by the cond_str parameter of the RVTEST_CASE macro. ----- - -[#img-testStruct] -.Test Suite, Test_Pool, Test, Test_Case relationship -image::./testpool.jpg[testStruct] - -=== The test case signature -The _test case signature_ is represented by single or multiple values. Values are written to memory at the address starting at the address specified by the RVMODEL_DATA_BEGIN and ending at RVMODEL_DATA_END. Signatures can be generated most easily using the RVTEST_SIGUPD macro. - -=== The test signature -The <> is a characteristic value which is generated by the architectural test run. The <> may consist of several <>, prefixed with a separate line containing the name of the test and a unique value indicating its version (e.g. git checkin hash). The test target is responsible for extracting values from memory and properly formatting them, using metadata provided to it by the framework using the RVMODEL_DATA_BEGIN and RVMODEL_DATA_END macros. Test case signature values are written one per line, starting with the most-significant byte on the left-hand side with the format where the length of value will be 32 bits (so 8 characters), regardless of the actual value length computed by the test. Furthermore, the signature should always begin at a 16-byte (128-bit) boundary and the size of the signature should be a multiple of 16-bytes (i.e. it should also end at a 16-byte boundary). - -=== The test suite signature -The _test suite signature_ is defined as a set of <> valid for given <>. It represents the test signature of the particular RISC-V configuration selected for the architectural test. - -=== The target shell -The <> is the software and hardware environment around the <> that enables it to communicate with the framework, including assembling and linking tests, loading tests into memory, executing tests, and extracting the signature. The input to the <> is a .S <> file, and the output is a <>. - -=== The test target -The <> can be either a RISC-V Instruction Set Simulator (ISS), a RISC-V emulator, a RISC-V RTL model running on an HDL simulator, a RISC-V FPGA implementation or a physical chip. Each of the target types offers specific features and represents specific interface challenges. It is a role of the <> to handle different targets while using the same <> as a test source. - -=== The RISC-V processor (device) configuration -The RISC-V ISA specification allows many optional instructions, registers, and other features. Production directed targets typically have a fixed subset of available options. A simulator, on the other hand, may implement all known options which may be constrained to mimic the behavior of the RISC-V processor with the particular configuration. It is a role of the Architectural Test Framework to build and use the <> suitable for the selected RISC-V configuration. - - -=== The architectural test framework -The <> selects and configures the <> from the <> for the selected <> based on both the specific architectural choices made by an implementation and those required by the Execution Environment It causes the <> to build, execute, and report a signature. The <> then compares reported signatures, inserts test part names and version numbers and summarizes differences (or lack of them) into a RISC-V test report. The primary role of the well-defined <> structure is to provide the tests in a form suitable for the Architectural Test Framework selection engine. - -<<< -== Architectural test pool -=== Test pool structure - -The structure of <> in the <> shall be based on defined RISC-V extensions and privileged mode selection. This will provide a good overview of which parts of the ISA specification are already covered in the <>, and which tests are suitable for certain configurations. The architectural test pool has this structure: - ----- -architectural-tests-suite (root) -|-- _/, where - is [ RV32I | RV64I | RV32E ] - is [ M | MU | MS | MSU ], where - M Machine mode tests - tests execute in M-mode only - MU Machine/User mode tests - tests execute in both M- & U-modes (S-mode may exist) - MS Machine/Supv mode tests - tests execute in both M- & S-modes (not U-mode) - MSU All mode tests - tests execute in all of M-, S-, & U-Modes - are the lettered extension [A | B | C | M ...] or subextension [Zifencei | Zam | ...] when the tests involve extensions, or more general names when tests cut across extension definitionss (e.g. Priv, Interrupt, Vm). The feature string consists of an initial capital letter, followed by any further letters in lower case. - ----- - -Note that this structure is for organizational purposes, not functional purposes, although full test names will take advantage of it. - -Tests that will be executed in different modes, even if the results are identical, should be replicated in each mode directory, e.g. RV32I_M/, RV32I_MS/, and RV32I_MU/. These tests are typically those involving trapping behavior, e.g load, store, and privilged ops. - -=== Test naming - -The naming convention of a single test: - -<__test objective__>-<__test number__>.S - -* __test objective__ – an aspect that the test is focused on. A test objective may be an instruction for ISA tests (ADD, SUB, ...), or a characteristic covering multiple instructions, e.g. exception event (misaligned fetch, misalign load/store) and others. - -* __test number__ – number of the test. It is expected that multiple tests may be specified for one test objective. We recommend to break down complex tests into a set of small tests. A simple rule of thumb is one simple test objective = one simple test. The code becomes more readable and the test of the objective can be improved just by adding <>. The typical example are instruction tests for the F extension. - -* A test name shall not include an ISA category as part of its name (i.e. the directory, subdirectory names). + -Experience has shown that including ISA category in the test name leads to very long test names. Instead, we have introduced the <> where the full name is composed of the test path in the <> and the simple test name. + -Since full names can be reconstructed easily it is not necessary to include the path in test names. - -=== Assembly macros and test labels - -There are both pre-defined and model-specific macros which shall be used in every test to guarantee -their portability. In addition, there are both pre-defined and model specific macros that are not required, -but may be used in tests for either convenience or debugging purposes. - -==== *Required, Pre-defined Macros* - -These macros are be defined in the file **compilance_test.h** by the author of the test. A -significant amount of the framework shall depend on the existence of these macros. - - `RVTEST_ISA(isa_str)`:: - - - defines the Test Virtual Machine (TVM, the ISA being tested) + - - empty macro to specify the isa required for compilation of the test. + - - this is mandated to be present at the start of the test. - - - `RVTEST_CODE_BEGIN`:: - - start of code (test) section - - macro to indicate test code start add and where test startup routine is inserted. + - - no part of the test-code section should precede this macro - - this macro includes an initialization routine which pre-loads all the GPRs with unique values - (not `0xdeadbeef`). Register t0 and t1 are initialized to point to the labels : - `rvtest_code_begin` and `rvtest_code_end` respectively. - - the macros contains a label `rvtest_code_begin` after the above initilization routine to mark - the begining of the actual test. - - `RVTEST_CODE_END`:: - - end of code (test) section + - - macro to indicate test code end. + - - no part of the test-code section should follow after this macro. - - the macro enforces a 16-byte boundary alignment - - the macro also inlcudes the label `rvtest_code_end` which marks the end of the actual test. - - if trap handling is enabled, this macro contains the entire trap handler code required by the - test. - - `RVTEST_DATA_BEGIN`:: - - marks the begining of the test data section + - - used to provided initialized data regions to be used by the test + - - this region starts at a 16-byte boundary + - - the start of this is macro can be addressed using the label: `rvtest_data_begin` - - when trap handling is enabled, this macro also includes the following labels : - . trapreg_sv: This region is used to save the temporary registers used in the trap-handler - code - . tramptbl_sv: This region is used to save the contents of the test-target's initial - code-section which is overwritten with the necessary trampoline table. - . mtvec_save: a double-word region to save the test-target specific mtvec register - . mscratch_save: a double-word region to save the test-target specific mscratch register - - `RVTEST_DATA_END`:: - - this macros marks the end of the test input data section. - - the start of this macro can be addressed using the label: `rvtest_data_end` - - `RVTEST_CASE(CaseName, CondStr)`:: - - execute this case only if condition in cond_str are met + - - caseName is arbitrary string + - - condStr is evaluated to determine if the test-case is enabled and sets name variable + - - condStr can also define compile time macros required for the test-case to be enabled. + - - the test-case must be delimited with an #ifdef CaseName/#endif pair + - - the format of CondStr can be found in https://riscof.readthedocs.io/en/latest/cond_spec.html#cond-spec - -==== *Required, Model-defined Macros* - -These macros are be defined by the owner of the test target in the file **model_test.h**. -These macros are required to define the signature regions and also the logic required to halt/exit -the test. - - `RVMODEL_DATA_BEGIN`:: - - This macro marks the start of signature regions. The test-target should use this macro to create a label to indicate the begining of the signature region. For example : `.globl begin_signature; begin_signature`. This macro must also begin at a 16-byte boundary and must not include anything else. - - `RVMODEL_DATA_END`:: - - This macros marks the end of the signature-region. The test-target must declare any labels required to indicate the end of the signature region. For example : `.globl end_signature; end_signature`. This label must be at a 16-byte boundary. The entire signature region must be included within the RVMODEL_DATA_BEGIN macro and the start of the RVMODEL_DATA_END macro. The RVMODEL_DATA_END macro can also contain other target specific data regions and initializations but only after the end of the signature. - - `RVMODEL_HALT`:: - - This macros must define the test-target halt mechanism. This macro is called when the test is - to be terminated either due to completion or dur to unsupported behavior. This macro could - also include routines to dump the signature region to a file on the host system which can be - used for comparison. - -==== *Optional, Pre-defined Macros* - - `RVTEST_SIGBASE(BaseReg,Val)`:: - - defines the base register used to update signature values + - - Register BaseReg is loaded with value Val + - - hidden_offset is initialized to zero - - `RVTEST_SIGUPD(BaseReg, SigReg [, Offset])`:: - - if Offset is present in the arguments, hidden_offset if set to Offset + - - Sigreg is stored at hidden_offset[BaseReg] - - hidden_offset is post incremented so repeated uses store signature values sequentially - - `RVTEST_BASEUPD(BaseReg[oldBase[,newOff]])`:: - - [moves &] updates BaseReg past stored signature + - - Register BaseReg is loaded with the oldReg+newOff+hidden_offset + - - BaseReg is used if oldBase isn't specified; 0 is used if newOff isn't specified + - - hidden_offset is re-initialized to 0 afterwards - - `RVTEST_SIGUPD_F(BaseReg, SigReg, FlagReg [, Offset])`:: - - This macro is used for RV32F and RV64D (where XLEN==FLEN). - - if Offset is present in the arguments, hidden_offset if set to Offset+(XLEN*2) + - - SigReg is stored at hidden_offset[BaseReg] - - FlagReg is stored at hidden_offset+XLEN[BaseReg] - - hidden_offset is post incremented so repeated uses store signature values sequentially - -==== *Optional, Model-defined Macros* - - `RVMODEL_BOOT`:: - - contains boot code for the test-target; may include emulation code or trap stub. If the - test-target enforces alignment or value restrictions on the mtvec csr, it is required that - this macro sets the value of mtvec to a region which is readable and writable by the machine - mode. May include code to copy the data sections from boot device to ram. Or any other code - that needs to be run prior to running the tests. - - `RVMODEL_IO_INIT`:: - - initializes IO for debug output - - this must be invoked if any of the other RV_MODEL_IO_* macros are used - -// `RVMODEL_IO_CHECK` -// - checks IO for debug output -// - - - `RVMODEL_IO_ASSERT_GPR_EQ(ScrReg, Reg, Value)`:: - - debug assertion that GPR should have value + - - outputs a debug message if Reg!=Value + - - ScrReg is a scratch register used by the output routine; its final value cannot be guaranteed - - Can be used to help debug what tests have passed/failed - - `RVMODEL_IO_WRITE_STR(ScrReg, String)`:: - - output debug string, using a scratch register + - - outputs the message String - - ScrReg is a scratch register used by the output routine; its final value cannot be guaranteed - - `RVMODEL_SET_MSW_INT`:: - - This macro needs to include a routine to set the machine software interrupt. - - Currently the test forces an empty macro if a target does not declare this. Future tests may - change this. - - `RVMODEL_CLEAR_MSW_INT`:: - - This macro needs to include a routine to clear the machine software interrupt. - - Currently the test forces an empty macro if a target does not declare this. Future tests may - change this. - - `RVMODEL_CLEAR_MTIMER_INT`:: - - This macro needs to include a routine to clear the machine timer interrupt. - - Currently the test forces an empty macro if a target does not declare this. Future tests may - change this. - - `RVMODEL_CLEAR_MEXT_INT`:: - - This macro needs to include a routine to clear the machine external interrupt. - - Currently the test forces an empty macro if a target does not declare this. Future tests may - change this. - -=== Required labels - -The test must define a `rvtest_entry_point` label to indicate the location to be used by the linker -as the entry point in the test. Generally, this would be before the `RVMODEL_BOOT` macro and should -belong to the `text.init` section. - -=== The test structure of an architectural test - -All tests shall use a signature approach. Each test shall be written in the same style, with defined mandatory items. -The test structure of an architectural test shall have the following sections in the order as follows: - -. Header + license (including a specification link, a brief test description and RVTEST_ISA macro)). -. Includes of header files (see Common Header Files section). -. Test Virtual Machine (TVM) specification, -. Test code between “RVTEST_CODE_BEGIN” and “RVTEST_CODE_END”. -. Input data section, marked with "RVTEST_DATA_BEGIN" and "RVTEST_DATA_END". -. Output data section between “RVMODEL_DATA_BEGIN” and “RVMODEL_DATA_END”. - - -Note:: Note that there is no requirement that the code or scratch data sections must be contiguous -in memory, or that they be located before or after data or code sections -(configured by embedded directives recognized by the linker) - -==== Common test format rules - -There are the following common rules that shall be applied to each <>: - -. Always use “//” as commentary. “#” should be used only for includes and defines. -. As part of the initialization code, all GPRs are preloaded with unique predefined values (which is -not `0xdeadbeef`). However, t0 is initialized with `rvtest_code_begin` and t1 is initialized with -`rvtest_data_begin`. -. The signature section of every test is pre-loaded with the word `0xdeadbeef` -. The signature region should always begin at a 16-byte boundary -. A test shall be divided into logical blocks (<>) according to the test goals. Test cases are enclosed in an `#ifdef <__CaseName__>, #endif` pair and begin with the RVTEST_CASE(CaseName,CondStr) macro that specifies the test case name, and a string that defines the conditions under which that <> can be selected for assembly and execution. Those conditions will be collected and used to generate the database which in turn is used to select tests for inclusion in the test suite for this target. -. Tests should use the RVTEST_SIGBASE(BaseReg,Val) macro to define the GPR used as a pointer to the output signature area, and its initial value. It can be used multiple times within a test to reassign the output area or change the base register. This value will be used by the invocations of the RVTEST_SIGUPD macro. -. Tests should use the RVTEST_SIGUPD(BaseReg, SigReg, ScratchReg, Value) macro to store signature values using (only) the base register defined in the most recently encountered RVTEST_SIGBASE(BaseReg,Val) macro. Repeated uses will automatically have an increasing offset that is managed by the macro. -.. Uses of RVTEST_SIGUPD shall always be preceded sometime in the test case by RVTEST_SIGBASE. + -.. Tests that use SIGUPD inside a loop or in any section of code that will be repeated (e.g. traps) must use the BASEUPD macro between each loop iteration or repeated code to ensure static values of the base and offset don't overwrite older values. -. When macros are needed for debug purposes, only macros from _model_test.h_ shall be used. - Note that using this feature shall not affect the signature results of the test run. -. Test shall not include other tests (e.g. #include “../add.S”) to prevent non-complete tests, compilation issues, and problems with code maintenance. -. Tests and test cases shall be skipped if not required for a specific model test configuration based on test conditions defined in the RVTEST_CASE macro. Tests that are selected may be further configured using variables (e.g. XLEN) which are passed into the tests and used to compile them. In either case, those conditions and variables are derived from the YAML specification of the device and execution environment that are passed into the framework. The flow is to run an architectural test suite built by the <> from the <> to determine which tests and test cases to run. -. Tests shall not depend on tool specific features. For example, tests shall avoid usage of internal GCC macros (e..g. ____risc_xlen__), specific syntax (char 'a' instead of 'a) or simulator features (e.g. tohost) etc. -. A test will end by either jumping to or implicitly reaching the `RVTEST_CODE_END` macro (i.e. -rvtest_code_end label). The `RVTEST_CODE_END` macro is always followed by the `RVMODEL_HALT` macro. -. Macros defined outside of a test shall only be defined in specific predefined header files (see <> below), and once they are in use, they may be modified only if the function of all affected tests remains unchanged. -It is acceptable that macros use may lead to operand repetition (register X is used every time). -- The aim of this restriction is to have test code more readable and to avoid side effects which may occur when different contributors will include new <> or updates of existing ones in the <>. -This measure results from the negative experience, where the <> could be used just for one target while the architectural test code changes were necessary to have it also running for other targets. -. All contents of the signature region must always be initialized to `0xdeadbeef`. -. The result of no operation should be stored in the signature even though not register has -been altered. -. Pseudo ops other than `li` and `la` which can map to multiple standard instruction sequences - should not be used. -. The actual test-section of the assembly must always start with the `RVTEST_CODE_BEGIN` which contains a routine to initialize the registers to specific values. - -==== Common Header Files - -Each test shall include only the following header files: - -. _model_test.h_ – defines target-specific macros, both required and optional: (e.g. RVMODEL_xxx) -. _arch_test.h_ – defines pre-defined test macros both required and optional: (e.g. RVTEST_xxx) - -The inclusion of the _arch_test.h_ should always occur after the _model_test.h_ file. - -Important points to be noted regarding header files : - -. Adding new header files is forbidden in the test. It may lead to macro redefinition and compilation issues. -. Macros maybe defined and used inside a test, as they will not be defined and used outside that specific test. -// . Assertions will generate code that reports assertion failures (and optionally successes?) only if enabled by the framework. -// . In addition, the framework may collect the assertion values and save them as a signature output file if enabled by the framework. - -==== Framework Requirements - -The framework will import files that describe - -- the implemented, target-specific configuration parameters in YAML format - -- the required, platform-specific configuration parameters in YAML format - -The framework will generate intermediate files, including a Test Database YAML file that selects tests from the test pool to generate a test suite for the target. - -The framework will also invoke the <> as appropriate to cause tests to be built, loaded, executed, and results reported. - -The YAML files define both the values of those conditions and values that can be used by the framework to configure tests (e.g. format of WARL CSR fields). -Tests should not have #if, #ifdef, etc. for conditional assembly except those that surround RVMODEL_CASE macros -Instead, each of those should be a separate <> whose conditions are defined in - the common reference document entry for that test and test case number. - - -<<< -[appendix] - -== Example ISA test _add-01.S_ - -.1) Header to inlcude comments - ----- -#This assembly file tests the add instruction of the RISC-V I extension for the add covergroup. - ----- - -.2) Includes of header files - ----- -#include "model_test.h" -#include "arch_test.h" ----- - -.3) Set the TVM of the test - ----- - -RVTEST_ISA("RV32I") ----- - -.4) Test target specifc boot-code - ----- -RVMODEL_BOOT ----- - -.5) Start of GPR intialization routine and test code - ----- -RVTEST_CODE_BEGIN ----- - -.6) Define the RVTEST_CASE string and conditions - ----- -#ifdef TEST_CASE_1 - -// this test is meant for devices implementing rv32I extension and requires enabling the compile -// macro TEST_CASE_1. This test will contribute to the "add" coverage label. - -RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) ----- - -.7) Initialize pointer to the signature region - ----- -RVTEST_SIGBASE( x16,signature_x16_1) // x16 will point to signature_x16_1 label in the signature region ----- - -.8) Define the test cases - ----- -TEST_RR_OP(add, x9, x4, x6, 0x80000005, 0x80000000, 0x00000005, x16, 0, x24) -TEST_RR_OP(add, x5, x5, x14, 0xfffffeff, 0x00000000, 0xfffffeff, x16, 4, x24) -... -... - ----- - -.9) Change signature base register - ----- -// this will change the signature base register to x3. x3 will not point to signature_x3_0 in -// the signature region -RVTEST_SIGBASE( x3,signature_x3_0) - -// continue with new test cases .. -TEST_RR_OP(add, x4, x24, x27, 0x55555955, 0x00000400, 0x55555555, x3, 0, x5) -... -... - ----- - -.10) End the test and halt the test-target - ----- -RVTEST_CODE_END -RVMODEL_HALT ----- - -.11) Create test input data section - ----- -RVTEST_DATA_BEGIN -rvtest_data: -.word 0xbabecafe -RVTEST_DATA_END ----- - -.12) Create pre-loaded signature region - ----- - -RVMODEL_DATA_BEGIN -.align 4 - -signature_x16_0: - .fill 0*(XLEN/32),4,0xdeadbeef - - -signature_x16_1: - .fill 16*(XLEN/32),4,0xdeadbeef - - -signature_x3_0: - .fill 86*(XLEN/32),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine - -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef - -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*(XLEN/32),4,0xdeadbeef - -#endif - -RVMODEL_DATA_END ----- - diff --git a/tests/wally-riscv-arch-test/spec/testpool.jpg b/tests/wally-riscv-arch-test/spec/testpool.jpg deleted file mode 100644 index 228d0f43a..000000000 Binary files a/tests/wally-riscv-arch-test/spec/testpool.jpg and /dev/null differ