diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 6a41b1154..8b9e29e82 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -30,48 +30,50 @@ `include "wally-config.vh" -module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) ( +module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHBW) ( input logic HCLK, HRESETn, - // bus interface - input logic HREADY, - input logic [`AHBW-1:0] HRDATA, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [1:0] HTRANS, - output logic HWRITE, - output logic [`PA_BITS-1:0] HADDR, - output logic [`AHBW-1:0] HWDATA, - output logic [`AHBW/8-1:0] HWSTRB, - output logic [LOGWPL-1:0] BeatCount, + // bus interface controls + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + output logic [2:0] HSIZE, // AHB transaction width + output logic [2:0] HBURST, // AHB burst length + // bus interface buses + input logic [`AHBW-1:0] HRDATA, // AHB read data + output logic [`PA_BITS-1:0] HADDR, // AHB address + output logic [`AHBW-1:0] HWDATA, // AHB write data + output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [`PA_BITS-1:0] CacheBusAdr, - input logic [`LLEN-1:0] CacheReadDataWordM, - input logic [`LLEN-1:0] WriteDataM, - input logic CacheableOrFlushCacheM, - input logic [1:0] CacheBusRW, - output logic CacheBusAck, - output logic [LINELEN-1:0] FetchBuffer, - input logic Cacheable, - - // lsu/ifu interface - input logic Flush, - input logic [`PA_BITS-1:0] PAdr, - input logic [1:0] BusRW, - input logic Stall, - input logic [2:0] Funct3, - output logic SelBusBeat, - output logic BusStall, - output logic BusCommitted -); - - localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // *** fix me duplciated in lsu. + input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback + input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ + input logic Cacheable, // Memory operation is cachable + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshack to $ indicating bus transaction completed + output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus + output logic [LOGWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr - localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0; - logic [`PA_BITS-1:0] LocalHADDR; - logic [LOGWPL-1:0] BeatCountDelayed; - logic CaptureEn; - logic [`AHBW-1:0] PreHWDATA; + // uncached interface + input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation + input logic [`LLEN-1:0] WriteDataM, // IEU write data for uncached store + input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write + input logic [2:0] Funct3, // Size of uncached memory operation + + // lsu/ifu interface + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + + + localparam integer BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index + logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [LOGWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage + logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data genvar index; @@ -105,7 +107,6 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - logic [`AHBW/8-1:0] BusByteMaskM; swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM)); flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB); diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index 28813eb11..63449fe8d 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -31,24 +31,24 @@ `include "wally-config.vh" module ahbinterface #(parameter LSU = 0) ( // **** modify to use LSU/ifu parameter to control widths of buses - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface - input logic HREADY, - input logic [`XLEN-1:0] HRDATA, - output logic [1:0] HTRANS, - output logic HWRITE, - output logic [`XLEN-1:0] HWDATA, - output logic [`XLEN/8-1:0] HWSTRB, + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + input logic [`XLEN-1:0] HRDATA, // AHB read data + output logic [`XLEN-1:0] HWDATA, // AHB write data + output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask // lsu/ifu interface - input logic Flush, - input logic [1:0] BusRW, - input logic [`XLEN/8-1:0] ByteMask, - input logic [`XLEN-1:0] WriteData, - input logic Stall, - output logic BusStall, - output logic BusCommitted, - output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word + input logic [`XLEN-1:0] WriteData, // IEU write data for a store + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus ); logic CaptureEn; diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 33ae5e46b..d9952a456 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -33,26 +33,29 @@ module buscachefsm #(parameter integer BeatCountThreshold, LOGWPL) ( input logic HRESETn, // IEU interface - input logic Flush, - input logic [1:0] BusRW, - input logic Stall, - output logic BusCommitted, - output logic BusStall, - output logic CaptureEn, + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + + // ahb cache interface locals. + output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA // cache interface - input logic [1:0] CacheBusRW, - output logic CacheBusAck, + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshack to $ indicating bus transaction completed // lsu interface - output logic [LOGWPL-1:0] BeatCount, BeatCountDelayed, - output logic SelBusBeat, + output logic [LOGWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase + output logic [LOGWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // BUS interface - input logic HREADY, - output logic [1:0] HTRANS, - output logic HWRITE, - output logic [2:0] HBURST + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + output logic [2:0] HBURST // AHB burst length ); typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 1b2cd4f11..1e8af036c 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -32,15 +32,16 @@ module busfsm ( input logic HRESETn, // IEU interface - input logic Flush, - input logic [1:0] BusRW, - input logic Stall, - output logic BusCommitted, - output logic BusStall, - output logic CaptureEn, - input logic HREADY, - output logic [1:0] HTRANS, - output logic HWRITE + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + // AHB control signals + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ + output logic HWRITE // AHB 0: Read operation 1: Write operation ); typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype; diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index cb670b611..8249f0191 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -34,8 +34,10 @@ module datapath ( // Decode stage signals input logic [2:0] ImmSrcD, // Selects type of immediate extension input logic [31:0] InstrD, // Instruction in Decode stage - input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage // Execute stage signals + input logic [`XLEN-1:0] PCE, // PC in Execute stage + input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) + input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic [2:0] ALUControlE, // Indicate operation ALU performs @@ -43,8 +45,6 @@ module datapath ( input logic ALUResultSrcE, // Selects result to pass on to Memory stage input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - input logic [`XLEN-1:0] PCE, // PC in Execute stage - input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -77,9 +77,9 @@ module datapath ( logic [`XLEN-1:0] R1E, R2E; // Source operands read from register file logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands - logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), computed address *** According to Figure 4.12, IEUResultE should be called IEUAdrE + logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage // Memory stage signals - logic [`XLEN-1:0] IEUResultM; // Address computed by ALU *** According to Figure 4.12, IEUResultM should be called IEUAdrM + logic [`XLEN-1:0] IEUResultM; // Result from execution stage logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register // Writeback stage signals logic [`XLEN-1:0] SCResultW; // Store Conditional result diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 765fdca16..db0ddb2cc 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -37,6 +37,7 @@ module ieu ( // Execute stage signals input logic [`XLEN-1:0] PCE, // PC input logic [`XLEN-1:0] PCLinkE, // PC + 4 + output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) input logic FWriteIntE, FCvtIntE, // FPU writes to integer register file, FPU converts float to int output logic [`XLEN-1:0] IEUAdrE, // Memory address output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction @@ -66,29 +67,28 @@ module ieu ( input logic FlushD, FlushE, FlushM, FlushW, // Flush signals output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit output logic MDUStallD, CSRRdStallD, StoreStallD, - output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions ); - logic [2:0] ImmSrcD; // Select type of immediate extension - logic [1:0] FlagsE; // Comparison flags ({eq, lt}) - logic [2:0] ALUControlE; // ALU Control - logic ALUSrcAE, ALUSrcBE; // ALU source operands - logic [2:0] ResultSrcW; // Source of result in Writeback stage - logic ALUResultSrcE; // ALU result - logic SCE; // Store Conditional instruction - logic FWriteIntM; // FPU writing to integer register file - logic IntDivW; // Integer divide instruction + logic [2:0] ImmSrcD; // Select type of immediate extension + logic [1:0] FlagsE; // Comparison flags ({eq, lt}) + logic [2:0] ALUControlE; // ALU control indicates function to perform + logic ALUSrcAE, ALUSrcBE; // ALU source operands + logic [2:0] ResultSrcW; // Selects result in Writeback stage + logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage + logic SCE; // Store Conditional instruction + logic FWriteIntM; // FPU writing to integer register file + logic IntDivW; // Integer divide instruction - // forwarding signals - logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers - logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers - logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages - logic MemReadE, CSRReadE; // Load, CSRRead instruction - logic JumpE; // Jump instruction - logic BranchSignedE; // Branch does signed comparison on operands - logic MDUE; // Multiply/divide instruction + // Forwarding signals + logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers + logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers + logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages + logic MemReadE, CSRReadE; // Load, CSRRead instruction + logic JumpE; // Jump instruction + logic BranchSignedE; // Branch does signed comparison on operands + logic MDUE; // Multiply/divide instruction controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 04b880a6c..63cea9b4c 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -201,6 +201,7 @@ module ifu ( localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; if(`ICACHE) begin : icache localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; + localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; @@ -226,7 +227,7 @@ module ifu ( .NextAdr(PCNextFSpill[11:0]), .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM)); - ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) + ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, LLENPOVERAHBW) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/speculativegshare.sv index 36c9086b2..3dd66366e 100644 --- a/pipelined/src/ifu/speculativegshare.sv +++ b/pipelined/src/ifu/speculativegshare.sv @@ -123,8 +123,8 @@ module speculativegshare assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-2:-1] : // shift left - OldGHRD; + WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left + OldGHRD[k:0]; assign GHRNextE = FlushE ? GHRNextM : GHRD; flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); diff --git a/pipelined/src/ebu/amoalu.sv b/pipelined/src/lsu/amoalu.sv similarity index 100% rename from pipelined/src/ebu/amoalu.sv rename to pipelined/src/lsu/amoalu.sv diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index d4fe7a081..a5f74e91e 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -26,14 +26,15 @@ `include "wally-config.vh" module dtim( - input logic clk, ce, - input logic [1:0] MemRWM, - input logic [`PA_BITS-1:0] Adr, - input logic FlushW, - input logic [`LLEN-1:0] WriteDataM, - input logic [`LLEN/8-1:0] ByteMaskM, - output logic [`LLEN-1:0] ReadDataWordM -); + input logic clk, + input logic ce, // Chip Enable + input logic [1:0] MemRWM, // Read/Write control + input logic [`PA_BITS-1:0] AdrM, // Execution stage memory address + input logic FlushW, + input logic [`LLEN-1:0] WriteDataM, // Write data from IEU + input logic [`LLEN/8-1:0] ByteMaskM, // Selects which bytes within a word to write + output logic [`LLEN-1:0] ReadDataWordM // Read data before subword selection + ); logic we; @@ -43,6 +44,6 @@ module dtim( assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) - ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); + ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(AdrM[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e69fbcb8b..49988e791 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -232,7 +232,7 @@ module lsu ( // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. // **** create config to support DTIM with floating point. dtim dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), - .Adr(DTIMAdr), .FlushW, .WriteDataM(LSUWriteDataM), + .AdrM(DTIMAdr), .FlushW, .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); end else begin end @@ -272,7 +272,7 @@ module lsu ( .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( + ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),