mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
commit
d191bc6cc1
@ -21,6 +21,7 @@ add wave -hex /testbench/dut/hart/ifu/InstrRawD
|
|||||||
add wave /testbench/CheckInstrD
|
add wave /testbench/CheckInstrD
|
||||||
add wave /testbench/lastCheckInstrD
|
add wave /testbench/lastCheckInstrD
|
||||||
add wave /testbench/speculative
|
add wave /testbench/speculative
|
||||||
|
add wave /testbench/dut/hart/ifu/bpred/BPPredWrongE
|
||||||
add wave /testbench/lastPC2
|
add wave /testbench/lastPC2
|
||||||
add wave -divider
|
add wave -divider
|
||||||
add wave -divider
|
add wave -divider
|
||||||
|
@ -531,27 +531,28 @@ module testbench();
|
|||||||
end
|
end
|
||||||
instrs += 1;
|
instrs += 1;
|
||||||
// are we at a branch/jump?
|
// are we at a branch/jump?
|
||||||
casex (lastCheckInstrD[31:0])
|
//casex (lastCheckInstrD[31:0])
|
||||||
32'b00000000001000000000000001110011, // URET
|
// 32'b00000000001000000000000001110011, // URET
|
||||||
32'b00010000001000000000000001110011, // SRET
|
// 32'b00010000001000000000000001110011, // SRET
|
||||||
32'b00110000001000000000000001110011, // MRET
|
// 32'b00110000001000000000000001110011, // MRET
|
||||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
|
// 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1101111, // JAL
|
||||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
|
// 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100111, // JALR
|
||||||
32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
|
// 32'bXXXXXXXXXXXXXXXXXXXXXXXXX1100011, // B
|
||||||
32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
|
// 32'bXXXXXXXXXXXXXXXX110XXXXXXXXXXX01, // C.BEQZ
|
||||||
32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
|
// 32'bXXXXXXXXXXXXXXXX111XXXXXXXXXXX01, // C.BNEZ
|
||||||
32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
|
// 32'bXXXXXXXXXXXXXXXX101XXXXXXXXXXX01: // C.J
|
||||||
speculative = 1;
|
// speculative = 1;
|
||||||
32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK:
|
// 32'bXXXXXXXXXXXXXXXX1001000000000010, // C.EBREAK:
|
||||||
32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR*
|
// 32'bXXXXXXXXXXXXXXXXX000XXXXX1110011: // Something that's not CSRR*
|
||||||
speculative = 0; // tbh don't really know what should happen here
|
// speculative = 0; // tbh don't really know what should happen here
|
||||||
32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, *
|
// 32'b000110000000XXXXXXXXXXXXX1110011, // CSR* SATP, *
|
||||||
32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
|
// 32'bXXXXXXXXXXXXXXXX1000XXXXX0000010, // C.JR
|
||||||
32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
|
// 32'bXXXXXXXXXXXXXXXX1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
|
||||||
speculative = 1;
|
// speculative = 1;
|
||||||
default:
|
// default:
|
||||||
speculative = 0;
|
// speculative = 0;
|
||||||
endcase
|
//endcase
|
||||||
|
speculative = dut.hart.ifu.bpred.BPPredWrongE;
|
||||||
|
|
||||||
//check things!
|
//check things!
|
||||||
if ((~speculative) && (~equal(dut.hart.ifu.PCD,pcExpected,3))) begin
|
if ((~speculative) && (~equal(dut.hart.ifu.PCD,pcExpected,3))) begin
|
||||||
|
Loading…
Reference in New Issue
Block a user