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More bp/ifu pcmux cleanup.

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This commit is contained in:
Ross Thompson 2022-12-19 23:16:58 -06:00
parent 761cf54dcc
commit d18ef45c18
2 changed files with 19 additions and 11 deletions
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17
pipelined/src/ifu/bpred.sv
View File

@ -42,9 +42,9 @@ module bpred
input logic [31:0] InstrD,
input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
input logic [`XLEN-1:0] PCPlus2or4F,
output logic [`XLEN-1:0] PCNext0F,
output logic [`XLEN-1:0] PCNext1F,
output logic [`XLEN-1:0] PCCorrectE,
output logic [`XLEN-1:0] PCBPWrongInvalidate, // The address of the currently executing instruction
output logic [`XLEN-1:0] NextValidPCE, // The address of the currently executing instruction
// Update Predictor
input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
@ -83,6 +83,8 @@ module bpred
logic SelBPPredF;
logic [`XLEN-1:0] BPPredPCF;
logic BPPredWrongM;
logic [`XLEN-1:0] PCNext0F;
@ -262,11 +264,16 @@ module bpred
mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
// Mux only required on instruction class miss prediction.
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
.s(BPPredWrongM), .y(PCBPWrongInvalidate));
// If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
// could also just use PCM+4
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(NextValidPCE));
//assign NextValidPCE = PCE;
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
endmodule

13
pipelined/src/ifu/ifu.sv
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@ -102,7 +102,7 @@ module ifu (
localparam [31:0] nop = 32'h00000013; // instruction for NOP
logic [31:0] NextInstrD, NextInstrE;
logic [`XLEN-1:0] PCBPWrongInvalidate;
logic [`XLEN-1:0] NextValidPCE;
(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
logic [`XLEN+1:0] PCFExt;
@ -288,10 +288,10 @@ module ifu (
assign PrivilegedChangePCM = RetM | TrapM;
mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
// if(`ICACHE | `ZICSR_SUPPORTED)
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(CSRWriteFenceM),
.y(PCNext2F));
mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F));
// mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F));
// else assign PCNext2F = PCNext1F;
if(`ZICSR_SUPPORTED)
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM),
@ -308,16 +308,17 @@ module ifu (
bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM,
.FlushD, .FlushE, .FlushM,
.InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .PCBPWrongInvalidate,
.InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .NextValidPCE,
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
end else begin : bpred
mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F));
assign BPPredWrongE = PCSrcE;
assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
assign PCNext0F = PCPlus2or4F;
assign PCCorrectE = IEUAdrE;
assign PCBPWrongInvalidate = PCE;
assign NextValidPCE = PCE;
end
// pcadder