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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Relocated the misalignment faults.
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@ -141,22 +141,16 @@ module lsu (
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
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mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
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mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE);
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// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
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mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw.
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assign LSUAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : PreLSUAdrE;
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mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
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mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM);
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// always block interrupts when using the hardware page table walker.
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// always block interrupts when using the hardware page table walker.
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assign CPUBusy = StallW & ~SelHPTW;
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assign CPUBusy = StallW & ~SelHPTW;
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// Specify which type of page fault is occurring
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assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLSURWM[1];
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assign DTLBStorePageFaultM = DTLBPageFaultM & PreLSURWM[0];
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end // if (`MEM_VIRTMEM)
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end // if (`MEM_VIRTMEM)
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else begin
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else begin
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assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF} = '0;
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assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF} = '0;
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assign IgnoreRequest = TrapM;
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assign IgnoreRequest = TrapM;
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assign {DTLBLoadPageFaultM, DTLBStorePageFaultM} = '0;
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assign CPUBusy = StallW;
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assign CPUBusy = StallW;
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assign LSUAdrE = PreLSUAdrE; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign LSUAdrE = PreLSUAdrE; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
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assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM;
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assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM;
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@ -215,11 +209,15 @@ module lsu (
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// If the CPU's (not HPTW's) request is a page fault.
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// If the CPU's (not HPTW's) request is a page fault.
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assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
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assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
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assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
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assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
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// Specify which type of page fault is occurring
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assign DTLBLoadPageFaultM = DTLBPageFaultM & PreLSURWM[1];
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assign DTLBStorePageFaultM = DTLBPageFaultM & PreLSURWM[0];
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end else begin
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end else begin
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assign {DTLBMissM, DTLBPageFaultM, LoadAccessFaultM, StoreAccessFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM} = '0;
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assign {DTLBMissM, DTLBPageFaultM, LoadAccessFaultM, StoreAccessFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM} = '0;
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assign LSUPAdrM = PreLSUPAdrM;
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assign LSUPAdrM = PreLSUPAdrM;
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assign CacheableM = 1;
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assign CacheableM = 1;
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assign {DTLBLoadPageFaultM, DTLBStorePageFaultM} = '0;
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end
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end
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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