From d107a42e8c19e7dec9f3cacfed04a5d14c1db1c2 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Fri, 5 Apr 2024 21:39:41 -0700 Subject: [PATCH] Replaced rewrite command with system rm command for uart file. Fixed comment on line 573 --- testbench/testbench.sv | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3fd367eb6..d3f3ee36a 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -329,8 +329,7 @@ module testbench; memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; uartoutfilename = {"logs/",TEST,"_uart.out"}; - // Initialize uart output file - $system("rm ",uartoutfilename); // Clear existing values in uartFile + $system("rm ",uartoutfilename); // Delete existing UARToutfile end else memfilename = {pathname, tests[test], ".elf.memfile"}; if (riscofTest) begin @@ -571,7 +570,7 @@ module testbench; .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end - // Write UART output to file for tests + // Append UART output to file for tests always @(posedge clk) begin if (TEST == "buildroot") begin if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin