Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 18:25:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed LRSC in 64bit version. 32bit version is broken.

Browse Source
This commit is contained in:
Ross Thompson 2021-07-17 20:58:49 -05:00
parent 3be88117c5
commit d0ed6e250a
4 changed files with 32 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
wally-pipelined/src/cache/dcache.sv vendored
View File

@ -462,6 +462,7 @@ module dcache
CommittedM = 1'b1;
end
// amo hit
/* -----\/----- EXCLUDED -----\/-----
else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
NextState = STATE_AMO_UPDATE;
DCacheStall = 1'b1;
@ -469,6 +470,7 @@ module dcache
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_AMO_UPDATE;
end
-----/\----- EXCLUDED -----/\----- */
// read hit valid cached
else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
DCacheStall = 1'b0;
@ -493,14 +495,14 @@ module dcache
DCacheStall = 1'b1;
end
// uncached write
else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
NextState = STATE_UNCACHED_WRITE;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBWrite = 1'b1;
end
// uncached read
else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
NextState = STATE_UNCACHED_READ;
CntReset = 1'b1;
DCacheStall = 1'b1;

15
wally-pipelined/src/lsu/lrsc.sv
View File

@ -31,11 +31,12 @@ module lrsc
input logic clk, reset,
input logic FlushW, StallWtoDCache,
input logic MemReadM,
input logic [1:0] MemRWMtoDCache, // *** how does this differ from MemReadM
input logic [1:0] MemRWMtoLRSC,
output logic [1:0] MemRWMtoDCache,
input logic [1:0] AtomicMtoDCache,
input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache
output logic SquashSCM,
output logic SquashSCWfromDCache
output logic SquashSCW
);
// Handle atomic load reserved / store conditional
generate
@ -45,9 +46,10 @@ module lrsc
logic lrM, scM, WriteAdrMatchM;
assign lrM = MemReadM && AtomicMtoDCache[0];
assign scM = MemRWMtoDCache[0] && AtomicMtoDCache[0];
assign WriteAdrMatchM = MemRWMtoDCache[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
assign scM = MemRWMtoLRSC[0] && AtomicMtoDCache[0];
assign WriteAdrMatchM = MemRWMtoLRSC[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
assign SquashSCM = scM && ~WriteAdrMatchM;
assign MemRWMtoDCache = SquashSCM ? 2'b00 : MemRWMtoLRSC;
always_comb begin // ReservationValidM (next value of valid reservation)
if (lrM) ReservationValidM = 1; // set valid on load reserve
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
@ -55,10 +57,11 @@ module lrsc
end
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCWfromDCache);
flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCW);
end else begin // Atomic operations not supported
assign SquashSCM = 0;
assign SquashSCWfromDCache = 0;
assign SquashSCW = 0;
assign MemRWMtoDCache = MemRWMtoLRSC;
end
endgenerate
endmodule

29
wally-pipelined/src/lsu/lsu.sv
View File

@ -128,6 +128,7 @@ module lsu
logic UseTranslationVAdr;
logic HPTWRead;
logic [1:0] MemRWMtoDCache;
logic [1:0] MemRWMtoLRSC;
logic [2:0] Funct3MtoDCache;
logic [1:0] AtomicMtoDCache;
logic [`XLEN-1:0] MemAdrMtoDCache;
@ -135,7 +136,6 @@ module lsu
logic [`XLEN-1:0] ReadDataWfromDCache;
logic StallWtoDCache;
logic MemReadM;
logic SquashSCWfromDCache;
logic DataMisalignedMfromDCache;
logic HPTWReady;
logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB.
@ -202,18 +202,16 @@ module lsu
.PendingInterruptM(PendingInterruptM),
.StallW(StallW),
.ReadDataW(ReadDataW),
.SquashSCW(SquashSCW),
.DataMisalignedM(DataMisalignedM),
.LSUStall(LSUStall),
// DCACHE
.DisableTranslation(DisableTranslation),
.MemRWMtoDCache(MemRWMtoDCache),
.MemRWMtoLRSC(MemRWMtoLRSC),
.Funct3MtoDCache(Funct3MtoDCache),
.AtomicMtoDCache(AtomicMtoDCache),
.MemAdrMtoDCache(MemAdrMtoDCache),
.MemAdrEtoDCache(MemAdrEtoDCache),
.StallWtoDCache(StallWtoDCache),
.SquashSCWfromDCache(SquashSCWfromDCache),
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
.ReadDataWfromDCache(ReadDataWfromDCache),
.CommittedMfromDCache(CommittedMfromDCache),
@ -237,8 +235,8 @@ module lsu
.ExecuteAccessF(1'b0),
//.AtomicAccessM(AtomicMaskedM[1]),
.AtomicAccessM(1'b0),
.WriteAccessM(MemRWMtoDCache[0]),
.ReadAccessM(MemRWMtoDCache[1]),
.WriteAccessM(MemRWMtoLRSC[0]),
.ReadAccessM(MemRWMtoLRSC[1]),
.SquashBusAccess(),
.DisableTranslation(DisableTranslation),
.InstrAccessFaultF(),
@ -247,9 +245,10 @@ module lsu
.AtomicAllowed(),
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
assign MemReadM = MemRWMtoDCache[1]; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoDCache, .AtomicMtoDCache, .MemPAdrM,
.SquashSCM, .SquashSCWfromDCache);
assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
.SquashSCM, .SquashSCW, .MemRWMtoDCache);
// *** BUG, this is most likely wrong
assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;
@ -261,8 +260,8 @@ module lsu
// Specify which type of page fault is occurring
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoDCache[1];
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoDCache[0];
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLRSC[1];
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
// Determine if an Unaligned access is taking place
always_comb
@ -282,8 +281,8 @@ module lsu
// *** BUG for now leave this out. come back later after the d cache is working. July 09, 2021
assign MemReadM = MemRWMtoDCache[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
assign MemWriteM = MemRWMtoDCache[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED;
assign MemReadM = MemRWMtoLRSC[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
assign MemWriteM = MemRWMtoLRSC[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED;
assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoDCache : 2'b00 ;
assign MemAccessM = MemReadM | MemWriteM;
@ -296,8 +295,8 @@ module lsu
-----/\----- EXCLUDED -----/\----- */
// Determine if address is valid
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[1];
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoDCache[0];
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1];
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
dcache dcache(.clk(clk),
.reset(reset),

7
wally-pipelined/src/lsu/lsuArb.sv
View File

@ -45,14 +45,13 @@ module lsuArb
input logic PendingInterruptM,
// to CPU
output logic [`XLEN-1:0] ReadDataW,
output logic SquashSCW,
output logic DataMisalignedM,
output logic CommittedM,
output logic LSUStall,
// to D Cache
output logic DisableTranslation,
output logic [1:0] MemRWMtoDCache,
output logic [1:0] MemRWMtoLRSC,
output logic [2:0] Funct3MtoDCache,
output logic [1:0] AtomicMtoDCache,
output logic [`XLEN-1:0] MemAdrMtoDCache,
@ -63,7 +62,6 @@ module lsuArb
// from D Cache
input logic CommittedMfromDCache,
input logic SquashSCWfromDCache,
input logic DataMisalignedMfromDCache,
input logic [`XLEN-1:0] ReadDataWfromDCache,
input logic DCacheStall
@ -75,7 +73,7 @@ module lsuArb
// multiplex the outputs to LSU
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
assign MemRWMtoDCache = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
generate
assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
@ -94,7 +92,6 @@ module lsuArb
// demux the inputs from LSU to walker or cpu's data port.
assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWfromDCache; // probably can avoid this demux
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromDCache;
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromDCache;
// *** need to rename DcacheStall and Datastall.
// not clear at all. I think it should be LSUStall from the LSU,