mirror of
https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
commit
d0b9ebd2ef
@ -25,7 +25,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module cachereplacementpolicy
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module cachereplacementpolicy
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#(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
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#(parameter NUMWAYS = 4, INDEXLEN = 9, OFFSETLEN = 5, NUMLINES = 128)
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(input logic clk, reset,
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(input logic clk, reset,
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input logic [NUMWAYS-1:0] WayHit,
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input logic [NUMWAYS-1:0] WayHit,
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output logic [NUMWAYS-1:0] VictimWay,
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output logic [NUMWAYS-1:0] VictimWay,
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13
wally-pipelined/src/cache/cacheway.sv
vendored
13
wally-pipelined/src/cache/cacheway.sv
vendored
@ -26,7 +26,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
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module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
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parameter OFFSETLEN, parameter INDEXLEN, parameter DIRTY_BITS = 1)
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parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1)
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(input logic clk,
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(input logic clk,
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input logic reset,
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input logic reset,
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@ -109,6 +109,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
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ValidBits <= {NUMLINES{1'b0}};
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ValidBits <= {NUMLINES{1'b0}};
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else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1;
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else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1;
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else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0;
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else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0;
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end
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always_ff @(posedge clk) begin
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Valid <= ValidBits[RAdr];
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Valid <= ValidBits[RAdr];
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end
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end
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@ -119,6 +122,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
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DirtyBits <= {NUMLINES{1'b0}};
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DirtyBits <= {NUMLINES{1'b0}};
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else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1;
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else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1;
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else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0;
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else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0;
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end
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end
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endgenerate
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// Since this is always updated on a clock edge we cannot include reset.
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generate
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if(DIRTY_BITS) begin
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always_ff @(posedge clk) begin
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Dirty <= DirtyBits[RAdr];
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Dirty <= DirtyBits[RAdr];
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end
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end
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end else begin
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end else begin
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@ -25,7 +25,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module tlbramline #(parameter WIDTH)
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module tlbramline #(parameter WIDTH = 22)
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(input logic clk, reset,
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(input logic clk, reset,
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input logic re, we,
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input logic re, we,
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input logic [WIDTH-1:0] d,
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input logic [WIDTH-1:0] d,
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