mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'multimanager' into main
This commit is contained in:
commit
d07c44bcf6
@ -3,7 +3,7 @@
|
|||||||
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
|
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
|
||||||
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
|
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
|
||||||
|
|
||||||
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
||||||
|
|
||||||
##### GPI ####
|
##### GPI ####
|
||||||
set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
|
set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
|
||||||
|
File diff suppressed because one or more lines are too long
@ -9,15 +9,15 @@
|
|||||||
</db_ref>
|
</db_ref>
|
||||||
</db_ref_list>
|
</db_ref_list>
|
||||||
<zoom_setting>
|
<zoom_setting>
|
||||||
<ZoomStartTime time="0fs"></ZoomStartTime>
|
<ZoomStartTime time="8081fs"></ZoomStartTime>
|
||||||
<ZoomEndTime time="3838fs"></ZoomEndTime>
|
<ZoomEndTime time="8103fs"></ZoomEndTime>
|
||||||
<Cursor1Time time="0fs"></Cursor1Time>
|
<Cursor1Time time="8083fs"></Cursor1Time>
|
||||||
</zoom_setting>
|
</zoom_setting>
|
||||||
<column_width_setting>
|
<column_width_setting>
|
||||||
<NameColumnWidth column_width="452"></NameColumnWidth>
|
<NameColumnWidth column_width="355"></NameColumnWidth>
|
||||||
<ValueColumnWidth column_width="133"></ValueColumnWidth>
|
<ValueColumnWidth column_width="170"></ValueColumnWidth>
|
||||||
</column_width_setting>
|
</column_width_setting>
|
||||||
<WVObjectSize size="11" />
|
<WVObjectSize size="15" />
|
||||||
<wave_markers>
|
<wave_markers>
|
||||||
</wave_markers>
|
</wave_markers>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
|
||||||
@ -53,6 +53,7 @@
|
|||||||
<wvobject type="group" fp_name="group468">
|
<wvobject type="group" fp_name="group468">
|
||||||
<obj_property name="label">CPU to LSU</obj_property>
|
<obj_property name="label">CPU to LSU</obj_property>
|
||||||
<obj_property name="DisplayName">label</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
<obj_property name="isExpanded"></obj_property>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
|
||||||
@ -81,7 +82,6 @@
|
|||||||
<wvobject type="group" fp_name="group469">
|
<wvobject type="group" fp_name="group469">
|
||||||
<obj_property name="label">xIP</obj_property>
|
<obj_property name="label">xIP</obj_property>
|
||||||
<obj_property name="DisplayName">label</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
<obj_property name="isExpanded"></obj_property>
|
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5">
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]</obj_property>
|
||||||
@ -91,46 +91,36 @@
|
|||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5">
|
||||||
|
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">MIP_REGW_5[9:9]</obj_property>
|
||||||
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
<obj_property name="LABELRADIX">true</obj_property>
|
||||||
|
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||||
|
</wvobject>
|
||||||
<wvobject type="group" fp_name="group470">
|
<wvobject type="group" fp_name="group470">
|
||||||
<obj_property name="label">PLIC</obj_property>
|
<obj_property name="label">PLIC</obj_property>
|
||||||
<obj_property name="DisplayName">label</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/requests">
|
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/requests[12:1]</obj_property>
|
|
||||||
<obj_property name="ObjectShortName">requests[12:1]</obj_property>
|
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPending">
|
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPending[12:1]</obj_property>
|
|
||||||
<obj_property name="ObjectShortName">intPending[12:1]</obj_property>
|
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intInProgress">
|
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intInProgress[12:1]</obj_property>
|
|
||||||
<obj_property name="ObjectShortName">intInProgress[12:1]</obj_property>
|
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="group" fp_name="group471">
|
<wvobject type="group" fp_name="group471">
|
||||||
<obj_property name="label">interrupts</obj_property>
|
<obj_property name="label">interrupts</obj_property>
|
||||||
<obj_property name="DisplayName">label</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
|
||||||
|
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
|
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
<obj_property name="LABELRADIX">true</obj_property>
|
||||||
|
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
|
||||||
|
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
|
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
<obj_property name="LABELRADIX">true</obj_property>
|
||||||
|
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
|
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||||
@ -143,58 +133,39 @@
|
|||||||
<wvobject type="group" fp_name="group463">
|
<wvobject type="group" fp_name="group463">
|
||||||
<obj_property name="label">LSU to Bus</obj_property>
|
<obj_property name="label">LSU to Bus</obj_property>
|
||||||
<obj_property name="DisplayName">label</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusRead">
|
<obj_property name="isExpanded"></obj_property>
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHADDR">
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusRead</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHADDR[31:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">LSUBusRead</obj_property>
|
<obj_property name="ObjectShortName">LSUHADDR[31:0]</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
|
||||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusWrite">
|
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusWrite</obj_property>
|
|
||||||
<obj_property name="ObjectShortName">LSUBusWrite</obj_property>
|
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusAdr">
|
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusAdr[31:0]</obj_property>
|
|
||||||
<obj_property name="ObjectShortName">LSUBusAdr[31:0]</obj_property>
|
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusSize">
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHBURST">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHBURST[2:0]</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusSize[1:0]</obj_property>
|
<obj_property name="ObjectShortName">LSUHBURST[2:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">LSUBusSize[1:0]</obj_property>
|
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusHWDATA">
|
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUHREADY">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHREADY</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusHWDATA[63:0]</obj_property>
|
<obj_property name="ObjectShortName">LSUHREADY</obj_property>
|
||||||
<obj_property name="ObjectShortName">LSUBusHWDATA[63:0]</obj_property>
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHSIZE">
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHSIZE[1:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">LSUHSIZE[1:0]</obj_property>
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusHRDATA">
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHWDATA">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHWDATA[63:0]</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusHRDATA[63:0]</obj_property>
|
<obj_property name="ObjectShortName">LSUHWDATA[63:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">LSUBusHRDATA[63:0]</obj_property>
|
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusAck">
|
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUHWRITE">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHWRITE</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusAck</obj_property>
|
<obj_property name="ObjectShortName">LSUHWRITE</obj_property>
|
||||||
<obj_property name="ObjectShortName">LSUBusAck</obj_property>
|
</wvobject>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="group" fp_name="group488">
|
<wvobject type="group" fp_name="group488">
|
||||||
@ -252,43 +223,69 @@
|
|||||||
<wvobject type="group" fp_name="group487">
|
<wvobject type="group" fp_name="group487">
|
||||||
<obj_property name="label">sdc</obj_property>
|
<obj_property name="label">sdc</obj_property>
|
||||||
<obj_property name="DisplayName">label</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
<wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q">
|
</wvobject>
|
||||||
|
<wvobject type="group" fp_name="group267">
|
||||||
|
<obj_property name="label">dcache</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState">
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">r_DAT_ERROR_Q</obj_property>
|
<obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
|
||||||
</wvobject>
|
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state">
|
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4:0]</obj_property>
|
|
||||||
<obj_property name="ObjectShortName">r_curr_state[4:0]</obj_property>
|
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
<obj_property name="LABELRADIX">true</obj_property>
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state">
|
</wvobject>
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<wvobject type="group" fp_name="group334">
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3:0]</obj_property>
|
<obj_property name="label">EBU</obj_property>
|
||||||
<obj_property name="ObjectShortName">r_curr_state[3:0]</obj_property>
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="isExpanded"></obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HTRANS">
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0]</obj_property>
|
||||||
</wvobject>
|
<obj_property name="ObjectShortName">HTRANS[1:0]</obj_property>
|
||||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state">
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
</wvobject>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3:0]</obj_property>
|
<wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HWRITE">
|
||||||
<obj_property name="ObjectShortName">r_curr_state[3:0]</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HWRITE</obj_property>
|
||||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
<obj_property name="ObjectShortName">HWRITE</obj_property>
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
</wvobject>
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HBURST">
|
||||||
</wvobject>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HBURST[2:0]</obj_property>
|
||||||
<wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16">
|
<obj_property name="ObjectShortName">HBURST[2:0]</obj_property>
|
||||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16</obj_property>
|
</wvobject>
|
||||||
<obj_property name="ObjectShortName">i_ERROR_CRC16</obj_property>
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HSIZE">
|
||||||
<obj_property name="LABELRADIX">true</obj_property>
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0]</obj_property>
|
||||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
<obj_property name="ObjectShortName">HSIZE[2:0]</obj_property>
|
||||||
</wvobject>
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HADDR">
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HADDR[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">HADDR[31:0]</obj_property>
|
||||||
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HWDATA">
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">HWDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HREADY">
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HREADY</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">HREADY</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HRESP">
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HRESP</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">HRESP</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
|
||||||
|
<obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
|
||||||
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
</wave_config>
|
</wave_config>
|
||||||
|
@ -169,7 +169,7 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load
|
|||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
|
||||||
add wave -noupdate -expand -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/BusState
|
add wave -noupdate -expand -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/CurrState
|
||||||
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both
|
||||||
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save
|
||||||
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore
|
||||||
@ -177,6 +177,8 @@ add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut
|
|||||||
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel
|
||||||
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive
|
||||||
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive
|
||||||
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/BeatCount
|
||||||
|
add wave -noupdate -expand -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/BeatCountDelayed
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/Threshold
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/Threshold
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||||
@ -196,7 +198,6 @@ add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu
|
|||||||
add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
|
add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
|
||||||
add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
|
add wave -noupdate -expand -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
|
||||||
add wave -noupdate -expand -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
|
add wave -noupdate -expand -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/NextBusState
|
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY
|
||||||
@ -211,185 +212,187 @@ add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
|||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDRD
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDRD
|
||||||
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZED
|
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZED
|
||||||
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
|
add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||||
add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/BusCurrState
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/RW
|
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/CacheRW
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/RW
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/AHBBuscachefsm/Cacheable
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CacheRW
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/HTRANS
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/FetchBuffer
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/HRDATA
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/cachedp/WordCount
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/LSUHWDATA_noDELAY
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/WordCount
|
||||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/LSUHWDATA_noDELAY
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData[62]}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData[62]}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelEvict
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelEvict
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelBusWord
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelBusWord
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FinalWriteData
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
|
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
||||||
|
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
||||||
|
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim
|
||||||
@ -460,77 +463,74 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
|||||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
|
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
|
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
|
||||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusRead
|
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
||||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUBusAck
|
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
||||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUTransComplete
|
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
||||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
|
||||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||||
add wave -noupdate -expand -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
|
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
|
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetDirtyWay
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetValidWay
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetDirtyWay
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetValidWay
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ByteMask}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ReadData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ByteMask}
|
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ReadData}
|
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
|
||||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
|
|
||||||
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
|
||||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||||
add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||||
@ -545,24 +545,41 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I
|
|||||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||||
add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/BusCurrState
|
add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheRW
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CacheRW
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/RW
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/RW
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/HREADY
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/WordCount
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/WordCount
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/FetchBuffer
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/CaptureEn
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/CaptureEn
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HADDR
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HSIZE
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/HTRANS
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
|
||||||
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/CacheBusAck
|
add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CacheBusAck
|
||||||
add wave -noupdate /testbench/dut/core/ifu/bus/icache/cachedp/AHBBuscachefsm/WordCountFlag
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/CurrState
|
||||||
add wave -noupdate /testbench/dut/core/lsu/ByteMaskM
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/DelayReady
|
||||||
add wave -noupdate /testbench/dut/core/fpu/fpu/FWriteDataM
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/CycleFlag
|
||||||
#add wave -group {Sqrt} -noupdate -recursive /testbench/dut/core/fpu/fpu/fdivsqrt/*
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/CycleThreshold
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/Cycle
|
||||||
|
add wave -noupdate /testbench/dut/HRDATA
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/HREADRam
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/HADDR
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/RamAddr
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/HREADY
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/HADDRD
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/initTrans
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/HREADYRam
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/HREADYRam
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/HREADY
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/HSELRegions
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/HSELRam
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/HSELRamD
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/addr
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memwriteD
|
||||||
|
add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memwrite
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 2} {377526 ns} 0} {{Cursor 3} {377441 ns} 1} {{Cursor 4} {378225 ns} 1}
|
WaveRestoreCursors {{Cursor 2} {5825491 ns} 1} {{Cursor 3} {1019481 ns} 0} {{Cursor 4} {378225 ns} 1}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 2
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 314
|
configure wave -valuecolwidth 314
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -577,4 +594,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {377347 ns} {377625 ns}
|
WaveRestoreZoom {0 ns} {1435677 ns}
|
||||||
|
74
pipelined/src/ebu/abhinterface.sv
Normal file
74
pipelined/src/ebu/abhinterface.sv
Normal file
@ -0,0 +1,74 @@
|
|||||||
|
///////////////////////////////////////////
|
||||||
|
// ahbinterface.sv
|
||||||
|
//
|
||||||
|
// Written: Ross Thompson ross1728@gmail.com August 29, 2022
|
||||||
|
// Modified:
|
||||||
|
//
|
||||||
|
// Purpose: Cache/Bus data path.
|
||||||
|
// Bus Side logic
|
||||||
|
// register the fetch data from the next level of memory.
|
||||||
|
// This register should be necessary for timing. There is no register in the uncore or
|
||||||
|
// ahblite controller between the memories and this cache.
|
||||||
|
//
|
||||||
|
// A component of the Wally configurable RISC-V project.
|
||||||
|
//
|
||||||
|
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||||
|
//
|
||||||
|
// MIT LICENSE
|
||||||
|
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||||
|
// software and associated documentation files (the "Software"), to deal in the Software
|
||||||
|
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||||
|
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||||
|
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||||
|
//
|
||||||
|
// The above copyright notice and this permission notice shall be included in all copies or
|
||||||
|
// substantial portions of the Software.
|
||||||
|
//
|
||||||
|
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||||
|
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||||
|
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||||
|
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||||
|
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||||
|
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
`include "wally-config.vh"
|
||||||
|
|
||||||
|
module ahbinterface #(parameter WRITEABLE = 0)
|
||||||
|
(
|
||||||
|
input logic HCLK, HRESETn,
|
||||||
|
|
||||||
|
// bus interface
|
||||||
|
input logic HREADY,
|
||||||
|
input logic [`XLEN-1:0] HRDATA,
|
||||||
|
output logic [1:0] HTRANS,
|
||||||
|
output logic HWRITE,
|
||||||
|
output logic [`XLEN-1:0] HWDATA,
|
||||||
|
output logic [`XLEN/8-1:0] HWSTRB,
|
||||||
|
|
||||||
|
// lsu/ifu interface
|
||||||
|
input logic [1:0] RW,
|
||||||
|
input logic [`XLEN/8-1:0] ByteMask,
|
||||||
|
input logic [`XLEN-1:0] WriteData,
|
||||||
|
input logic CPUBusy,
|
||||||
|
output logic BusStall,
|
||||||
|
output logic BusCommitted,
|
||||||
|
output logic [`XLEN-1:0] ReadDataWord);
|
||||||
|
|
||||||
|
logic CaptureEn;
|
||||||
|
|
||||||
|
flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWord));
|
||||||
|
|
||||||
|
if(WRITEABLE) begin
|
||||||
|
// delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
||||||
|
flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA);
|
||||||
|
flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
|
||||||
|
end else begin
|
||||||
|
assign HWDATA = '0;
|
||||||
|
assign HWSTRB = '0;
|
||||||
|
end
|
||||||
|
|
||||||
|
busfsm busfsm(.HCLK, .HRESETn, .RW,
|
||||||
|
.BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY,
|
||||||
|
.HTRANS, .HWRITE);
|
||||||
|
endmodule
|
@ -1,5 +1,5 @@
|
|||||||
///////////////////////////////////////////
|
///////////////////////////////////////////
|
||||||
// AHBCachedp.sv
|
// ahbcacheinterface.sv
|
||||||
//
|
//
|
||||||
// Written: Ross Thompson ross1728@gmail.com August 29, 2022
|
// Written: Ross Thompson ross1728@gmail.com August 29, 2022
|
||||||
// Modified:
|
// Modified:
|
||||||
@ -34,7 +34,7 @@
|
|||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
|
||||||
module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
|
module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
|
||||||
(
|
(
|
||||||
input logic HCLK, HRESETn,
|
input logic HCLK, HRESETn,
|
||||||
|
|
||||||
@ -82,7 +82,7 @@ module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
|
|||||||
|
|
||||||
mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
|
mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
|
||||||
|
|
||||||
AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
|
buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
|
||||||
.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
|
.HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
|
||||||
.CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
|
.CacheRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
|
||||||
.HREADY, .HTRANS, .HWRITE, .HBURST);
|
.HREADY, .HTRANS, .HWRITE, .HBURST);
|
@ -1,141 +0,0 @@
|
|||||||
///////////////////////////////////////////
|
|
||||||
// ahblite.sv
|
|
||||||
//
|
|
||||||
// Written: David_Harris@hmc.edu 9 January 2021
|
|
||||||
// Modified:
|
|
||||||
//
|
|
||||||
// Purpose: AHB Lite External Bus Unit
|
|
||||||
// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
|
|
||||||
// Arbitrates requests from instruction and data streams
|
|
||||||
// Connects core to peripherals and I/O pins on SOC
|
|
||||||
// Bus width presently matches XLEN
|
|
||||||
// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
|
|
||||||
//
|
|
||||||
// A component of the Wally configurable RISC-V project.
|
|
||||||
//
|
|
||||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
|
||||||
//
|
|
||||||
// MIT LICENSE
|
|
||||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
|
||||||
// software and associated documentation files (the "Software"), to deal in the Software
|
|
||||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
|
||||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
|
||||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
|
||||||
//
|
|
||||||
// The above copyright notice and this permission notice shall be included in all copies or
|
|
||||||
// substantial portions of the Software.
|
|
||||||
//
|
|
||||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
|
||||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
|
||||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
|
||||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
|
||||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
|
||||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
|
||||||
|
|
||||||
`include "wally-config.vh"
|
|
||||||
|
|
||||||
module ahblite (
|
|
||||||
input logic clk, reset,
|
|
||||||
// Load control
|
|
||||||
input logic UnsignedLoadM,
|
|
||||||
input logic [1:0] AtomicMaskedM,
|
|
||||||
// Signals from Instruction Cache
|
|
||||||
input logic [`PA_BITS-1:0] IFUHADDR,
|
|
||||||
input logic [2:0] IFUHBURST,
|
|
||||||
input logic [1:0] IFUHTRANS,
|
|
||||||
input logic IFUBusRead,
|
|
||||||
input logic IFUTransComplete,
|
|
||||||
logic IFUHWRITE,
|
|
||||||
logic IFUHREADY,
|
|
||||||
output logic IFUBusInit,
|
|
||||||
output logic IFUBusAck,
|
|
||||||
|
|
||||||
// Signals from Data Cache
|
|
||||||
input logic [`PA_BITS-1:0] LSUHADDR,
|
|
||||||
input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
|
|
||||||
input logic [2:0] LSUHSIZE,
|
|
||||||
input logic [2:0] LSUHBURST,
|
|
||||||
input logic [1:0] LSUHTRANS,
|
|
||||||
input logic LSUBusRead,
|
|
||||||
input logic LSUBusWrite,
|
|
||||||
input logic LSUTransComplete,
|
|
||||||
logic LSUHWRITE,
|
|
||||||
logic LSUHREADY,
|
|
||||||
output logic LSUBusInit,
|
|
||||||
output logic LSUBusAck,
|
|
||||||
|
|
||||||
// AHB-Lite external signals
|
|
||||||
(* mark_debug = "true" *) input logic HREADY, HRESP,
|
|
||||||
(* mark_debug = "true" *) output logic HCLK, HRESETn,
|
|
||||||
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address
|
|
||||||
(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
|
|
||||||
output logic [`XLEN/8-1:0] HWSTRB,
|
|
||||||
(* mark_debug = "true" *) output logic HWRITE,
|
|
||||||
(* mark_debug = "true" *) output logic [2:0] HSIZE,
|
|
||||||
(* mark_debug = "true" *) output logic [2:0] HBURST,
|
|
||||||
(* mark_debug = "true" *) output logic [3:0] HPROT,
|
|
||||||
(* mark_debug = "true" *) output logic [1:0] HTRANS,
|
|
||||||
(* mark_debug = "true" *) output logic HMASTLOCK
|
|
||||||
);
|
|
||||||
|
|
||||||
localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator
|
|
||||||
|
|
||||||
typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
|
|
||||||
statetype BusState, NextBusState;
|
|
||||||
logic LSUGrant;
|
|
||||||
logic [ADRBITS-1:0] HADDRD;
|
|
||||||
logic [1:0] HSIZED;
|
|
||||||
|
|
||||||
assign HCLK = clk;
|
|
||||||
assign HRESETn = ~reset;
|
|
||||||
|
|
||||||
// Bus State FSM
|
|
||||||
// Data accesses have priority over instructions. However, if a data access comes
|
|
||||||
// while an cache line read is occuring, the line read finishes before
|
|
||||||
// the data access can take place.
|
|
||||||
|
|
||||||
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
|
|
||||||
always_comb
|
|
||||||
case (BusState)
|
|
||||||
IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
|
|
||||||
else if (LSUBusWrite) NextBusState = MEMWRITE;
|
|
||||||
else if (IFUBusRead) NextBusState = INSTRREAD;
|
|
||||||
else NextBusState = IDLE;
|
|
||||||
MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
|
|
||||||
else if (LSUTransComplete) NextBusState = IDLE;
|
|
||||||
else NextBusState = MEMREAD;
|
|
||||||
MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
|
|
||||||
else if (LSUTransComplete) NextBusState = IDLE;
|
|
||||||
else NextBusState = MEMWRITE;
|
|
||||||
INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD;
|
|
||||||
else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE;
|
|
||||||
else if (IFUTransComplete) NextBusState = IDLE;
|
|
||||||
else NextBusState = INSTRREAD;
|
|
||||||
default: NextBusState = IDLE;
|
|
||||||
endcase
|
|
||||||
|
|
||||||
// LSU/IFU mux: choose source of access
|
|
||||||
assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
|
|
||||||
assign HADDR = LSUGrant ? LSUHADDR : IFUHADDR;
|
|
||||||
assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
|
|
||||||
assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.
|
|
||||||
assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
|
|
||||||
assign HPROT = 4'b0011; // not used; see Section 3.7
|
|
||||||
assign HMASTLOCK = 0; // no locking supported
|
|
||||||
assign HWRITE = (NextBusState == MEMWRITE);
|
|
||||||
|
|
||||||
// delay write data by one cycle for
|
|
||||||
flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
|
||||||
|
|
||||||
// Byte mask for HWSTRB based on delayed signals
|
|
||||||
flop #(ADRBITS) adrreg(HCLK, HADDR[ADRBITS-1:0], HADDRD);
|
|
||||||
flop #(2) sizereg(HCLK, HSIZE[1:0], HSIZED);
|
|
||||||
swbytemask swbytemask(.Size({1'b0, HSIZED}), .Adr(HADDRD), .ByteMask(HWSTRB));
|
|
||||||
|
|
||||||
// Send control back to IFU and LSU
|
|
||||||
assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD);
|
|
||||||
assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE));
|
|
||||||
assign IFUBusAck = HREADY & (BusState == INSTRREAD);
|
|
||||||
assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE));
|
|
||||||
endmodule
|
|
@ -80,17 +80,17 @@ module ahbmultimanager
|
|||||||
logic [1:0] save, restore, dis, sel;
|
logic [1:0] save, restore, dis, sel;
|
||||||
logic both;
|
logic both;
|
||||||
|
|
||||||
logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDRRestore;
|
logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDROut;
|
||||||
logic [1:0] IFUHTRANSSave, IFUHTRANSRestore;
|
logic [1:0] IFUHTRANSSave, IFUHTRANSOut;
|
||||||
logic [2:0] IFUHBURSTSave, IFUHBURSTRestore;
|
logic [2:0] IFUHBURSTSave, IFUHBURSTOut;
|
||||||
logic [2:0] IFUHSIZERestore;
|
logic [2:0] IFUHSIZEOut;
|
||||||
logic IFUHWRITERestore;
|
logic IFUHWRITEOut;
|
||||||
|
|
||||||
logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDRRestore;
|
logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDROut;
|
||||||
logic [1:0] LSUHTRANSSave, LSUHTRANSRestore;
|
logic [1:0] LSUHTRANSSave, LSUHTRANSOut;
|
||||||
logic [2:0] LSUHBURSTSave, LSUHBURSTRestore;
|
logic [2:0] LSUHBURSTSave, LSUHBURSTOut;
|
||||||
logic [2:0] LSUHSIZESave, LSUHSIZERestore;
|
logic [2:0] LSUHSIZESave, LSUHSIZEOut;
|
||||||
logic LSUHWRITESave, LSUHWRITERestore;
|
logic LSUHWRITESave, LSUHWRITEOut;
|
||||||
|
|
||||||
logic IFUReq, LSUReq;
|
logic IFUReq, LSUReq;
|
||||||
logic IFUActive, LSUActive;
|
logic IFUActive, LSUActive;
|
||||||
@ -113,24 +113,24 @@ module ahbmultimanager
|
|||||||
managerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
|
managerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
|
||||||
.Request(IFUReq), .Active(IFUActive),
|
.Request(IFUReq), .Active(IFUActive),
|
||||||
.HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
|
.HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
|
||||||
.HWRITERestore(IFUHWRITERestore), .HSIZERestore(IFUHSIZERestore), .HBURSTRestore(IFUHBURSTRestore), .HREADYRestore(IFUHREADY),
|
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
|
||||||
.HTRANSRestore(IFUHTRANSRestore), .HADDRRestore(IFUHADDRRestore), .HREADYin(HREADY));
|
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
|
||||||
|
|
||||||
// input stage LSU
|
// input stage LSU
|
||||||
managerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
|
managerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
|
||||||
.Request(LSUReq), .Active(LSUActive),
|
.Request(LSUReq), .Active(LSUActive),
|
||||||
.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYRestore(LSUHREADY),
|
.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),
|
||||||
.HWRITERestore(LSUHWRITERestore), .HSIZERestore(LSUHSIZERestore), .HBURSTRestore(LSUHBURSTRestore),
|
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
|
||||||
.HTRANSRestore(LSUHTRANSRestore), .HADDRRestore(LSUHADDRRestore), .HREADYin(HREADY));
|
.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY));
|
||||||
|
|
||||||
// output mux //*** rewrite for general number of managers.
|
// output mux //*** rewrite for general number of managers.
|
||||||
assign HADDR = sel[1] ? LSUHADDRRestore : sel[0] ? IFUHADDRRestore : '0;
|
assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0;
|
||||||
assign HSIZE = sel[1] ? LSUHSIZERestore : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits
|
assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits
|
||||||
assign HBURST = sel[1] ? LSUHBURSTRestore : sel[0] ? IFUHBURSTRestore : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
|
assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
|
||||||
assign HTRANS = sel[1] ? LSUHTRANSRestore : sel[0] ? IFUHTRANSRestore: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
|
assign HTRANS = sel[1] ? LSUHTRANSOut : sel[0] ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
|
||||||
|
assign HWRITE = sel[1] ? LSUHWRITEOut : sel[0] ? 1'b0 : '0;
|
||||||
assign HPROT = 4'b0011; // not used; see Section 3.7
|
assign HPROT = 4'b0011; // not used; see Section 3.7
|
||||||
assign HMASTLOCK = 0; // no locking supported
|
assign HMASTLOCK = 0; // no locking supported
|
||||||
assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0;
|
|
||||||
|
|
||||||
// data phase muxing. This would be a mux if IFU wrote data.
|
// data phase muxing. This would be a mux if IFU wrote data.
|
||||||
assign HWDATA = LSUHWDATA;
|
assign HWDATA = LSUHWDATA;
|
||||||
@ -145,15 +145,16 @@ module ahbmultimanager
|
|||||||
case (CurrState)
|
case (CurrState)
|
||||||
IDLE: if (both) NextState = ARBITRATE;
|
IDLE: if (both) NextState = ARBITRATE;
|
||||||
else NextState = IDLE;
|
else NextState = IDLE;
|
||||||
ARBITRATE: if (HREADY & FinalBeat) NextState = IDLE;
|
ARBITRATE: if (HREADY & FinalBeat & ~(LSUReq & IFUReq)) NextState = IDLE;
|
||||||
else NextState = ARBITRATE;
|
else NextState = ARBITRATE;
|
||||||
default: NextState = IDLE;
|
default: NextState = IDLE;
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
|
// This part is only used when burst mode is supported.
|
||||||
// Manager needs to count beats.
|
// Manager needs to count beats.
|
||||||
flopenr #(4)
|
flopenr #(4)
|
||||||
BeatCountReg(.clk(HCLK),
|
BeatCountReg(.clk(HCLK),
|
||||||
.reset(~HRESETn | CntReset),
|
.reset(~HRESETn | CntReset | FinalBeat),
|
||||||
.en(BeatCntEn),
|
.en(BeatCntEn),
|
||||||
.d(NextBeatCount),
|
.d(NextBeatCount),
|
||||||
.q(BeatCount));
|
.q(BeatCount));
|
||||||
@ -185,9 +186,10 @@ module ahbmultimanager
|
|||||||
default: Threshold = 4'b0000; // INCR without end.
|
default: Threshold = 4'b0000; // INCR without end.
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
// end of burst mode.
|
||||||
|
|
||||||
// basic arb always selects LSU when both
|
// basic arb always selects LSU when both
|
||||||
// replace this block for more sophisticated arbitration.
|
// replace this block for more sophisticated arbitration as needed.
|
||||||
// Manager 0 (IFU)
|
// Manager 0 (IFU)
|
||||||
assign save[0] = CurrState == IDLE & both;
|
assign save[0] = CurrState == IDLE & both;
|
||||||
assign restore[0] = CurrState == ARBITRATE;
|
assign restore[0] = CurrState == ARBITRATE;
|
||||||
|
@ -29,9 +29,10 @@
|
|||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
`define BURST_EN 1
|
||||||
|
|
||||||
// HCLK and clk must be the same clock!
|
// HCLK and clk must be the same clock!
|
||||||
module AHBBuscachefsm #(parameter integer WordCountThreshold,
|
module buscachefsm #(parameter integer WordCountThreshold,
|
||||||
parameter integer LOGWPL, parameter logic CACHE_ENABLED )
|
parameter integer LOGWPL, parameter logic CACHE_ENABLED )
|
||||||
(input logic HCLK,
|
(input logic HCLK,
|
||||||
input logic HRESETn,
|
input logic HRESETn,
|
||||||
@ -59,16 +60,15 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
|
|||||||
output logic [2:0] HBURST
|
output logic [2:0] HBURST
|
||||||
);
|
);
|
||||||
|
|
||||||
typedef enum logic [2:0] {STATE_READY,
|
typedef enum logic [2:0] {ADR_PHASE,
|
||||||
STATE_CAPTURE,
|
DATA_PHASE,
|
||||||
STATE_DELAY,
|
MEM3,
|
||||||
STATE_CPU_BUSY,
|
CACHE_FETCH,
|
||||||
STATE_CACHE_FETCH,
|
CACHE_EVICT} busstatetype;
|
||||||
STATE_CACHE_EVICT} busstatetype;
|
|
||||||
|
|
||||||
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
|
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
|
||||||
|
|
||||||
(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
|
(* mark_debug = "true" *) busstatetype CurrState, NextState;
|
||||||
|
|
||||||
logic [LOGWPL-1:0] NextWordCount;
|
logic [LOGWPL-1:0] NextWordCount;
|
||||||
logic FinalWordCount;
|
logic FinalWordCount;
|
||||||
@ -78,26 +78,24 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
|
|||||||
logic CacheAccess;
|
logic CacheAccess;
|
||||||
|
|
||||||
always_ff @(posedge HCLK)
|
always_ff @(posedge HCLK)
|
||||||
if (~HRESETn) BusCurrState <= #1 STATE_READY;
|
if (~HRESETn) CurrState <= #1 ADR_PHASE;
|
||||||
else BusCurrState <= #1 BusNextState;
|
else CurrState <= #1 NextState;
|
||||||
|
|
||||||
always_comb begin
|
always_comb begin
|
||||||
case(BusCurrState)
|
case(CurrState)
|
||||||
STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
|
ADR_PHASE: if(HREADY & |RW) NextState = DATA_PHASE;
|
||||||
else if (HREADY & CacheRW[0]) BusNextState = STATE_CACHE_EVICT;
|
else if (HREADY & CacheRW[0]) NextState = CACHE_EVICT;
|
||||||
else if (HREADY & CacheRW[1]) BusNextState = STATE_CACHE_FETCH;
|
else if (HREADY & CacheRW[1]) NextState = CACHE_FETCH;
|
||||||
else BusNextState = STATE_READY;
|
else NextState = ADR_PHASE;
|
||||||
STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
|
DATA_PHASE: if(HREADY) NextState = MEM3;
|
||||||
else BusNextState = STATE_CAPTURE;
|
else NextState = DATA_PHASE;
|
||||||
STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
|
MEM3: if(CPUBusy) NextState = MEM3;
|
||||||
else BusNextState = STATE_READY;
|
else NextState = ADR_PHASE;
|
||||||
STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
|
CACHE_FETCH: if(HREADY & FinalWordCount) NextState = ADR_PHASE;
|
||||||
else BusNextState = STATE_READY;
|
else NextState = CACHE_FETCH;
|
||||||
STATE_CACHE_FETCH: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
|
CACHE_EVICT: if(HREADY & FinalWordCount) NextState = ADR_PHASE;
|
||||||
else BusNextState = STATE_CACHE_FETCH;
|
else NextState = CACHE_EVICT;
|
||||||
STATE_CACHE_EVICT: if(HREADY & FinalWordCount) BusNextState = STATE_READY;
|
default: NextState = ADR_PHASE;
|
||||||
else BusNextState = STATE_CACHE_EVICT;
|
|
||||||
default: BusNextState = STATE_READY;
|
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -119,30 +117,30 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
|
|||||||
assign NextWordCount = WordCount + 1'b1;
|
assign NextWordCount = WordCount + 1'b1;
|
||||||
|
|
||||||
assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0];
|
assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0];
|
||||||
assign WordCntEn = ((BusNextState == STATE_CACHE_EVICT | BusNextState == STATE_CACHE_FETCH) & HREADY) |
|
assign WordCntEn = ((NextState == CACHE_EVICT | NextState == CACHE_FETCH) & HREADY) |
|
||||||
(BusNextState == STATE_READY & |CacheRW & HREADY);
|
(NextState == ADR_PHASE & |CacheRW & HREADY);
|
||||||
assign WordCntReset = BusNextState == STATE_READY;
|
assign WordCntReset = NextState == ADR_PHASE;
|
||||||
|
|
||||||
assign CaptureEn = (BusCurrState == STATE_CAPTURE & RW[1]) | (BusCurrState == STATE_CACHE_FETCH & HREADY);
|
assign CaptureEn = (CurrState == DATA_PHASE & RW[1]) | (CurrState == CACHE_FETCH & HREADY);
|
||||||
assign CacheAccess = BusCurrState == STATE_CACHE_FETCH | BusCurrState == STATE_CACHE_EVICT;
|
assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_EVICT;
|
||||||
|
|
||||||
assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) |
|
assign BusStall = (CurrState == ADR_PHASE & (|RW | |CacheRW)) |
|
||||||
(BusCurrState == STATE_CAPTURE) |
|
//(CurrState == DATA_PHASE & ~RW[0]) | // replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
|
||||||
(BusCurrState == STATE_CACHE_FETCH) |
|
(CurrState == DATA_PHASE) |
|
||||||
(BusCurrState == STATE_CACHE_EVICT);
|
(CurrState == CACHE_FETCH) |
|
||||||
assign BusCommitted = BusCurrState != STATE_READY;
|
(CurrState == CACHE_EVICT);
|
||||||
assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) |
|
assign BusCommitted = CurrState != ADR_PHASE;
|
||||||
(BusCurrState == STATE_CAPTURE) |
|
assign SelUncachedAdr = (CurrState == ADR_PHASE & |RW) |
|
||||||
(BusCurrState == STATE_DELAY);
|
(CurrState == DATA_PHASE) |
|
||||||
|
(CurrState == MEM3);
|
||||||
|
|
||||||
// AHB bus interface
|
// AHB bus interface
|
||||||
assign HTRANS = (BusCurrState == STATE_READY & HREADY & (|RW | |CacheRW)) |
|
assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|RW | |CacheRW)) |
|
||||||
(BusCurrState == STATE_CAPTURE & ~HREADY) |
|
(CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ :
|
||||||
(CacheAccess & ~HREADY & ~|WordCount) ? AHB_NONSEQ :
|
(CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
|
||||||
(CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE;
|
|
||||||
|
|
||||||
assign HWRITE = RW[0] | CacheRW[0];
|
assign HWRITE = RW[0] | CacheRW[0];
|
||||||
assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0;
|
assign HBURST = `BURST_EN ? ((|CacheRW) ? LocalBurstType : 3'b0) : 3'b0; // this line is for burst.
|
||||||
|
|
||||||
always_comb begin
|
always_comb begin
|
||||||
case(WordCountThreshold)
|
case(WordCountThreshold)
|
||||||
@ -156,8 +154,8 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
|
|||||||
|
|
||||||
// communication to cache
|
// communication to cache
|
||||||
assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
|
assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount);
|
||||||
assign SelBusWord = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) |
|
assign SelBusWord = (CurrState == ADR_PHASE & (RW[0] | CacheRW[0])) |
|
||||||
(BusCurrState == STATE_CAPTURE & RW[0]) |
|
(CurrState == DATA_PHASE & RW[0]) |
|
||||||
(BusCurrState == STATE_CACHE_EVICT);
|
(CurrState == CACHE_EVICT);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
@ -31,7 +31,7 @@
|
|||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
|
||||||
// HCLK and clk must be the same clock!
|
// HCLK and clk must be the same clock!
|
||||||
module AHBBusfsm
|
module busfsm
|
||||||
(input logic HCLK,
|
(input logic HCLK,
|
||||||
input logic HRESETn,
|
input logic HRESETn,
|
||||||
|
|
||||||
@ -46,41 +46,39 @@ module AHBBusfsm
|
|||||||
output logic HWRITE
|
output logic HWRITE
|
||||||
);
|
);
|
||||||
|
|
||||||
typedef enum logic [2:0] {STATE_READY,
|
typedef enum logic [2:0] {ADR_PHASE,
|
||||||
STATE_CAPTURE,
|
DATA_PHASE,
|
||||||
STATE_DELAY,
|
MEM3} busstatetype;
|
||||||
STATE_CPU_BUSY} busstatetype;
|
|
||||||
|
|
||||||
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
|
typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
|
||||||
|
|
||||||
(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
|
(* mark_debug = "true" *) busstatetype CurrState, NextState;
|
||||||
|
|
||||||
always_ff @(posedge HCLK)
|
always_ff @(posedge HCLK)
|
||||||
if (~HRESETn) BusCurrState <= #1 STATE_READY;
|
if (~HRESETn) CurrState <= #1 ADR_PHASE;
|
||||||
else BusCurrState <= #1 BusNextState;
|
else CurrState <= #1 NextState;
|
||||||
|
|
||||||
always_comb begin
|
always_comb begin
|
||||||
case(BusCurrState)
|
case(CurrState)
|
||||||
STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE;
|
ADR_PHASE: if(HREADY & |RW) NextState = DATA_PHASE;
|
||||||
else BusNextState = STATE_READY;
|
else NextState = ADR_PHASE;
|
||||||
STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY;
|
DATA_PHASE: if(HREADY) NextState = MEM3;
|
||||||
else BusNextState = STATE_CAPTURE;
|
else NextState = DATA_PHASE;
|
||||||
STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
|
MEM3: if(CPUBusy) NextState = MEM3;
|
||||||
else BusNextState = STATE_READY;
|
else NextState = ADR_PHASE;
|
||||||
STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY;
|
default: NextState = ADR_PHASE;
|
||||||
else BusNextState = STATE_READY;
|
|
||||||
default: BusNextState = STATE_READY;
|
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
assign BusStall = (BusCurrState == STATE_READY & |RW) |
|
assign BusStall = (CurrState == ADR_PHASE & |RW) |
|
||||||
(BusCurrState == STATE_CAPTURE);
|
// (CurrState == DATA_PHASE & ~RW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
|
||||||
|
(CurrState == DATA_PHASE);
|
||||||
|
|
||||||
assign BusCommitted = BusCurrState != STATE_READY;
|
assign BusCommitted = CurrState != ADR_PHASE;
|
||||||
|
|
||||||
assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) |
|
assign HTRANS = (CurrState == ADR_PHASE & HREADY & |RW) |
|
||||||
(BusCurrState == STATE_CAPTURE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
|
(CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE;
|
||||||
assign HWRITE = (BusCurrState == STATE_READY) & RW[0]; // *** might not be necessary, maybe just RW[0]
|
assign HWRITE = RW[0];
|
||||||
assign CaptureEn = BusCurrState == STATE_CAPTURE;
|
assign CaptureEn = CurrState == DATA_PHASE;
|
||||||
|
|
||||||
endmodule
|
endmodule
|
@ -47,13 +47,13 @@ module managerinputstage
|
|||||||
input logic [2:0] HBURSTin,
|
input logic [2:0] HBURSTin,
|
||||||
input logic [1:0] HTRANSin,
|
input logic [1:0] HTRANSin,
|
||||||
input logic [`PA_BITS-1:0] HADDRin,
|
input logic [`PA_BITS-1:0] HADDRin,
|
||||||
output logic HREADYRestore,
|
output logic HREADYOut,
|
||||||
// manager output
|
// manager output
|
||||||
output logic HWRITERestore,
|
output logic HWRITEOut,
|
||||||
output logic [2:0] HSIZERestore,
|
output logic [2:0] HSIZEOut,
|
||||||
output logic [2:0] HBURSTRestore,
|
output logic [2:0] HBURSTOut,
|
||||||
output logic [1:0] HTRANSRestore,
|
output logic [1:0] HTRANSOut,
|
||||||
output logic [`PA_BITS-1:0] HADDRRestore,
|
output logic [`PA_BITS-1:0] HADDROut,
|
||||||
input logic HREADYin
|
input logic HREADYin
|
||||||
);
|
);
|
||||||
|
|
||||||
@ -69,11 +69,11 @@ module managerinputstage
|
|||||||
mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin},
|
mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEin, HSIZEin, HBURSTin, HTRANSin, HADDRin},
|
||||||
{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
|
{HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
|
||||||
Restore,
|
Restore,
|
||||||
{HWRITERestore, HSIZERestore, HBURSTRestore, HTRANSRestore, HADDRRestore});
|
{HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
|
||||||
|
|
||||||
assign Request = HTRANSRestore != 2'b00;
|
assign Request = HTRANSOut != 2'b00;
|
||||||
assign HREADYRestore = HREADYin & ~Disable;
|
assign HREADYOut = HREADYin & ~Disable;
|
||||||
assign Active = Request & HREADYRestore;
|
assign Active = Request & HREADYOut;
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
@ -40,7 +40,7 @@ module synchronizer (
|
|||||||
|
|
||||||
always_ff @(posedge clk) begin
|
always_ff @(posedge clk) begin
|
||||||
mid <= #1 d;
|
mid <= #1 d;
|
||||||
q <= #1 d;
|
q <= #1 mid;
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
@ -36,7 +36,8 @@ module brom1p1r
|
|||||||
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
||||||
parameter ADDR_WIDTH = 8,
|
parameter ADDR_WIDTH = 8,
|
||||||
// Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth
|
// Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth
|
||||||
parameter DATA_WIDTH = 32 // Data Width in bits
|
parameter DATA_WIDTH = 32, // Data Width in bits
|
||||||
|
parameter PRELOAD_ENABLED = 0
|
||||||
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
||||||
) (
|
) (
|
||||||
input logic clk,
|
input logic clk,
|
||||||
@ -49,4 +50,53 @@ module brom1p1r
|
|||||||
always @ (posedge clk) begin
|
always @ (posedge clk) begin
|
||||||
dout <= ROM[addr];
|
dout <= ROM[addr];
|
||||||
end
|
end
|
||||||
|
|
||||||
|
if(PRELOAD_ENABLED) begin
|
||||||
|
initial begin
|
||||||
|
ROM[0] = 64'h9581819300002197;
|
||||||
|
ROM[1] = 64'h4281420141014081;
|
||||||
|
ROM[2] = 64'h4481440143814301;
|
||||||
|
ROM[3] = 64'h4681460145814501;
|
||||||
|
ROM[4] = 64'h4881480147814701;
|
||||||
|
ROM[5] = 64'h4a814a0149814901;
|
||||||
|
ROM[6] = 64'h4c814c014b814b01;
|
||||||
|
ROM[7] = 64'h4e814e014d814d01;
|
||||||
|
ROM[8] = 64'h0110011b4f814f01;
|
||||||
|
ROM[9] = 64'h059b45011161016e;
|
||||||
|
ROM[10] = 64'h0004063705fe0010;
|
||||||
|
ROM[11] = 64'h05a000ef8006061b;
|
||||||
|
ROM[12] = 64'h0ff003930000100f;
|
||||||
|
ROM[13] = 64'h4e952e3110060e37;
|
||||||
|
ROM[14] = 64'hc602829b0053f2b7;
|
||||||
|
ROM[15] = 64'h2023fe02dfe312fd;
|
||||||
|
ROM[16] = 64'h829b0053f2b7007e;
|
||||||
|
ROM[17] = 64'hfe02dfe312fdc602;
|
||||||
|
ROM[18] = 64'h4de31efd000e2023;
|
||||||
|
ROM[19] = 64'h059bf1402573fdd0;
|
||||||
|
ROM[20] = 64'h0000061705e20870;
|
||||||
|
ROM[21] = 64'h0010029b01260613;
|
||||||
|
ROM[22] = 64'h11010002806702fe;
|
||||||
|
ROM[23] = 64'h84b2842ae426e822;
|
||||||
|
ROM[24] = 64'h892ee04aec064511;
|
||||||
|
ROM[25] = 64'h06e000ef07e000ef;
|
||||||
|
ROM[26] = 64'h979334fd02905563;
|
||||||
|
ROM[27] = 64'h07930177d4930204;
|
||||||
|
ROM[28] = 64'h4089093394be2004;
|
||||||
|
ROM[29] = 64'h04138522008905b3;
|
||||||
|
ROM[30] = 64'h19e3014000ef2004;
|
||||||
|
ROM[31] = 64'h64a2644260e2fe94;
|
||||||
|
ROM[32] = 64'h6749808261056902;
|
||||||
|
ROM[33] = 64'hdfed8b8510472783;
|
||||||
|
ROM[34] = 64'h2423479110a73823;
|
||||||
|
ROM[35] = 64'h10472783674910f7;
|
||||||
|
ROM[36] = 64'h20058693ffed8b89;
|
||||||
|
ROM[37] = 64'h05a1118737836749;
|
||||||
|
ROM[38] = 64'hfed59be3fef5bc23;
|
||||||
|
ROM[39] = 64'h1047278367498082;
|
||||||
|
ROM[40] = 64'h47858082dfed8b85;
|
||||||
|
ROM[41] = 64'h40a7853b4015551b;
|
||||||
|
ROM[42] = 64'h808210a7a02367c9;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
endmodule // bytewrite_tdp_ram_rf
|
endmodule // bytewrite_tdp_ram_rf
|
||||||
|
@ -230,8 +230,8 @@ module ifu (
|
|||||||
.NextAdr(PCNextFSpill[11:0]),
|
.NextAdr(PCNextFSpill[11:0]),
|
||||||
.PAdr(PCPF),
|
.PAdr(PCPF),
|
||||||
.CacheCommitted(), .InvalidateCache(InvalidateICacheM));
|
.CacheCommitted(), .InvalidateCache(InvalidateICacheM));
|
||||||
AHBCachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
|
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
|
||||||
cachedp(.HCLK(clk), .HRESETn(~reset),
|
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
|
||||||
.HRDATA,
|
.HRDATA,
|
||||||
.CacheRW, .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
|
.CacheRW, .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
|
||||||
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
|
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
|
||||||
@ -248,11 +248,11 @@ module ifu (
|
|||||||
logic CaptureEn;
|
logic CaptureEn;
|
||||||
logic [1:0] RW;
|
logic [1:0] RW;
|
||||||
assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF};
|
assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF};
|
||||||
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
|
|
||||||
|
|
||||||
|
ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY),
|
||||||
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW, .CaptureEn,
|
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
|
||||||
.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
|
.HWSTRB(), .RW, .ByteMask(), .WriteData('0),
|
||||||
|
.CPUBusy, .BusStall, .BusCommitted(), .ReadDataWord(AllInstrRawF[31:0]));
|
||||||
|
|
||||||
assign IFUHBURST = 3'b0;
|
assign IFUHBURST = 3'b0;
|
||||||
assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
|
assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
|
||||||
|
@ -259,7 +259,7 @@ module lsu (
|
|||||||
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
|
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
|
||||||
.FetchBuffer, .CacheFetchLine(DCacheFetchLine),
|
.FetchBuffer, .CacheFetchLine(DCacheFetchLine),
|
||||||
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
|
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
|
||||||
AHBCachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) cachedp(
|
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) ahbcacheinterface(
|
||||||
.HCLK(clk), .HRESETn(~reset),
|
.HCLK(clk), .HRESETn(~reset),
|
||||||
.HRDATA,
|
.HRDATA,
|
||||||
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
|
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
|
||||||
@ -274,7 +274,7 @@ module lsu (
|
|||||||
mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
|
mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
|
||||||
.s(SelUncachedAdr), .y(LSUHWDATA_noDELAY));
|
.s(SelUncachedAdr), .y(LSUHWDATA_noDELAY));
|
||||||
|
|
||||||
flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
flopen #(`XLEN) wdreg(clk, LSUHREADY, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
||||||
|
|
||||||
// *** bummer need a second byte mask for bus as it is XLEN rather than LLEN.
|
// *** bummer need a second byte mask for bus as it is XLEN rather than LLEN.
|
||||||
// probably can merge by muxing LSUPAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
|
// probably can merge by muxing LSUPAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
|
||||||
@ -283,7 +283,6 @@ module lsu (
|
|||||||
|
|
||||||
flop #(`XLEN/8) HWSTRBReg(clk, BusByteMaskM[`XLEN/8-1:0], LSUHWSTRB);
|
flop #(`XLEN/8) HWSTRBReg(clk, BusByteMaskM[`XLEN/8-1:0], LSUHWSTRB);
|
||||||
|
|
||||||
|
|
||||||
end else begin : passthrough // just needs a register to hold the value from the bus
|
end else begin : passthrough // just needs a register to hold the value from the bus
|
||||||
logic CaptureEn;
|
logic CaptureEn;
|
||||||
logic [1:0] RW;
|
logic [1:0] RW;
|
||||||
@ -292,14 +291,10 @@ module lsu (
|
|||||||
assign LSUHADDR = LSUPAdrM;
|
assign LSUHADDR = LSUPAdrM;
|
||||||
assign LSUHSIZE = LSUFunct3M;
|
assign LSUHSIZE = LSUFunct3M;
|
||||||
|
|
||||||
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(ReadDataWordM));
|
ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(LSUHREADY),
|
||||||
|
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
|
||||||
flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
.HWSTRB(LSUHWSTRB), .RW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
|
||||||
flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB);
|
.CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .ReadDataWord(ReadDataWordM));
|
||||||
|
|
||||||
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW,
|
|
||||||
.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
|
|
||||||
.HWRITE(LSUHWRITE));
|
|
||||||
|
|
||||||
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
|
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
|
||||||
assign LSUHBURST = 3'b0;
|
assign LSUHBURST = 3'b0;
|
||||||
@ -333,8 +328,7 @@ module lsu (
|
|||||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
|
subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
|
||||||
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
|
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
|
||||||
subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
|
subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
|
||||||
.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
|
|
||||||
|
|
||||||
// Compute byte masks
|
// Compute byte masks
|
||||||
swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
|
swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
|
||||||
|
@ -31,7 +31,6 @@
|
|||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
|
||||||
module subwordwrite (
|
module subwordwrite (
|
||||||
input logic [2:0] LSUPAdrM,
|
|
||||||
input logic [2:0] LSUFunct3M,
|
input logic [2:0] LSUFunct3M,
|
||||||
input logic [`LLEN-1:0] IMAFWriteDataM,
|
input logic [`LLEN-1:0] IMAFWriteDataM,
|
||||||
output logic [`LLEN-1:0] LittleEndianWriteDataM);
|
output logic [`LLEN-1:0] LittleEndianWriteDataM);
|
||||||
|
@ -29,6 +29,7 @@
|
|||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
`define RAM_LATENCY 0
|
||||||
|
|
||||||
module ram_ahb #(parameter BASE=0, RANGE = 65535) (
|
module ram_ahb #(parameter BASE=0, RANGE = 65535) (
|
||||||
input logic HCLK, HRESETn,
|
input logic HCLK, HRESETn,
|
||||||
@ -51,10 +52,11 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
|
|||||||
logic initTrans;
|
logic initTrans;
|
||||||
logic memwrite, memwriteD, memread;
|
logic memwrite, memwriteD, memread;
|
||||||
logic nextHREADYRam;
|
logic nextHREADYRam;
|
||||||
|
logic DelayReady;
|
||||||
|
|
||||||
// a new AHB transactions starts when HTRANS requests a transaction,
|
// a new AHB transactions starts when HTRANS requests a transaction,
|
||||||
// the peripheral is selected, and the previous transaction is completing
|
// the peripheral is selected, and the previous transaction is completing
|
||||||
assign initTrans = HREADY & HSELRam & HTRANS[1];
|
assign initTrans = HREADY & HSELRam & HTRANS[1] ;
|
||||||
assign memwrite = initTrans & HWRITE;
|
assign memwrite = initTrans & HWRITE;
|
||||||
assign memread = initTrans & ~HWRITE;
|
assign memread = initTrans & ~HWRITE;
|
||||||
|
|
||||||
@ -62,8 +64,9 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
|
|||||||
flopenr #(`PA_BITS) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
|
flopenr #(`PA_BITS) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
|
||||||
|
|
||||||
// Stall on a read after a write because the RAM can't take both adddresses on the same cycle
|
// Stall on a read after a write because the RAM can't take both adddresses on the same cycle
|
||||||
assign nextHREADYRam = ~(memwriteD & memread);
|
assign nextHREADYRam = (~(memwriteD & memread)) & ~DelayReady;
|
||||||
flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
|
flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
|
||||||
|
|
||||||
assign HRESPRam = 0; // OK
|
assign HRESPRam = 0; // OK
|
||||||
|
|
||||||
// On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
|
// On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
|
||||||
@ -72,5 +75,41 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
|
|||||||
// single-ported RAM
|
// single-ported RAM
|
||||||
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH, `FPGA)
|
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH, `FPGA)
|
||||||
memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
|
memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
|
||||||
|
|
||||||
|
// use this to add arbitrary latency to ram. Helps test AHB controller correctness
|
||||||
|
if(`RAM_LATENCY > 0) begin
|
||||||
|
logic [7:0] NextCycle, Cycle;
|
||||||
|
logic CntEn, CntRst;
|
||||||
|
logic CycleFlag;
|
||||||
|
|
||||||
|
flopenr #(8) counter (HCLK, ~HRESETn | CntRst, CntEn, NextCycle, Cycle);
|
||||||
|
assign NextCycle = Cycle + 1'b1;
|
||||||
|
|
||||||
|
typedef enum logic {READY, DELAY} statetype;
|
||||||
|
statetype CurrState, NextState;
|
||||||
|
|
||||||
|
always_ff @(posedge HCLK)
|
||||||
|
if (~HRESETn) CurrState <= #1 READY;
|
||||||
|
else CurrState <= #1 NextState;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
case(CurrState)
|
||||||
|
READY: if(initTrans & ~CycleFlag) NextState = DELAY;
|
||||||
|
else NextState = READY;
|
||||||
|
DELAY: if(CycleFlag) NextState = READY;
|
||||||
|
else NextState = DELAY;
|
||||||
|
default: NextState = READY;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
assign CycleFlag = Cycle == `RAM_LATENCY;
|
||||||
|
assign CntEn = NextState == DELAY;
|
||||||
|
assign DelayReady = NextState == DELAY;
|
||||||
|
assign CntRst = NextState == READY;
|
||||||
|
end else begin
|
||||||
|
assign DelayReady = 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
@ -48,7 +48,7 @@ module rom_ahb #(parameter BASE=0, RANGE = 65535) (
|
|||||||
assign HRESPRom = 0; // OK
|
assign HRESPRom = 0; // OK
|
||||||
|
|
||||||
// single-ported ROM
|
// single-ported ROM
|
||||||
brom1p1r #(ADDR_WIDTH, `XLEN)
|
brom1p1r #(ADDR_WIDTH, `XLEN, `FPGA)
|
||||||
memory(.clk(HCLK), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
|
memory(.clk(HCLK), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
@ -197,7 +197,12 @@ module uncore (
|
|||||||
HSELNoneD; // don't lock up the bus if no region is being accessed
|
HSELNoneD; // don't lock up the bus if no region is being accessed
|
||||||
|
|
||||||
// Address Decoder Delay (figure 4-2 in spec)
|
// Address Decoder Delay (figure 4-2 in spec)
|
||||||
flopr #(11) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
|
// The select for HREADY needs to be based on the address phase address. If the device
|
||||||
|
// takes more than 1 cycle to repsond it needs to hold on to the old select until the
|
||||||
|
// device is ready. Hense this register must be selectively enabled by HREADY.
|
||||||
|
// However on reset None must be seleted.
|
||||||
|
flopenr #(10) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:1], {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
|
||||||
|
flopenl #(1) hseldelayreg2(HCLK, ~HRESETn, HREADY, HSELRegions[0], 1'b1, HSELNoneD);
|
||||||
flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
|
flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user