diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv
index 3509b5b0b..d4029fafa 100644
--- a/wally-pipelined/src/uncore/uartPC16550D.sv
+++ b/wally-pipelined/src/uncore/uartPC16550D.sv
@@ -377,7 +377,8 @@ module uartPC16550D(
           txhrfull <= #1 1;
         end
         $write("%c",Din); // for testbench
-        if (Din == 13) $fflush;
+        //if (Din == 13) $fflush;
+        $fflush;
       end
       if (txstate == UART_IDLE) begin // move data into tx shift register if available
         if (fifoenabled) begin