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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2022-09-18 21:27:36 -07:00
commit cff3c2535d
13 changed files with 698 additions and 167 deletions
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213
fpga/constraints/debug2.xdc
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File diff suppressed because one or more lines are too long

86
fpga/src/fpgaTop.v
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@ -70,21 +70,21 @@ module fpgaTop
wire peripheral_aresetn; wire peripheral_aresetn;
wire mb_reset; wire mb_reset;
wire [`AHBW-1:0] HRDATAEXT;
wire HREADYEXT;
wire HRESPEXT;
wire HSELEXT;
wire HCLKOpen; wire HCLKOpen;
wire HRESETnOpen; wire HRESETnOpen;
wire [31:0] HADDR; (* mark_debug = "true" *) wire [`AHBW-1:0] HRDATAEXT;
wire [`AHBW-1:0] HWDATA; (* mark_debug = "true" *) wire HREADYEXT;
wire HWRITE; (* mark_debug = "true" *) wire HRESPEXT;
wire [2:0] HSIZE; (* mark_debug = "true" *) wire HSELEXT;
wire [2:0] HBURST; (* mark_debug = "true" *) wire [31:0] HADDR;
(* mark_debug = "true" *) wire [`AHBW-1:0] HWDATA;
(* mark_debug = "true" *) wire HWRITE;
(* mark_debug = "true" *) wire [2:0] HSIZE;
(* mark_debug = "true" *) wire [2:0] HBURST;
(* mark_debug = "true" *) wire [1:0] HTRANS;
(* mark_debug = "true" *) wire HREADY;
wire [3:0] HPROT; wire [3:0] HPROT;
wire [1:0] HTRANS;
wire HMASTLOCK; wire HMASTLOCK;
wire HREADY;
@ -94,41 +94,41 @@ module fpgaTop
wire SDCCmdOE; wire SDCCmdOE;
wire SDCCmdOut; wire SDCCmdOut;
wire [3:0] m_axi_awid; (* mark_debug = "true" *) wire [3:0] m_axi_awid;
wire [7:0] m_axi_awlen; (* mark_debug = "true" *) wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize; (* mark_debug = "true" *) wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst; (* mark_debug = "true" *) wire [1:0] m_axi_awburst;
wire [3:0] m_axi_awcache; (* mark_debug = "true" *) wire [3:0] m_axi_awcache;
wire [31:0] m_axi_awaddr; (* mark_debug = "true" *) wire [31:0] m_axi_awaddr;
wire [2:0] m_axi_awprot; wire [2:0] m_axi_awprot;
wire m_axi_awvalid; (* mark_debug = "true" *) wire m_axi_awvalid;
wire m_axi_awready; (* mark_debug = "true" *) wire m_axi_awready;
wire m_axi_awlock; (* mark_debug = "true" *) wire m_axi_awlock;
wire [63:0] m_axi_wdata; (* mark_debug = "true" *) wire [63:0] m_axi_wdata;
wire [7:0] m_axi_wstrb; (* mark_debug = "true" *) wire [7:0] m_axi_wstrb;
wire m_axi_wlast; (* mark_debug = "true" *) wire m_axi_wlast;
wire m_axi_wvalid; (* mark_debug = "true" *) wire m_axi_wvalid;
wire m_axi_wready; (* mark_debug = "true" *) wire m_axi_wready;
wire [3:0] m_axi_bid; (* mark_debug = "true" *) wire [3:0] m_axi_bid;
wire [1:0] m_axi_bresp; (* mark_debug = "true" *) wire [1:0] m_axi_bresp;
wire m_axi_bvalid; (* mark_debug = "true" *) wire m_axi_bvalid;
wire m_axi_bready; (* mark_debug = "true" *) wire m_axi_bready;
wire [3:0] m_axi_arid; (* mark_debug = "true" *) wire [3:0] m_axi_arid;
wire [7:0] m_axi_arlen; (* mark_debug = "true" *) wire [7:0] m_axi_arlen;
wire [2:0] m_axi_arsize; (* mark_debug = "true" *) wire [2:0] m_axi_arsize;
wire [1:0] m_axi_arburst; (* mark_debug = "true" *) wire [1:0] m_axi_arburst;
wire [2:0] m_axi_arprot; wire [2:0] m_axi_arprot;
wire [3:0] m_axi_arcache; (* mark_debug = "true" *) wire [3:0] m_axi_arcache;
wire m_axi_arvalid; (* mark_debug = "true" *) wire m_axi_arvalid;
wire [31:0] m_axi_araddr; (* mark_debug = "true" *) wire [31:0] m_axi_araddr;
wire m_axi_arlock; wire m_axi_arlock;
wire m_axi_arready; (* mark_debug = "true" *) wire m_axi_arready;
wire [3:0] m_axi_rid; (* mark_debug = "true" *) wire [3:0] m_axi_rid;
wire [63:0] m_axi_rdata; (* mark_debug = "true" *) wire [63:0] m_axi_rdata;
wire [1:0] m_axi_rresp; (* mark_debug = "true" *) wire [1:0] m_axi_rresp;
wire m_axi_rvalid; (* mark_debug = "true" *) wire m_axi_rvalid;
wire m_axi_rlast; (* mark_debug = "true" *) wire m_axi_rlast;
wire m_axi_rready; (* mark_debug = "true" *) wire m_axi_rready;
wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arregion;
wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_arqos;

3
pipelined/src/ebu/ahbinterface.sv
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@ -34,7 +34,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbinterface #(parameter WRITEABLE = 0) module ahbinterface #(parameter WRITEABLE = 0) // **** modify to use LSU/ifu parameter to control widths of buses
( (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
@ -57,6 +57,7 @@ module ahbinterface #(parameter WRITEABLE = 0)
logic CaptureEn; logic CaptureEn;
/// *** only 32 bit for IFU.
flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWord)); flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWord));
if(WRITEABLE) begin if(WRITEABLE) begin

26
pipelined/src/ebu/ahbmulticontroller.sv
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@ -41,6 +41,7 @@ module ahbmulticontroller
input logic clk, reset, input logic clk, reset,
// Signals from IFU // Signals from IFU
input logic [`PA_BITS-1:0] IFUHADDR, input logic [`PA_BITS-1:0] IFUHADDR,
input logic [2:0] IFUHSIZE,
input logic [2:0] IFUHBURST, input logic [2:0] IFUHBURST,
input logic [1:0] IFUHTRANS, input logic [1:0] IFUHTRANS,
output logic IFUHREADY, output logic IFUHREADY,
@ -69,28 +70,23 @@ module ahbmulticontroller
(* mark_debug = "true" *) output logic HMASTLOCK (* mark_debug = "true" *) output logic HMASTLOCK
); );
localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator
typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; typedef enum logic [1:0] {IDLE, ARBITRATE} statetype;
statetype CurrState, NextState; statetype CurrState, NextState;
logic LSUGrant;
logic [ADRBITS-1:0] HADDRD;
logic [1:0] HSIZED;
logic [1:0] save, restore, dis, sel; logic [1:0] save, restore, dis, sel;
logic both; logic both;
logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDROut; logic [`PA_BITS-1:0] IFUHADDROut;
logic [1:0] IFUHTRANSSave, IFUHTRANSOut; logic [1:0] IFUHTRANSOut;
logic [2:0] IFUHBURSTSave, IFUHBURSTOut; logic [2:0] IFUHBURSTOut;
logic [2:0] IFUHSIZEOut; logic [2:0] IFUHSIZEOut;
logic IFUHWRITEOut; logic IFUHWRITEOut;
logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDROut; logic [`PA_BITS-1:0] LSUHADDROut;
logic [1:0] LSUHTRANSSave, LSUHTRANSOut; logic [1:0] LSUHTRANSOut;
logic [2:0] LSUHBURSTSave, LSUHBURSTOut; logic [2:0] LSUHBURSTOut;
logic [2:0] LSUHSIZESave, LSUHSIZEOut; logic [2:0] LSUHSIZEOut;
logic LSUHWRITESave, LSUHWRITEOut; logic LSUHWRITEOut;
logic IFUReq, LSUReq; logic IFUReq, LSUReq;
logic IFUActive, LSUActive; logic IFUActive, LSUActive;
@ -112,7 +108,7 @@ module ahbmulticontroller
// input stage IFU // input stage IFU
controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]), controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
.Request(IFUReq), .Active(IFUActive), .Request(IFUReq), .Active(IFUActive),
.HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR), .HWRITEin(1'b0), .HSIZEin(IFUHSIZE), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY)); .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
@ -125,7 +121,7 @@ module ahbmulticontroller
// output mux //*** rewrite for general number of controllers. // output mux //*** rewrite for general number of controllers.
assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0; assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0;
assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? IFUHSIZEOut: '0;
assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
assign HTRANS = sel[1] ? LSUHTRANSOut : sel[0] ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HTRANS = sel[1] ? LSUHTRANSOut : sel[0] ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
assign HWRITE = sel[1] ? LSUHWRITEOut : sel[0] ? 1'b0 : '0; assign HWRITE = sel[1] ? LSUHWRITEOut : sel[0] ? 1'b0 : '0;

4
pipelined/src/ifu/ifu.sv
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@ -41,6 +41,7 @@ module ifu (
(* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic IFUStallF,
(* mark_debug = "true" *) output logic [2:0] IFUHBURST, (* mark_debug = "true" *) output logic [2:0] IFUHBURST,
(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, (* mark_debug = "true" *) output logic [1:0] IFUHTRANS,
(* mark_debug = "true" *) output logic [2:0] IFUHSIZE,
(* mark_debug = "true" *) output logic IFUHWRITE, (* mark_debug = "true" *) output logic IFUHWRITE,
(* mark_debug = "true" *) input logic IFUHREADY, (* mark_debug = "true" *) input logic IFUHREADY,
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
@ -234,7 +235,7 @@ module ifu (
ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE)
ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
.HRDATA, .HRDATA,
.CacheRW, .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .CacheRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS),
.Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
.WordCount(), .SelUncachedAdr, .SelBusWord(), .WordCount(), .SelUncachedAdr, .SelBusWord(),
.CacheBusAck(ICacheBusAck), .CacheBusAck(ICacheBusAck),
@ -249,6 +250,7 @@ module ifu (
logic CaptureEn; logic CaptureEn;
logic [1:0] RW; logic [1:0] RW;
assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}; assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF};
assign IFUHSIZE = 3'b010;
ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY),
.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),

3
pipelined/src/lsu/lsu.sv
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@ -216,7 +216,8 @@ module lsu (
assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
assign DTIMAccessRW = |MemRWM; assign DTIMAccessRW = |MemRWM;
// *** Ross remove this.
adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); // maybe we pull this out of the mmu? adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); // maybe we pull this out of the mmu?
//assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected //assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected
assign NonDTIMMemRWM = MemRWM; // *** fix assign NonDTIMMemRWM = MemRWM; // *** fix

24
pipelined/src/wally/wallypipelinedcore.sv
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@ -132,18 +132,19 @@ module wallypipelinedcore (
logic CommittedM; logic CommittedM;
// AHB ifu interface // AHB ifu interface
logic [`PA_BITS-1:0] IFUHADDR; logic [`PA_BITS-1:0] IFUHADDR;
logic [2:0] IFUHBURST; logic [2:0] IFUHBURST;
logic [1:0] IFUHTRANS; logic [1:0] IFUHTRANS;
logic IFUHWRITE; logic [2:0] IFUHSIZE;
logic IFUHREADY; logic IFUHWRITE;
logic IFUHREADY;
// AHB LSU interface // AHB LSU interface
logic [`PA_BITS-1:0] LSUHADDR; logic [`PA_BITS-1:0] LSUHADDR;
logic [`XLEN-1:0] LSUHWDATA; logic [`XLEN-1:0] LSUHWDATA;
logic [`XLEN/8-1:0] LSUHWSTRB; logic [`XLEN/8-1:0] LSUHWSTRB;
logic LSUHWRITE; logic LSUHWRITE;
logic LSUHREADY; logic LSUHREADY;
logic BPPredWrongE; logic BPPredWrongE;
logic BPPredDirWrongM; logic BPPredDirWrongM;
@ -172,7 +173,7 @@ module wallypipelinedcore (
.FlushF, .FlushD, .FlushE, .FlushM, .FlushF, .FlushD, .FlushE, .FlushM,
// Fetch // Fetch
.HRDATA, .PCF, .IFUHADDR, .HRDATA, .PCF, .IFUHADDR,
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE,
.IFUHREADY, .IFUHWRITE, .IFUHREADY, .IFUHWRITE,
.ICacheAccess, .ICacheMiss, .ICacheAccess, .ICacheMiss,
@ -295,6 +296,7 @@ module wallypipelinedcore (
.IFUHBURST, .IFUHBURST,
.IFUHTRANS, .IFUHTRANS,
.IFUHREADY, .IFUHREADY,
.IFUHSIZE,
// LSU interface // LSU interface
.LSUHADDR, .LSUHADDR,
.LSUHWDATA, .LSUHWDATA,

25
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output Normal file
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@ -0,0 +1,25 @@
aabbccdd # Test 5.3.2.4: M mode little endian load/store word of 0xAABBCCDD # NOTE: the memory was already filled with's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's
deadccdd # M mode little endian load/store halfword of 0xAABBCCDD # NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension
deadbedd # M mode little endian load/store byte of 0xAABBCCDD
ddccbbaa # M mode big endian load/store word of 0xDDCCBBAA
deadbbaa # M mode big endian load/store halfword of 0xDDCCBBAA
deadbeaa # M mode big endian load/store byte of 0xDDCCBBAA
0000000b # ecall after going from M mode to S mode
aabbccdd # S mode little endian load/store word of 0xAABBCCDD
deadccdd # S mode little endian load/store halfword of 0xAABBCCDD
deadbedd # S mode little endian load/store byte of 0xAABBCCDD
00000009 # ecall after going from S mode to M mode
0000000b # ecall after going from M mode to S mode
ddccbbaa # S mode big endian load/store word of 0xDDCCBBAA
deadbbaa # S mode big endian load/store halfword of 0xDDCCBBAA
deadbeaa # S mode big endian load/store byte of 0xDDCCBBAA
00000009 # ecall after going from S mode to U mode
aabbccdd # U mode little endian load/store word of 0xAABBCCDD
deadccdd # U mode little endian load/store halfword of 0xAABBCCDD
deadbedd # U mode little endian load/store byte of 0xAABBCCDD
00000008 # ecall after going from U mode to M mode
0000000b # ecall after going from M mode to U mode
ddccbbaa # U mode big endian load/store word of 0xDDCCBBAA
deadbbaa # U mode big endian load/store halfword of 0xDDCCBBAA
deadbeaa # U mode big endian load/store byte of 0xDDCCBBAA
00000008 # ecall after ending tests in U mode

192
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S Normal file
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@ -0,0 +1,192 @@
///////////////////////////////////////////
//
// WALLY-endianness
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-09-05
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
RVTEST_ISA("RV32I")
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",endianness)
INIT_TESTS
TRAP_HANDLER m
// Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go
// correctly with the relevant status bit indicating endianness for each mode.
// do this by going to each mode with and testing loads with the big endian bit on and off work correctly
// *** It appears Sail has the MBE, SBE, and UBE bits of mstatus hardwired to zero
// M Mode little Endianness tests:
li x28, 0xAABBCCDD
li x29, 0x8000F000
sw x28, 0(x29) // value stored in memory as 0xAABBCCDD
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xAABBCCDD
addi t1, t1, 4
addi a6, a6, 4
lh x30, 0(x29) // test load half, should read out 0xCCDD
sh x30, 0(t1) // test store half, should save 0xCCDD
addi t1, t1, 4
addi a6, a6, 4
lb x30, 0(x29) // test load byte, should read out 0xDD
sb x30, 0(t1) // test store byte, should save 0xDD
addi t1, t1, 4
addi a6, a6, 4
li x28, 0x2000000000
csrs mstatus, x28 // turn on big endianness for M mode
// M mode Big Endianness tests
// In big endian modes, all values are sign extended to the right, rather than left
li x28, 0xAABBCCDD
li x29, 0x8000F000
sw x28, 0(x29) // value stored in memory as 0xDDCCBBAA
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xDDCCBBAA
addi t1, t1, 4
addi a6, a6, 4
lh x30, 0(x29) // test load half, should read out 0xAABB
sh x30, 0(t1) // test store half, should save 0xBBAA
addi t1, t1, 4
addi a6, a6, 4
lb x30, 0(x29) // test load byte, should read out 0xAA
sb x30, 0(t1) // test store byte, should save 0xAA
addi t1, t1, 4
addi a6, a6, 4
li x28, 0x2000000000
csrc mstatus, x28 // Turn off big endianness for M mode before going into the trap handler
GOTO_S_MODE
// S mode Little endian tests
li x28, 0xAABBCCDD
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0xAABBCCDD
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xAABBCCDD
addi t1, t1, 4
addi a6, a6, 4
lh x30, 0(x29) // test load half, should read out 0xCCDD
sh x30, 0(t1) // test store half, should save 0xCCDD
addi t1, t1, 4
addi a6, a6, 4
lb x30, 0(x29) // test load byte, should read out 0xDD
sb x30, 0(t1) // test store byte, should save 0xDD
addi t1, t1, 4
addi a6, a6, 4
GOTO_M_MODE // Go back to M mode to be able to toggle SBE bit of mstatus
li x28, 0x1000000000
csrs mstatus, x28 // turn on big endianness for S mode
GOTO_S_MODE
// S mode Big endian tests
li x28, 0xAABBCCDD
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xDDCCBBAA
addi t1, t1, 4
addi a6, a6, 4
lh x30, 0(x29) // test load half, should read out 0xAABB
sh x30, 0(t1) // test store half, should save 0xBBAA
addi t1, t1, 4
addi a6, a6, 4
lb x30, 0(x29) // test load byte, should read out 0xAA
sb x30, 0(t1) // test store byte, should save 0xAA
addi t1, t1, 4
addi a6, a6, 4
GOTO_U_MODE
// U mode Little endian tests
li x28, 0xAABBCCDD
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0xAABBCCDD
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xAABBCCDD
addi t1, t1, 4
addi a6, a6, 4
lh x30, 0(x29) // test load half, should read out 0xCCDD
sh x30, 0(t1) // test store half, should save 0xCCDD
addi t1, t1, 4
addi a6, a6, 4
lb x30, 0(x29) // test load byte, should read out 0xDD
sb x30, 0(t1) // test store byte, should save 0xDD
addi t1, t1, 4
addi a6, a6, 4
GOTO_M_MODE // go to M mode in order to be able to toggle the UBE bit
li x28, 0x40
csrs mstatus, x28 // turn on big endianness for U mode
GOTO_U_MODE
// U mode Big endian tests
li x28, 0xAABBCCDD
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xDDCCBBAA
addi t1, t1, 4
addi a6, a6, 4
lh x30, 0(x29) // test load half, should read out 0xAABB
sh x30, 0(t1) // test store half, should save 0xBBAA
addi t1, t1, 4
addi a6, a6, 4
lb x30, 0(x29) // test load byte, should read out 0xAA
sb x30, 0(t1) // test store byte, should save 0xAA
addi t1, t1, 4
addi a6, a6, 4
END_TESTS
TEST_STACK_AND_DATA

74
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output
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@ -1,26 +1,62 @@
00000011 # Test *** NUMBER: Read of 1st byte of 0xAABBCCDDEEFF1122 in M mode little endian eeff1122 # Test 5.3.2.4: M mode little endian load/store double of 0xaabbccddeeff1122
aabbccdd # NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension
eeff1122 # M mode little endian load/store word of 0xaabbccddeeff1122
deadbeef # NOTE: the memory was already filled with deadbeef's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's
dead1122 # M mode little endian load/store halfword of 0xaabbccddeeff1122
deadbeef
deadbe22 # M mode little endian load/store byte of 0xaabbccddeeff1122
deadbeef
ddccbbaa # M mode big endian load/store double of 0x2211ffeeddccbbaa
2211ffee
ddccbbaa # M mode big endian load/store word of 0x2211ffeeddccbbaa
deadbeef
deadbbaa # M mode big endian load/store halfword of 0x2211ffeeddccbbaa
deadbeef
deadbeaa # M mode big endian load/store byte of 0x2211ffeeddccbbaa
deadbeef
0000000b # ecall after going from M mode to S mode
00000000 00000000
ffffffff # sign extended value after Read of 1st byte of 0xAABBCCDDEEFF1122 in M mode big endian eeff1122 # S mode little endian load/store double of 0xaabbccddeeff1122
bbffffff # This is 0xbb sign extended and stored in big endian mode aabbccdd
0000000b # mcause from ecall going from M mode to S mode eeff1122 # S mode little endian load/store word of 0xaabbccddeeff1122
deadbeef
dead1122 # S mode little endian load/store halfword of 0xaabbccddeeff1122
deadbeef
deadbe22 # S mode little endian load/store byte of 0xaabbccddeeff1122
deadbeef
00000009 # ecall after going from S mode to M mode
00000000 00000000
00000011 # Read of 1st byte of 0xAABBCCDDEEFF1122 in S mode little endian 0000000b # ecall after going from M mode to S mode
00000000 00000000
00000009 # mcause from ecall going from S mode to M mode (necessary to change mstatus bits) ddccbbaa # S mode big endian load/store double of 0x2211ffeeddccbbaa
2211ffee
ddccbbaa # S mode big endian load/store word of 0x2211ffeeddccbbaa
deadbeef
deadbbaa # S mode big endian load/store halfword of 0x2211ffeeddccbbaa
deadbeef
deadbeaa # S mode big endian load/store byte of 0x2211ffeeddccbbaa
deadbeef
00000009 # ecall after going from S mode to U mode
00000000 00000000
0000000b # mcause from ecall going back from M mode to S mode eeff1122 # U mode little endian load/store double of 0xaabbccddeeff1122
00000000 aabbccdd
ffffffff # sign extended value after Read of 1st byte of 0xAABBCCDDEEFF1122 in S mode big endian eeff1122 # U mode little endian load/store word of 0xaabbccddeeff1122
bbffffff # This is 0xbb sign extended and stored in big endian mode deadbeef
00000009 # mcause from ecall going from S mode to U mode dead1122 # U mode little endian load/store halfword of 0xaabbccddeeff1122
deadbeef
deadbe22 # U mode little endian load/store byte of 0xaabbccddeeff1122
deadbeef
00000008 # ecall after going from U mode to M mode
00000000 00000000
00000011 # Read of 1st byte of 0xAABBCCDDEEFF1122 in U mode little endian 0000000b # ecall after going from M mode to U mode
00000000 00000000
00000008 # mcause from ecall going from U mode to M mode (necessary to change mstatus bits) ddccbbaa # U mode big endian load/store double of 0x2211ffeeddccbbaa
2211ffee
ddccbbaa # U mode big endian load/store word of 0x2211ffeeddccbbaa
deadbeef
deadbbaa # U mode big endian load/store halfword of 0x2211ffeeddccbbaa
deadbeef
deadbeaa # U mode big endian load/store byte of 0x2211ffeeddccbbaa
deadbeef
00000008 # ecall after ending tests in U mode
00000000 00000000
0000000b # mcause from ecall going back from M mode to U mode
00000000
ffffffff # sign extended value after Read of 1st byte of 0xAABBCCDDEEFF1122 in U mode big endian
bbffffff # This is 0xbb sign extended and stored in big endian mode
00000008 # Ecall from terminating tests in U mode.
00000000

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output Normal file
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@ -0,0 +1,4 @@
00000000 # Test *** Number : Read out SXL, UXL of mstatus as 2 and 2 for 64 bit systems
0000000a
00000000 # read of read-only uxl, sxl bits after attmepted write
0000000a

160
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S
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@ -30,29 +30,66 @@ INIT_TESTS
TRAP_HANDLER m TRAP_HANDLER m
// Test ***Number: testing that accesses to sub-word memory acceses not on a word boundary go // Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go
// correctly with the relevant status bit indicating endianness for each mode. // correctly with the relevant status bit indicating endianness for each mode.
// do this by going to each mode with and testing loads with the big endian bit on and off work correctly // do this by going to each mode with and testing loads with the big endian bit on and off work correctly
// *** It appears has the MBE, SBE, and UBE bits of mstatus hardwired to zero // *** It appears Sail has the MBE, SBE, and UBE bits of mstatus hardwired to zero
// M Mode little Endianness tests:
li x28, 0xAABBCCDDEEFF1122 li x28, 0xAABBCCDDEEFF1122
li x29, 0x8000F000 li x29, 0x8000F000
sd x28, 0(x29) // Store test value into memory address in little endian mode sd x28, 0(x29) // value stored in memory as 0xAABBCCDDEEFF1122
// in little endian mode, byte at 0x1(x29) is 0x11
// in big endian mode, 0x1(x29) should be 0xBB
lb x30, 0x1(x29) // Test M Mode Little endianness, should return 0x11 ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122
sd x30, 0(t1) // store recorded M mode Little endian value to output sd x30, 0(t1) // test store double, should save 0xAABBCCDDEEFF1122
addi t1, t1, 8
addi a6, a6, 8
lw x30, 0(x29) // test load word, should read out 0xEEFF1122
sw x30, 0(t1) // test store word, should save 0xEEFF1122
addi t1, t1, 8
addi a6, a6, 8
lh x30, 0(x29) // test load half, should read out 0x1122
sh x30, 0(t1) // test store half, should save 0x1122
addi t1, t1, 8
addi a6, a6, 8
lb x30, 0(x29) // test load byte, should read out 0x22
sb x30, 0(t1) // test store byte, should save 0x22
addi t1, t1, 8 addi t1, t1, 8
addi a6, a6, 8 addi a6, a6, 8
li x28, 0x2000000000 li x28, 0x2000000000
csrs mstatus, x28 // turn on big endianness for M mode csrs mstatus, x28 // turn on big endianness for M mode
lb x30, 0x1(x29) // Test M mode big endaianness, should return 0xBB // M mode Big Endianness tests
sd x30, 0(t1) // store recorded M mode big endian value to output // In big endian modes, all values are sign extended to the right, rather than left
addi t1, t1, 8
li x28, 0xAABBCCDDEEFF1122
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0x2211FFEEDDCCBBAA
ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122
sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA
addi t1, t1, 8
addi a6, a6, 8
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xDDCCBBAA
addi t1, t1, 8
addi a6, a6, 8
lh x30, 0(x29) // test load half, should read out 0xAABB
sh x30, 0(t1) // test store half, should save 0xBBAA
addi t1, t1, 8
addi a6, a6, 8
lb x30, 0(x29) // test load byte, should read out 0xAA
sb x30, 0(t1) // test store byte, should save 0xAA
addi t1, t1, 8
addi a6, a6, 8 addi a6, a6, 8
li x28, 0x2000000000 li x28, 0x2000000000
@ -60,8 +97,29 @@ csrc mstatus, x28 // Turn off big endianness for M mode before going into the tr
GOTO_S_MODE GOTO_S_MODE
lb x30, 0x1(x29) // Test S Mode Little endianness, should return 0x11 // S mode Little endian tests
sd x30, 0(t1) // store recorded M mode Little endian value to output
li x28, 0xAABBCCDDEEFF1122
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0xAABBCCDDEEFF1122
ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122
sd x30, 0(t1) // test store double, should save 0xAABBCCDDEEFF1122
addi t1, t1, 8
addi a6, a6, 8
lw x30, 0(x29) // test load word, should read out 0xEEFF1122
sw x30, 0(t1) // test store word, should save 0xEEFF1122
addi t1, t1, 8
addi a6, a6, 8
lh x30, 0(x29) // test load half, should read out 0x1122
sh x30, 0(t1) // test store half, should save 0x1122
addi t1, t1, 8
addi a6, a6, 8
lb x30, 0(x29) // test load byte, should read out 0x22
sb x30, 0(t1) // test store byte, should save 0x22
addi t1, t1, 8 addi t1, t1, 8
addi a6, a6, 8 addi a6, a6, 8
@ -72,18 +130,57 @@ csrs mstatus, x28 // turn on big endianness for S mode
GOTO_S_MODE GOTO_S_MODE
lb x30, 0x1(x29) // Test S mode big endaianness, should return 0xBB // S mode Big endian tests
sd x30, 0(t1) // store recorded S mode big endian value to output
addi t1, t1, 8 li x28, 0xAABBCCDDEEFF1122
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0x2211FFEEDDCCBBAA
ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122
sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA
addi t1, t1, 8
addi a6, a6, 8 addi a6, a6, 8
# li x28, 0x1000000000 lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
# csrc sstatus, x28 // Turn off big endianness for S mode before going into the trap handler sw x30, 0(t1) // test store word, should save 0xDDCCBBAA
addi t1, t1, 8
addi a6, a6, 8
lh x30, 0(x29) // test load half, should read out 0xAABB
sh x30, 0(t1) // test store half, should save 0xBBAA
addi t1, t1, 8
addi a6, a6, 8
lb x30, 0(x29) // test load byte, should read out 0xAA
sb x30, 0(t1) // test store byte, should save 0xAA
addi t1, t1, 8
addi a6, a6, 8
GOTO_U_MODE GOTO_U_MODE
lb x30, 0x1(x29) // Test U Mode Little endianness, should return 0x11 // U mode Little endian tests
sd x30, 0(t1) // store recorded M mode Little endian value to output
li x28, 0xAABBCCDDEEFF1122
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0xAABBCCDDEEFF1122
ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122
sd x30, 0(t1) // test store double, should save 0xAABBCCDDEEFF1122
addi t1, t1, 8
addi a6, a6, 8
lw x30, 0(x29) // test load word, should read out 0xEEFF1122
sw x30, 0(t1) // test store word, should save 0xEEFF1122
addi t1, t1, 8
addi a6, a6, 8
lh x30, 0(x29) // test load half, should read out 0x1122
sh x30, 0(t1) // test store half, should save 0x1122
addi t1, t1, 8
addi a6, a6, 8
lb x30, 0(x29) // test load byte, should read out 0x22
sb x30, 0(t1) // test store byte, should save 0x22
addi t1, t1, 8 addi t1, t1, 8
addi a6, a6, 8 addi a6, a6, 8
@ -94,8 +191,29 @@ csrs mstatus, x28 // turn on big endianness for U mode
GOTO_U_MODE GOTO_U_MODE
lb x30, 0x1(x29) // Test U mode big endaianness, should return 0xBB // U mode Big endian tests
sd x30, 0(t1) // store recorded U mode big endian value to output
li x28, 0xAABBCCDDEEFF1122
li x29, 0x8000F000
sd x28, 0(x29) // value stored in memory as 0x2211FFEEDDCCBBAA
ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122
sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA
addi t1, t1, 8
addi a6, a6, 8
lw x30, 0(x29) // test load word, should read out 0xAABBCCDD
sw x30, 0(t1) // test store word, should save 0xDDCCBBAA
addi t1, t1, 8
addi a6, a6, 8
lh x30, 0(x29) // test load half, should read out 0xAABB
sh x30, 0(t1) // test store half, should save 0xBBAA
addi t1, t1, 8
addi a6, a6, 8
lb x30, 0(x29) // test load byte, should read out 0xAA
sb x30, 0(t1) // test store byte, should save 0xAA
addi t1, t1, 8 addi t1, t1, 8
addi a6, a6, 8 addi a6, a6, 8

51
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S Normal file
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@ -0,0 +1,51 @@
///////////////////////////////////////////
//
// WALLY-status-xlen
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-09-17
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",endianness)
INIT_TESTS
TRAP_HANDLER m
// Test ***Number: check that the UXL and SXL bits of mstatus are read only and the correct value (2 for 64 bit systems)
csrr x28, mstatus
li x29, 0xF00000000 // mask bits for uxl and sxl
and x28, x28, x29
sd x28, 0(t1) // should store 0xA00000000 to memory
addi t1, t1, 8
addi a6, a6, 8
csrs mstatus, x29 // attempt to write to uxl and sxl, should not work
csrr x28, mstatus
and x28, x28, x29
sd x28, 0(t1) // should store 0xA00000000 to memory
addi t1, t1, 8
addi a6, a6, 8
END_TESTS
TEST_STACK_AND_DATA