From 80cdb02d43f594a68fd8bdf959f64684e450a112 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 May 2023 16:51:00 -0500 Subject: [PATCH 01/28] Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. --- config/shared/parameter-defs.vh | 2 +- sim/verilate | 4 +- src/wally/wallypipelinedsoc.sv | 19 +++---- testbench/common/instrNameDecTB.sv | 3 + testbench/testbench.sv | 90 ++++++++++++++++++++++++------ 5 files changed, 87 insertions(+), 31 deletions(-) diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 271fc7fe8..78efd582d 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -76,7 +76,7 @@ parameter cvw_t P = '{ // *** definitely need to fix this. // it thinks we are casting from the enum type to BPRED_TYPE. BPRED_TYPE : BPRED_TYPE, - /* verilator lint_off ENUMVALUE */ + /* verilator lint_on ENUMVALUE */ BPRED_SIZE : BPRED_SIZE, BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, diff --git a/sim/verilate b/sim/verilate index 345e17ab9..9555322f9 100755 --- a/sim/verilate +++ b/sim/verilate @@ -7,8 +7,8 @@ verilator=`which verilator` basepath=$(dirname $0)/.. #for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do for config in rv64gc; do - echo "$config linting..." - if !($verilator --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + echo "$config simulating..." + if !($verilator --timescale "1ns/1ns" --timing --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/common/*.sv $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 03974fe51..14e085260 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -26,22 +26,19 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "config.vh" -//import cvw::*; // global CORE-V-Wally parameters - -module wallypipelinedsoc import cvw::*; ( +module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( input logic clk, input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [AHBW-1:0] HRDATAEXT, + input logic [P.AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, + output logic [P.PA_BITS-1:0] HADDR, + output logic [P.AHBW-1:0] HWDATA, + output logic [P.XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -64,14 +61,12 @@ module wallypipelinedsoc import cvw::*; ( ); // Uncore signals - logic [AHBW-1:0] HRDATA; // from AHB mux in uncore + logic [P.AHBW-1:0] HRDATA; // from AHB mux in uncore logic HRESP; // response from AHB logic MTimerInt, MSwInt;// timer and software interrupts from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs logic MExtInt,SExtInt; // from PLIC - `include "parameter-defs.vh" - // synchronize reset to SOC clock domain synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); @@ -83,7 +78,7 @@ module wallypipelinedsoc import cvw::*; ( ); // instantiate uncore if a bus interface exists - if (BUS_SUPPORTED) begin : uncore + if (P.BUS_SUPPORTED) begin : uncore uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index dd993e715..58f1ea9fc 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -250,7 +250,10 @@ module instrNameDecTB( else if (funct7[6:2] == 5'b00100) name = "FSGNJX"; else if (funct7[6:2] == 5'b10100) name = "FEQ"; else name = "ILLEGAL"; + /* verilator lint_off CASEOVERLAP */ + // *** RT: definitely take a look at this. This overlaps with 10'b1010011_000 10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD"; + /* verilator lint_on CASEOVERLAP */ else if (funct7[6:2] == 5'b00001) name = "FSUB"; else if (funct7[6:2] == 5'b00010) name = "FMUL"; else if (funct7[6:2] == 5'b00011) name = "FDIV"; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 6184cefb0..c2e2212e8 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -26,6 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" +`include "config.vh" `include "tests.vh" `define PrintHPMCounters 0 @@ -33,7 +34,12 @@ `define I_CACHE_ADDR_LOGGER 0 `define D_CACHE_ADDR_LOGGER 0 +import cvw::*; + + module testbench; + /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; parameter TEST="none"; @@ -42,7 +48,8 @@ module testbench; parameter SIGNATURESIZE = 5000000; - int test, i, errors, totalerrors; + int test, errors, totalerrors; + logic [`PA_BITS-1:0] i; logic [31:0] sig32[0:SIGNATURESIZE]; logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; logic [`XLEN-1:0] testadr, testadrNoBase; @@ -66,6 +73,8 @@ module testbench; logic HCLK, HRESETn; logic [`XLEN-1:0] PCW; + `include "parameter-defs.vh" + string ProgramAddrMapFile, ProgramLabelMapFile; integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; @@ -190,7 +199,7 @@ module testbench; assign HRDATAEXT = 0; end - if(`FPGA) begin : sdcard + if(P.FPGA) begin : sdcard sdModel sdcard (.sdClk(SDCCLK), .cmd(SDCCmd), @@ -204,7 +213,7 @@ module testbench; assign SDCDat = '0; end - wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); @@ -239,9 +248,8 @@ module testbench; // not initialized the compare results in an 'x' which propagates through // the design. if (TEST == "coremark") - for (i=MemStartAddr; i>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; if(`DCACHE_SUPPORTED) begin - localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; - localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; - localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + //localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; + localparam numlines = DCACHE_WAYSIZEINBYTES*8/DCACHE_LINELENINBITS; + //localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; + localparam numways = DCACHE_NUMWAYS; + //localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; + localparam linebytelen = DCACHE_LINELENINBITS/8; + localparam linelen = DCACHE_LINELENINBITS; + //localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; + localparam sramlen = 128; + //localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + localparam cachesramwords = DCACHE_LINELENINBITS/sramlen; localparam numwords = sramlen/`XLEN; localparam lognumlines = $clog2(numlines); localparam loglinebytelen = $clog2(linebytelen); @@ -772,6 +820,8 @@ module DCacheFlushFSM end end flop #(1) doneReg(.clk, .d(start), .q(done)); + /* verilator lint_on WIDTHTRUNC */ + /* verilator lint_on WIDTHEXPAND */ endmodule module copyShadow @@ -790,6 +840,8 @@ module copyShadow output logic CacheDirty); + /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ always_ff @(posedge clk) begin if(start) begin CacheTag = tag; @@ -800,9 +852,13 @@ module copyShadow end end + /* verilator lint_on WIDTHTRUNC */ + /* verilator lint_on WIDTHEXPAND */ endmodule task automatic updateProgramAddrLabelArray; + /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ input string ProgramAddrMapFile, ProgramLabelMapFile; inout integer ProgramAddrLabelArray [string]; // Gets the memory location of begin_signature @@ -821,5 +877,7 @@ task automatic updateProgramAddrLabelArray; end $fclose(ProgramLabelMapFP); $fclose(ProgramAddrMapFP); + /* verilator lint_on WIDTHTRUNC */ + /* verilator lint_on WIDTHEXPAND */ endtask From 987e5a5bf0d7f541e899c89adf60cfd403c7e9cf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Jun 2023 15:30:51 -0500 Subject: [PATCH 02/28] Removed comments around commented code for verilator. --- testbench/testbench.sv | 39 +++++++++++++++------------------------ 1 file changed, 15 insertions(+), 24 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1e35009f1..4fefa2cfe 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -247,9 +247,12 @@ module testbench; // strings, but uses a load double to read them in. If the last 2 bytes are // not initialized the compare results in an 'x' which propagates through // the design. +/* -----\/----- EXCLUDED -----\/----- + // **** Must fix for coremark if (TEST == "coremark") for (i=MemStartAddr; i>>>>>> verilator end for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin - /* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. + // *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; - */ end end end @@ -681,9 +673,8 @@ module testbench; logic PCSrcM; string LogFile; logic resetD, resetEdge; - /* *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. + // *** EXCLUDE for now: verilator does not like . reference when missing module even when this code not executed. flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); - */ flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin From 9a1042b0b1d934b67405e6d0b6cf16ef4e603d9d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 12 Jun 2023 11:00:30 -0500 Subject: [PATCH 03/28] This parameterizes the testbench but does not use the verilator updates or the new testbench. --- src/wally/wallypipelinedcore.sv | 2 +- src/wally/wallypipelinedsoc.sv | 17 ++- testbench/testbench.sv | 195 ++++++++++++++++---------------- 3 files changed, 109 insertions(+), 105 deletions(-) diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index a3becb9be..65460c58f 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -26,7 +26,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( +module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Privileged input logic MTimerInt, MExtInt, SExtInt, MSwInt, diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 03974fe51..d00013f05 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -26,22 +26,22 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "config.vh" +//`include "config.vh" //import cvw::*; // global CORE-V-Wally parameters -module wallypipelinedsoc import cvw::*; ( +module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( input logic clk, input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [AHBW-1:0] HRDATAEXT, + input logic [P.AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, + output logic [P.PA_BITS-1:0] HADDR, + output logic [P.AHBW-1:0] HWDATA, + output logic [P.XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -64,13 +64,12 @@ module wallypipelinedsoc import cvw::*; ( ); // Uncore signals - logic [AHBW-1:0] HRDATA; // from AHB mux in uncore + logic [P.AHBW-1:0] HRDATA; // from AHB mux in uncore logic HRESP; // response from AHB logic MTimerInt, MSwInt;// timer and software interrupts from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs logic MExtInt,SExtInt; // from PLIC - `include "parameter-defs.vh" // synchronize reset to SOC clock domain synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); @@ -83,7 +82,7 @@ module wallypipelinedsoc import cvw::*; ( ); // instantiate uncore if a bus interface exists - if (BUS_SUPPORTED) begin : uncore + if (P.BUS_SUPPORTED) begin : uncore uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9712693ec..00e4030e8 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -26,6 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" +`include "config.vh" `include "tests.vh" `define PrintHPMCounters 0 @@ -33,10 +34,14 @@ `define I_CACHE_ADDR_LOGGER 0 `define D_CACHE_ADDR_LOGGER 0 +import cvw::*; + module testbench; parameter DEBUG=0; parameter TEST="none"; +`include "parameter-defs.vh" + logic clk; logic reset_ext, reset; @@ -44,19 +49,19 @@ module testbench; int test, i, errors, totalerrors; logic [31:0] sig32[0:SIGNATURESIZE]; - logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; - logic [`XLEN-1:0] testadr, testadrNoBase; + logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; + logic [P.XLEN-1:0] testadr, testadrNoBase; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; string tests[]; logic [3:0] dummy; - logic [`AHBW-1:0] HRDATAEXT; + logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; - logic [`PA_BITS-1:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic [`XLEN/8-1:0] HWSTRB; + logic [P.PA_BITS-1:0] HADDR; + logic [P.AHBW-1:0] HWDATA; + logic [P.XLEN/8-1:0] HWSTRB; logic HWRITE; logic [2:0] HSIZE; logic [2:0] HBURST; @@ -64,7 +69,7 @@ module testbench; logic [1:0] HTRANS; logic HMASTLOCK; logic HCLK, HRESETn; - logic [`XLEN-1:0] PCW; + logic [P.XLEN-1:0] PCW; string ProgramAddrMapFile, ProgramLabelMapFile; integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; @@ -73,7 +78,7 @@ module testbench; logic riscofTest; logic StartSample, EndSample; - flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); + flopenr #(P.XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); // check assertions for a legal configuration @@ -83,25 +88,25 @@ module testbench; initial begin $display("TEST is %s", TEST); //tests = '{}; - if (`XLEN == 64) begin // RV64 + if (P.XLEN == 64) begin // RV64 case (TEST) "arch64i": tests = arch64i; "arch64priv": tests = arch64priv; - "arch64c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; + "arch64c": if (P.C_SUPPORTED) + if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; else tests = {arch64c}; - "arch64m": if (`M_SUPPORTED) tests = arch64m; - "arch64f": if (`F_SUPPORTED) tests = arch64f; - "arch64d": if (`D_SUPPORTED) tests = arch64d; - "arch64f_fma": if (`F_SUPPORTED) tests = arch64f_fma; - "arch64d_fma": if (`D_SUPPORTED) tests = arch64d_fma; - "arch64zi": if (`ZIFENCEI_SUPPORTED) tests = arch64zi; + "arch64m": if (P.M_SUPPORTED) tests = arch64m; + "arch64f": if (P.F_SUPPORTED) tests = arch64f; + "arch64d": if (P.D_SUPPORTED) tests = arch64d; + "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; + "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; + "arch64zi": if (P.ZIFENCEI_SUPPORTED) tests = arch64zi; "imperas64i": tests = imperas64i; - "imperas64f": if (`F_SUPPORTED) tests = imperas64f; - "imperas64d": if (`D_SUPPORTED) tests = imperas64d; - "imperas64m": if (`M_SUPPORTED) tests = imperas64m; - "wally64a": if (`A_SUPPORTED) tests = wally64a; - "imperas64c": if (`C_SUPPORTED) tests = imperas64c; + "imperas64f": if (P.F_SUPPORTED) tests = imperas64f; + "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; + "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; + "wally64a": if (P.A_SUPPORTED) tests = wally64a; + "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "custom": tests = custom; "wally64i": tests = wally64i; @@ -111,29 +116,29 @@ module testbench; "fpga": tests = fpga; "ahb" : tests = ahb; "coverage64gc" : tests = coverage64gc; - "arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba; - "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; - "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; - "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; + "arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba; + "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; + "arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc; + "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; endcase end else begin // RV32 case (TEST) "arch32i": tests = arch32i; "arch32priv": tests = arch32priv; - "arch32c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; + "arch32c": if (P.C_SUPPORTED) + if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; else tests = {arch32c}; - "arch32m": if (`M_SUPPORTED) tests = arch32m; - "arch32f": if (`F_SUPPORTED) tests = arch32f; - "arch32d": if (`D_SUPPORTED) tests = arch32d; - "arch32f_fma": if (`F_SUPPORTED) tests = arch32f_fma; - "arch32d_fma": if (`D_SUPPORTED) tests = arch32d_fma; - "arch32zi": if (`ZIFENCEI_SUPPORTED) tests = arch32zi; + "arch32m": if (P.M_SUPPORTED) tests = arch32m; + "arch32f": if (P.F_SUPPORTED) tests = arch32f; + "arch32d": if (P.D_SUPPORTED) tests = arch32d; + "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; + "arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma; + "arch32zi": if (P.ZIFENCEI_SUPPORTED) tests = arch32zi; "imperas32i": tests = imperas32i; - "imperas32f": if (`F_SUPPORTED) tests = imperas32f; - "imperas32m": if (`M_SUPPORTED) tests = imperas32m; - "wally32a": if (`A_SUPPORTED) tests = wally32a; - "imperas32c": if (`C_SUPPORTED) tests = imperas32c; + "imperas32f": if (P.F_SUPPORTED) tests = imperas32f; + "imperas32m": if (P.M_SUPPORTED) tests = imperas32m; + "wally32a": if (P.A_SUPPORTED) tests = wally32a; + "imperas32c": if (P.C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; "wally32i": tests = wally32i; "wally32e": tests = wally32e; @@ -141,10 +146,10 @@ module testbench; "wally32periph": tests = wally32periph; "embench": tests = embench; "coremark": tests = coremark; - "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba; - "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; - "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; - "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; + "arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba; + "arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb; + "arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc; + "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; endcase end if (tests.size() == 0) begin @@ -179,8 +184,8 @@ module testbench; assign GPIOIN = 0; assign UARTSin = 1; - if(`EXT_MEM_SUPPORTED) begin - ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) + if(P.EXT_MEM_SUPPORTED) begin + ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); @@ -190,7 +195,7 @@ module testbench; assign HRDATAEXT = 0; end - if(`FPGA) begin : sdcard + if(P.FPGA) begin : sdcard sdModel sdcard (.sdClk(SDCCLK), .cmd(SDCCmd), @@ -204,7 +209,7 @@ module testbench; assign SDCDat = '0; end - wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); @@ -218,7 +223,7 @@ module testbench; // initialize tests localparam MemStartAddr = 0; - localparam MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32); + localparam MemEndAddr = P.UNCORE_RAM_RANGE>>1+(P.XLEN/32); initial begin @@ -244,12 +249,12 @@ module testbench; // read test vectors into memory pathname = tvpaths[tests[0].atoi()]; - /* if (tests[0] == `IMPERASTEST) + /* if (tests[0] == P.IMPERASTEST) pathname = tvpaths[0]; else pathname = tvpaths[1]; */ if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"}; - if (`FPGA) begin + if (P.FPGA) begin string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; @@ -258,9 +263,9 @@ module testbench; // force sdc timers dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else begin - if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); end if (riscofTest) begin @@ -273,7 +278,7 @@ module testbench; // declare memory labels that interest us, the updateProgramAddrLabelArray task will find // the addr of each label and fill the array. To expand, add more elements to this array // and initialize them to zero (also initilaize them to zero at the start of the next test) - if(!`FPGA) begin + if(!P.FPGA) begin updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); $display("Read memfile %s", memfilename); end @@ -312,8 +317,8 @@ module testbench; begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); - testadr = ($unsigned(begin_signature_addr))/(`XLEN/8); - testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8); + testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); + testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); #600; // give time for instructions in pipeline to finish if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file @@ -342,7 +347,7 @@ module testbench; $readmemh(signame, sig32); i = 0; while (i < SIGNATURESIZE) begin - if (`XLEN == 32) begin + if (P.XLEN == 32) begin signature[i] = sig32[i]; i = i+1; end else begin @@ -362,14 +367,14 @@ module testbench; i = 0; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin - logic [`XLEN-1:0] sig; - if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + logic [P.XLEN-1:0] sig; + if (P.DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; + else if (P.UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", - tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); + tests[test], i, (testadr+i)*(P.XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); $stop; //***debug end i = i + 1; @@ -395,9 +400,9 @@ module testbench; if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"}; //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + else if (P.UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; @@ -407,7 +412,7 @@ module testbench; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; end ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 }; - if(!`FPGA) begin + if(!P.FPGA) begin updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); $display("Read memfile %s", memfilename); end @@ -417,12 +422,12 @@ module testbench; end // always @ (negedge clk) - if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample + if(`PrintHPMCounters & P.ZICOUNTERS_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; logic StartSampleDelayed, BeginDelayed; logic EndSampleFirst, EndSampleDelayed; - logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0]; + logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0]; string HPMCnames[] = '{"Mcycle", "------", @@ -503,7 +508,7 @@ module testbench; // track the current function or global label - if (DEBUG == 1 | (`PrintHPMCounters & `ZICOUNTERS_SUPPORTED)) begin : FunctionName + if (DEBUG == 1 | (`PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName FunctionName FunctionName(.reset(reset), .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), @@ -516,7 +521,7 @@ module testbench; // or sd gp, -56(t0) // or on a jump to self infinite loop (6f) for RISC-V Arch tests logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls - if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; + if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; else assign ecf = 0; assign DCacheFlushStart = ecf & (dut.core.ieu.dp.regf.rf[3] == 1 | @@ -526,21 +531,21 @@ module testbench; ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); - DCacheFlushFSM DCacheFlushFSM(.clk(clk), + DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_SUPPORTED) begin + if (P.BPRED_SUPPORTED) begin integer adrindex; // local history only - if (`BPRED_TYPE == "BP_LOCAL_AHEAD" | `BPRED_TYPE == "BP_LOCAL_REPAIR") begin + if (P.BPRED_TYPE == "BP_LOCAL_AHEAD" | P.BPRED_TYPE == "BP_LOCAL_REPAIR") begin always @(*) begin if(reset) begin - for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin + for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; end end @@ -549,10 +554,10 @@ module testbench; always @(*) begin if(reset) begin - for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin + for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) begin dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; end - for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin + for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) begin dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; end end @@ -560,7 +565,7 @@ module testbench; end - if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger + if (P.ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger int file; string LogFile; logic resetD, resetEdge; @@ -597,7 +602,7 @@ module testbench; end - if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger + if (P.DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger int file; string LogFile; logic resetD, resetEdge; @@ -636,7 +641,7 @@ module testbench; end end - if (`BPRED_SUPPORTED) begin : BranchLogger + if (P.BPRED_SUPPORTED) begin : BranchLogger if (`BPRED_LOGGER) begin string direction; int file; @@ -648,7 +653,7 @@ module testbench; assign resetEdge = ~reset & resetD; initial begin LogFile = "branch.log"; // will break some of Ross's research analysis scripts - //LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE); + //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE); file = $fopen(LogFile, "w"); end always @(posedge clk) begin @@ -664,7 +669,7 @@ module testbench; end // check for hang up. - logic [`XLEN-1:0] OldPCW; + logic [P.XLEN-1:0] OldPCW; integer WatchDogTimerCount; localparam WatchDogTimerThreshold = 1000000; logic WatchDogTimeOut; @@ -687,7 +692,7 @@ endmodule /* verilator lint_on STMTDLY */ /* verilator lint_on WIDTH */ -module DCacheFlushFSM +module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) (input logic clk, input logic reset, input logic start, @@ -695,16 +700,16 @@ module DCacheFlushFSM genvar adr; - logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; + logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; - if(`DCACHE_SUPPORTED) begin + if(P.DCACHE_SUPPORTED) begin localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; - localparam numwords = sramlen/`XLEN; + localparam numwords = sramlen/P.XLEN; localparam lognumlines = $clog2(numlines); localparam loglinebytelen = $clog2(linebytelen); localparam lognumways = $clog2(numways); @@ -715,23 +720,23 @@ module DCacheFlushFSM genvar index, way, cacheWord; logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic [sramlen-1:0] cacheline; - logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [P.XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [P.PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; for(index = 0; index < numlines; index++) begin for(way = 0; way < numways; way++) begin for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin - copyShadow #(.tagstart(tagstart), + copyShadow #(.P(P), .tagstart(tagstart), .loglinebytelen(loglinebytelen), .sramlen(sramlen)) copyShadow(.clk, .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]), + .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]), .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), // these dirty bit selections would be needed if dirty is moved inside the tag array. //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]), - //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]), + //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]), .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]), .index(index), .cacheWord(cacheWord), @@ -757,8 +762,8 @@ module DCacheFlushFSM // does not work with modelsim // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions. // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions - //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k]; - ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN]; + //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k]; + ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + k] = CacheData[j][i][l][P.XLEN*k +: P.XLEN]; end end end @@ -770,18 +775,18 @@ module DCacheFlushFSM flop #(1) doneReg(.clk, .d(start), .q(done)); endmodule -module copyShadow - #(parameter tagstart, loglinebytelen, sramlen) +module copyShadow import cvw::*; #(parameter cvw_t P, + parameter tagstart, loglinebytelen, sramlen) (input logic clk, input logic start, - input logic [`PA_BITS-1:tagstart] tag, + input logic [P.PA_BITS-1:tagstart] tag, input logic valid, dirty, input logic [sramlen-1:0] data, input logic [32-1:0] index, input logic [32-1:0] cacheWord, output logic [sramlen-1:0] CacheData, - output logic [`PA_BITS-1:0] CacheAdr, - output logic [`XLEN-1:0] CacheTag, + output logic [P.PA_BITS-1:0] CacheAdr, + output logic [P.XLEN-1:0] CacheTag, output logic CacheValid, output logic CacheDirty); From bbe3f1caf0284a692941c41a343fde4afaa79558 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 12 Jun 2023 11:49:51 -0500 Subject: [PATCH 04/28] Created temporary wrapper for lint. --- sim/lint-wally | 2 +- testbench/wallywrapper.sv | 103 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 testbench/wallywrapper.sv diff --git a/sim/lint-wally b/sim/lint-wally index acad750b6..71d6b80c4 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -8,7 +8,7 @@ basepath=$(dirname $0)/.. for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do #for config in rv64gc; do echo "$config linting..." - if !($verilator --no-timing --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv new file mode 100644 index 000000000..7a60ea185 --- /dev/null +++ b/testbench/wallywrapper.sv @@ -0,0 +1,103 @@ +/////////////////////////////////////////// +// testbench.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Wally Testbench and helper modules +// Applies test programs from the riscv-arch-test and Imperas suites +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" +`include "config.vh" +`include "tests.vh" + +`define PrintHPMCounters 0 +`define BPRED_LOGGER 0 +`define I_CACHE_ADDR_LOGGER 0 +`define D_CACHE_ADDR_LOGGER 0 + +import cvw::*; + +module wallywrapper; + parameter DEBUG=0; + parameter TEST="none"; + +`include "parameter-defs.vh" + + logic clk; + logic reset_ext, reset; + + parameter SIGNATURESIZE = 5000000; + + int test, i, errors, totalerrors; + logic [31:0] sig32[0:SIGNATURESIZE]; + logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; + logic [P.XLEN-1:0] testadr, testadrNoBase; + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [31:0] InstrW; + + string tests[]; + logic [3:0] dummy; + + logic [P.AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic [P.PA_BITS-1:0] HADDR; + logic [P.AHBW-1:0] HWDATA; + logic [P.XLEN/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; + logic UARTSin, UARTSout; + + logic SDCCLK; + logic SDCCmdIn; + logic SDCCmdOut; + logic SDCCmdOE; + logic [3:0] SDCDatIn; + tri1 [3:0] SDCDat; + tri1 SDCCmd; + + logic HREADY; + logic HSELEXT; + + // instantiate device to be tested + assign GPIOIN = 0; + assign UARTSin = 1; + + assign HREADYEXT = 1; + assign HRESPEXT = 0; + assign HRDATAEXT = 0; + + assign SDCCmd = '0; + assign SDCDat = '0; + + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, + .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); + +endmodule From 80a6170fe10074ff075a6086803ce866e3ffdaba Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 12 Jun 2023 14:06:17 -0500 Subject: [PATCH 05/28] Progress towards new testbench. --- testbench/testbench.sv | 287 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 270 insertions(+), 17 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 00e4030e8..4720803a1 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -44,6 +44,7 @@ module testbench; logic clk; logic reset_ext, reset; + logic ResetMem; parameter SIGNATURESIZE = 5000000; @@ -156,10 +157,187 @@ module testbench; $display("TEST %s not supported in this configuration", TEST); $stop; end - end + end // initial begin + + // Model the testbench as an fsm. + // Do this in parts so it easier to verify + // part 1: build a version which echos the same behavior as the below code, but does not drive anything + // part 2: drive some of the controls + // part 3: drive all logic and remove old inital and always @ negedge clk block + + typedef enum logic [3:0]{STATE_INIT_TEST, + STATE_RESET_MEMORIES, + STATE_LOAD_MEMORIES, + STATE_RESET_TEST, + STATE_RUN_TEST, + STATE_CHECK_TEST} statetype; + statetype CurrState, NextState; + logic TestBenchReset; + logic [2:0] ResetCount, ResetThreshold; + logic LoadMem; + logic ResetCntEn; + logic ResetCntRst; + string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; integer outputFilePointer; + integer begin_signature_addr; + + assign ResetThreshold = 3'd5; + + initial begin + TestBenchReset = 1; + # 100; + TestBenchReset = 0; + end + + always_ff @(negedge clk) + if (TestBenchReset) CurrState <= #1 STATE_INIT_TEST; + else CurrState <= #1 NextState; + + always_comb begin + reset_ext = 0; + ResetMem = 0; + LoadMem = 0; + ResetCntEn = 0; + ResetCntRst = 0; + case(CurrState) + STATE_INIT_TEST: begin + NextState = STATE_RESET_MEMORIES; + ResetCntRst = 1; + // 4 major steps: select test, reset wally, reset memories, and load memories + + // 1: test selection + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests + // and tests[0] == "2" refers to WallyRiscvArchTests + riscofTest = tests[0] == "1" | tests[0] == "2"; + // fill memory with defined values to reduce Xs in simulation + // Quick note the memory will need to be initialized. The C library does not + // guarantee the initialized reads. For example a strcmp can read 6 byte + // strings, but uses a load double to read them in. If the last 2 bytes are + // not initialized the compare results in an 'x' which propagates through + // the design. + + // read test vectors into memory + pathname = tvpaths[tests[0].atoi()]; + /* if (tests[0] == `IMPERASTEST) + pathname = tvpaths[0]; + else pathname = tvpaths[1]; */ + if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; + else memfilename = {pathname, tests[test], ".elf.memfile"}; + if (riscofTest) begin + ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; + end else begin + ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + end + + // declare memory labels that interest us, the updateProgramAddrLabelArray task will find + // the addr of each label and fill the array. To expand, add more elements to this array + // and initialize them to zero (also initilaize them to zero at the start of the next test) + if(!P.FPGA) begin + updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); + $display("Read memfile %s", memfilename); + end + + // 2: reset wally + reset_ext = 1; + + end + STATE_RESET_MEMORIES: begin + NextState = STATE_LOAD_MEMORIES; + reset_ext = 1; + ResetMem = 1; + end + STATE_LOAD_MEMORIES: begin + NextState = STATE_RESET_TEST; + reset_ext = 1; + LoadMem = 1; + end + STATE_RESET_TEST: begin + reset_ext = 1; + ResetCntEn = 1; + if(ResetCount < ResetThreshold) begin + NextState = STATE_RESET_TEST; + end else begin + NextState = STATE_RUN_TEST; + end + end + STATE_RUN_TEST: + if(DCacheFlushDone) begin + NextState = STATE_CHECK_TEST; + end else begin + NextState = STATE_RUN_TEST; + end + STATE_CHECK_TEST: begin + NextState = STATE_INIT_TEST; + begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; + if (!begin_signature_addr) + $display("begin_signature addr not found in %s", ProgramLabelMapFile); + else begin + CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); + if(errors > 0) totalerrors = totalerrors + 1; + end + + end + default: NextState = STATE_INIT_TEST; + endcase + end // always_comb + + counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); + + //////////////////////////////////////////////////////////////////////////////// + // Some memories are not reset, but should be zeros or set to some initial value for simulation + //////////////////////////////////////////////////////////////////////////////// + + integer adrindex; + if (P.UNCORE_RAM_SUPPORTED) + always @(posedge ResetMem) + for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + + // *** add resets for each memory + + if (P.BPRED_SUPPORTED) begin + // local history only + if (P.BPRED_TYPE == "BP_LOCAL_AHEAD" | P.BPRED_TYPE == "BP_LOCAL_REPAIR") begin + always @(posedge ResetMem) begin + for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; + end + end + end + + always @(posedge ResetMem) begin + for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) begin + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + end + for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + end + end + end + + //////////////////////////////////////////////////////////////////////////////// + // load memories with program image + //////////////////////////////////////////////////////////////////////////////// + always @(posedge LoadMem) begin + if (P.FPGA) begin + string romfilename, sdcfilename; + romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; + sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; + $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); + $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); + // shorten sdc timers for simulation + dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + end + else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + end + + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; @@ -176,7 +354,7 @@ module testbench; logic HSELEXT; logic InitializingMemories; - integer ResetCount, ResetThreshold; + integer ResetCountOld, ResetThresholdOld; logic InReset; logic BeginSample; @@ -227,31 +405,32 @@ module testbench; initial begin - ResetCount = 0; - ResetThreshold = 2; + ResetCountOld = 0; + ResetThresholdOld = 2; InReset = 1; test = 1; - totalerrors = 0; + //totalerrors = 0; testadr = 0; testadrNoBase = 0; // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests // and tests[0] == "2" refers to WallyRiscvArchTests - riscofTest = tests[0] == "1" | tests[0] == "2"; + //riscofTest = tests[0] == "1" | tests[0] == "2"; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not // guarantee the initialized reads. For example a strcmp can read 6 byte // strings, but uses a load double to read them in. If the last 2 bytes are // not initialized the compare results in an 'x' which propagates through // the design. +/* -----\/----- EXCLUDED -----\/----- if (TEST == "coremark") for (i=MemStartAddr; i Date: Mon, 12 Jun 2023 15:08:23 -0500 Subject: [PATCH 06/28] The new testbench is almost working except the shadow copy is not working. --- sim/wave.do | 433 +++++++++++++++++++++-------------------- testbench/testbench.sv | 35 +++- 2 files changed, 251 insertions(+), 217 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index 2a48308ef..70973f60a 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -61,10 +61,10 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM @@ -94,13 +94,13 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS -add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -divider {class check} -add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check} +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 @@ -177,200 +177,200 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -expand -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault +add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk +add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType +add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM +add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt @@ -599,9 +599,26 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BP add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewBPDirPredM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem +add wave -noupdate /testbench/CurrState +add wave -noupdate /testbench/reset_ext +add wave -noupdate /testbench/ResetMem +add wave -noupdate /testbench/LoadMem +add wave -noupdate /testbench/DCacheFlushFSM/start +add wave -noupdate /testbench/DCacheFlushFSM/done +add wave -noupdate /testbench/begin_signature_addr +add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/RAM +add wave -noupdate /testbench/DCacheFlushFSM/startD +add wave -noupdate {/testbench/DCacheFlushFSM/ShadowRAM[268441600]} +add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM +add wave -noupdate -expand /testbench/DCacheFlushFSM/genblk1/CacheData +add wave -noupdate -expand /testbench/DCacheFlushFSM/genblk1/CacheValid +add wave -noupdate -expand /testbench/DCacheFlushFSM/genblk1/CacheTag +add wave -noupdate /testbench/DCacheFlushFSM/genblk1/CacheDirty +add wave -noupdate /testbench/DCacheFlushFSM/genblk1/cacheline +add wave -noupdate /testbench/DCacheFlushFSM/genblk1/CacheAdr TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {12208 ns} 1} {{Cursor 4} {1472797 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 4} {144959 ns} 0} {{Cursor 4} {2536 ns} 1} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -616,4 +633,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1472724 ns} {1472832 ns} +WaveRestoreZoom {144870 ns} {145030 ns} diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4720803a1..e6731560a 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -170,7 +170,9 @@ module testbench; STATE_LOAD_MEMORIES, STATE_RESET_TEST, STATE_RUN_TEST, - STATE_CHECK_TEST} statetype; + STATE_CHECK_TEST, + STATE_CHECK_TEST_WAIT, + STATE_VALIDATE} statetype; statetype CurrState, NextState; logic TestBenchReset; logic [2:0] ResetCount, ResetThreshold; @@ -265,27 +267,40 @@ module testbench; end end STATE_RUN_TEST: - if(DCacheFlushDone) begin + if(DCacheFlushStart) begin NextState = STATE_CHECK_TEST; end else begin NextState = STATE_RUN_TEST; end STATE_CHECK_TEST: begin - NextState = STATE_INIT_TEST; - begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; + if (DCacheFlushDone) begin + NextState = STATE_VALIDATE; + end else begin + NextState = STATE_CHECK_TEST_WAIT; + end + end + STATE_CHECK_TEST_WAIT: begin + if(DCacheFlushDone) begin + NextState = STATE_VALIDATE; + end else begin + NextState = STATE_CHECK_TEST_WAIT; + end + end + STATE_VALIDATE: begin if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); else begin CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); - if(errors > 0) totalerrors = totalerrors + 1; end - + NextState = STATE_INIT_TEST; + if(errors > 0) totalerrors = totalerrors + 1; end default: NextState = STATE_INIT_TEST; endcase end // always_comb counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); + assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; //////////////////////////////////////////////////////////////////////////////// // Some memories are not reset, but should be zeros or set to some initial value for simulation @@ -899,7 +914,8 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) localparam tagstart = lognumlines + loglinebytelen; - + logic startD; + genvar index, way, cacheWord; logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; logic [sramlen-1:0] cacheline; @@ -935,7 +951,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) integer i, j, k, l; always @(posedge clk) begin - if (start) begin + if (startD) begin for(i = 0; i < numlines; i++) begin for(j = 0; j < numways; j++) begin for(l = 0; l < cachesramwords; l++) begin @@ -955,7 +971,8 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) end end end - flop #(1) doneReg(.clk, .d(start), .q(done)); + flop #(1) doneReg1(.clk, .d(start), .q(startD)); + flop #(1) doneReg2(.clk, .d(startD), .q(done)); endmodule module copyShadow import cvw::*; #(parameter cvw_t P, From 261b34af5dffed92423008c9cb0dbfd1a352f320 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jun 2023 13:18:46 -0500 Subject: [PATCH 07/28] The testbench now at least runs the arch64i in rv64gc config. Still has several issues 1. need to remove all dead code 2. seems to still be double reading memory files sometimes. 3. batch mode does not work. --- testbench/testbench.sv | 50 ++++++++++++++++++++++++++++-------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index e6731560a..1de54a670 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -165,7 +165,8 @@ module testbench; // part 2: drive some of the controls // part 3: drive all logic and remove old inital and always @ negedge clk block - typedef enum logic [3:0]{STATE_INIT_TEST, + typedef enum logic [3:0]{STATE_TESTBENCH_RESET, + STATE_INIT_TEST, STATE_RESET_MEMORIES, STATE_LOAD_MEMORIES, STATE_RESET_TEST, @@ -194,25 +195,34 @@ module testbench; end always_ff @(negedge clk) - if (TestBenchReset) CurrState <= #1 STATE_INIT_TEST; + if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET; else CurrState <= #1 NextState; + always_comb begin reset_ext = 0; ResetMem = 0; LoadMem = 0; ResetCntEn = 0; ResetCntRst = 0; - case(CurrState) + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests + // and tests[0] == "2" refers to WallyRiscvArchTests + riscofTest = tests[0] == "1" | tests[0] == "2"; + pathname = tvpaths[tests[0].atoi()]; + + case(CurrState) + STATE_TESTBENCH_RESET: begin + NextState = STATE_INIT_TEST; + test = 1; + ResetMem = 1; // only need to reset the memories once. Assumes the tests don't write xs to memory. + reset_ext = 1; + end STATE_INIT_TEST: begin NextState = STATE_RESET_MEMORIES; ResetCntRst = 1; // 4 major steps: select test, reset wally, reset memories, and load memories // 1: test selection - // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests - // and tests[0] == "2" refers to WallyRiscvArchTests - riscofTest = tests[0] == "1" | tests[0] == "2"; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not // guarantee the initialized reads. For example a strcmp can read 6 byte @@ -221,7 +231,6 @@ module testbench; // the design. // read test vectors into memory - pathname = tvpaths[tests[0].atoi()]; /* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; else pathname = tvpaths[1]; */ @@ -240,7 +249,6 @@ module testbench; // and initialize them to zero (also initilaize them to zero at the start of the next test) if(!P.FPGA) begin updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); - $display("Read memfile %s", memfilename); end // 2: reset wally @@ -250,7 +258,6 @@ module testbench; STATE_RESET_MEMORIES: begin NextState = STATE_LOAD_MEMORIES; reset_ext = 1; - ResetMem = 1; end STATE_LOAD_MEMORIES: begin NextState = STATE_RESET_TEST; @@ -287,15 +294,21 @@ module testbench; end end STATE_VALIDATE: begin + NextState = STATE_INIT_TEST; if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); else begin CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); end - NextState = STATE_INIT_TEST; if(errors > 0) totalerrors = totalerrors + 1; + test = test + 1; + if (test == tests.size()) begin + if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); + else $display("FAIL: %d test programs had errors", totalerrors); + $stop; + end end - default: NextState = STATE_INIT_TEST; + default: NextState = STATE_TESTBENCH_RESET; endcase end // always_comb @@ -316,7 +329,7 @@ module testbench; if (P.BPRED_SUPPORTED) begin // local history only - if (P.BPRED_TYPE == "BP_LOCAL_AHEAD" | P.BPRED_TYPE == "BP_LOCAL_REPAIR") begin + if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin always @(posedge ResetMem) begin for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; @@ -350,6 +363,7 @@ module testbench; else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $display("Read memfile %s", memfilename); end @@ -423,7 +437,7 @@ module testbench; ResetCountOld = 0; ResetThresholdOld = 2; InReset = 1; - test = 1; + //test = 1; //totalerrors = 0; testadr = 0; testadrNoBase = 0; @@ -582,8 +596,9 @@ module testbench; //totalerrors = totalerrors+1; end -----/\----- EXCLUDED -----/\----- */ - end +// end // move onto the next test, check to see if we're done +/* -----\/----- EXCLUDED -----\/----- test = test + 1; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); @@ -591,6 +606,7 @@ module testbench; $stop; end else begin InitializingMemories = 1; + -----/\----- EXCLUDED -----/\----- */ // If there are still additional tests to run, read in information for the next test //pathname = tvpaths[tests[0]]; /* -----\/----- EXCLUDED -----\/----- @@ -707,7 +723,7 @@ module testbench; // track the current function or global label if (DEBUG == 1 | (`PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName - FunctionName FunctionName(.reset(reset), + FunctionName FunctionName(.reset(reset_ext | TestBenchReset), .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); @@ -740,7 +756,7 @@ module testbench; integer adrindex; // local history only - if (P.BPRED_TYPE == "BP_LOCAL_AHEAD" | P.BPRED_TYPE == "BP_LOCAL_REPAIR") begin + if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin always @(*) begin if(reset) begin for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin @@ -899,6 +915,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) genvar adr; logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; + logic startD; if(P.DCACHE_SUPPORTED) begin localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; @@ -914,7 +931,6 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) localparam tagstart = lognumlines + loglinebytelen; - logic startD; genvar index, way, cacheWord; logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; From 40f7031fe7eddbf91209e69eaa53b6063d14ebd3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jun 2023 13:52:02 -0500 Subject: [PATCH 08/28] Fixed the multliple reads of the same preload memory file. --- testbench/testbench.sv | 211 ++++++----------------------------------- 1 file changed, 29 insertions(+), 182 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1de54a670..542ddc874 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -182,8 +182,7 @@ module testbench; logic ResetCntRst; - string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; - integer outputFilePointer; + string signame, memfilename, pathname; integer begin_signature_addr; assign ResetThreshold = 3'd5; @@ -214,7 +213,6 @@ module testbench; STATE_TESTBENCH_RESET: begin NextState = STATE_INIT_TEST; test = 1; - ResetMem = 1; // only need to reset the memories once. Assumes the tests don't write xs to memory. reset_ext = 1; end STATE_INIT_TEST: begin @@ -258,6 +256,8 @@ module testbench; STATE_RESET_MEMORIES: begin NextState = STATE_LOAD_MEMORIES; reset_ext = 1; + // this initialization is very expensive, only do it for coremark. + if (TEST == "coremark") ResetMem = 1; end STATE_LOAD_MEMORIES: begin NextState = STATE_RESET_TEST; @@ -295,6 +295,11 @@ module testbench; end STATE_VALIDATE: begin NextState = STATE_INIT_TEST; + if (TEST == "coremark") + if (dut.core.priv.priv.EcallFaultM) begin + $display("Benchmark: coremark is done."); + $stop; + end if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); else begin @@ -350,20 +355,22 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// // load memories with program image //////////////////////////////////////////////////////////////////////////////// - always @(posedge LoadMem) begin - if (P.FPGA) begin - string romfilename, sdcfilename; - romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; - sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; - $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); - $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); - // shorten sdc timers for simulation - dut.uncore.uncore.sdc.SDC.LimitTimers = 1; - end - else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); - $display("Read memfile %s", memfilename); + always @(posedge clk) begin + if (LoadMem) begin + if (P.FPGA) begin + string romfilename, sdcfilename; + romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; + sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; + $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); + $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); + // shorten sdc timers for simulation + dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + end + else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $display("Read memfile %s", memfilename); + end end @@ -382,8 +389,6 @@ module testbench; logic HREADY; logic HSELEXT; - logic InitializingMemories; - integer ResetCountOld, ResetThresholdOld; logic InReset; logic BeginSample; @@ -428,70 +433,6 @@ module testbench; dut.core.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - // initialize tests - localparam MemStartAddr = 0; - localparam MemEndAddr = P.UNCORE_RAM_RANGE>>1+(P.XLEN/32); - - initial - begin - ResetCountOld = 0; - ResetThresholdOld = 2; - InReset = 1; - //test = 1; - //totalerrors = 0; - testadr = 0; - testadrNoBase = 0; - // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests - // and tests[0] == "2" refers to WallyRiscvArchTests - //riscofTest = tests[0] == "1" | tests[0] == "2"; - // fill memory with defined values to reduce Xs in simulation - // Quick note the memory will need to be initialized. The C library does not - // guarantee the initialized reads. For example a strcmp can read 6 byte - // strings, but uses a load double to read them in. If the last 2 bytes are - // not initialized the compare results in an 'x' which propagates through - // the design. -/* -----\/----- EXCLUDED -----\/----- - if (TEST == "coremark") - for (i=MemStartAddr; i>1+(P.XLEN/32)); adrindex = adrindex+1) + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; // *** add resets for each memory if (P.BPRED_SUPPORTED) begin // local history only if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin - always @(posedge ResetMem) begin - for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; + always @(posedge clk) begin + if (ResetMem) begin + for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; + end end end end - always @(posedge ResetMem) begin - for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) begin - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; - end - for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + always @(posedge clk) begin + if(ResetMem) begin + for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) begin + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + end + for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + end end end end From 7d53af9206de920136d36e13995fb5110e2273b5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jun 2023 13:57:58 -0500 Subject: [PATCH 10/28] Compacted memory resets. --- testbench/testbench.sv | 32 +++++++++----------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index fad6d35f0..f59d47cc5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -325,34 +325,20 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// integer adrindex; - if (P.UNCORE_RAM_SUPPORTED) - always @(posedge clk) - if (ResetMem) + always @(posedge clk) begin + if (ResetMem) begin + if (P.UNCORE_RAM_SUPPORTED) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; - - // *** add resets for each memory - - if (P.BPRED_SUPPORTED) begin - // local history only - if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin - always @(posedge clk) begin - if (ResetMem) begin - for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin + if (P.BPRED_SUPPORTED) begin + // local history only + if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) + for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; - end - end - end - end - - always @(posedge clk) begin - if(ResetMem) begin - for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) begin + for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; - end - for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) begin + for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; - end end end end From 5b0467b287c8acb0d13e85d472d1facc3d7853ef Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jun 2023 14:05:17 -0500 Subject: [PATCH 11/28] Cleaned up testbench more. --- testbench/testbench.sv | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index f59d47cc5..4149b44b9 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -326,10 +326,11 @@ module testbench; integer adrindex; always @(posedge clk) begin - if (ResetMem) begin + if (ResetMem) // program memory is sometimes reset if (P.UNCORE_RAM_SUPPORTED) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + if(reset) begin // branch predictor must always be reset if (P.BPRED_SUPPORTED) begin // local history only if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) @@ -589,32 +590,6 @@ module testbench; .done(DCacheFlushDone)); - // initialize the branch predictor - if (P.BPRED_SUPPORTED) begin - integer adrindex; - - // local history only - if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin - always @(*) begin - if(reset) begin - for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; - end - end - end - end - - always @(*) begin - if(reset) begin - for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) begin - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; - end - for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) begin - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; - end - end - end - end if (P.ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger From ed7d785175ca5ce2e1132c5e632153224386540a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jun 2023 15:09:40 -0500 Subject: [PATCH 12/28] Now have most of the regression tests running again. --- testbench/testbench.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4149b44b9..2b3698bc5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -73,7 +73,7 @@ module testbench; logic [P.XLEN-1:0] PCW; string ProgramAddrMapFile, ProgramLabelMapFile; - integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; + integer ProgramAddrLabelArray [string]; logic DCacheFlushDone, DCacheFlushStart; logic riscofTest; @@ -558,8 +558,6 @@ module testbench; end end - - // track the current function or global label if (DEBUG == 1 | (`PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName FunctionName FunctionName(.reset(reset_ext | TestBenchReset), @@ -839,8 +837,12 @@ task automatic updateProgramAddrLabelArray; integer ProgramLabelMapFP, ProgramAddrMapFP; ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r"); ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); - + + if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files + // *** RT: I'm a bit confused by the required initialization here. + ProgramAddrLabelArray["begin_signature"] = 0; + ProgramAddrLabelArray["tohost"] = 0; while (!$feof(ProgramLabelMapFP)) begin string label, adrstr; integer returncode; From 5d0e86f65081ed23cdfb8510277917026f2d649c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 13 Jun 2023 16:24:38 -0500 Subject: [PATCH 13/28] Fixed another issue with the timing of memory resets in the new testbench. --- testbench/testbench.sv | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 2b3698bc5..9caf6417b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -29,16 +29,16 @@ `include "config.vh" `include "tests.vh" -`define PrintHPMCounters 0 -`define BPRED_LOGGER 0 -`define I_CACHE_ADDR_LOGGER 0 -`define D_CACHE_ADDR_LOGGER 0 - import cvw::*; module testbench; parameter DEBUG=0; parameter TEST="none"; + parameter PrintHPMCounters=0; + parameter BPRED_LOGGER=0; + parameter I_CACHE_ADDR_LOGGER=0; + parameter D_CACHE_ADDR_LOGGER=0; + `include "parameter-defs.vh" @@ -46,17 +46,12 @@ module testbench; logic reset_ext, reset; logic ResetMem; - parameter SIGNATURESIZE = 5000000; - int test, i, errors, totalerrors; - logic [31:0] sig32[0:SIGNATURESIZE]; - logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; - logic [P.XLEN-1:0] testadr, testadrNoBase; + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; string tests[]; - logic [3:0] dummy; logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; @@ -168,6 +163,7 @@ module testbench; typedef enum logic [3:0]{STATE_TESTBENCH_RESET, STATE_INIT_TEST, STATE_RESET_MEMORIES, + STATE_RESET_MEMORIES2, STATE_LOAD_MEMORIES, STATE_RESET_TEST, STATE_RUN_TEST, @@ -254,6 +250,12 @@ module testbench; end STATE_RESET_MEMORIES: begin + NextState = STATE_RESET_MEMORIES2; + reset_ext = 1; + // this initialization is very expensive, only do it for coremark. + if (TEST == "coremark") ResetMem = 1; + end + STATE_RESET_MEMORIES2: begin // Give the reset enough time to ensure the bus is reset before loading the memories. NextState = STATE_LOAD_MEMORIES; reset_ext = 1; // this initialization is very expensive, only do it for coremark. @@ -296,7 +298,7 @@ module testbench; STATE_VALIDATE: begin NextState = STATE_INIT_TEST; if (TEST == "coremark") - if (dut.core.priv.priv.EcallFaultM) begin + if (dut.core.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end @@ -475,7 +477,7 @@ module testbench; -----/\----- EXCLUDED -----/\----- */ - if(`PrintHPMCounters & P.ZICOUNTERS_SUPPORTED) begin : HPMCSample + if(PrintHPMCounters & P.ZICOUNTERS_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; logic StartSampleDelayed, BeginDelayed; @@ -559,7 +561,7 @@ module testbench; end // track the current function or global label - if (DEBUG == 1 | (`PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName + if (DEBUG == 1 | (PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName FunctionName FunctionName(.reset(reset_ext | TestBenchReset), .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), @@ -590,7 +592,7 @@ module testbench; - if (P.ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger + if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger int file; string LogFile; logic resetD, resetEdge; @@ -627,7 +629,7 @@ module testbench; end - if (P.DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger + if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger int file; string LogFile; logic resetD, resetEdge; @@ -667,7 +669,7 @@ module testbench; end if (P.BPRED_SUPPORTED) begin : BranchLogger - if (`BPRED_LOGGER) begin + if (BPRED_LOGGER) begin string direction; int file; logic PCSrcM; @@ -864,7 +866,7 @@ task automatic CheckSignature; input integer begin_signature_addr; output integer errors; - localparam SIGNATURESIZE = 50000; + localparam SIGNATURESIZE = 50000000; integer i; logic [31:0] sig32[0:SIGNATURESIZE]; logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; From c91530aa17e8ed65999ca346449ad484541b93f4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 10:49:09 -0500 Subject: [PATCH 14/28] Updates to wave file. --- sim/wave.do | 374 ++++++++++++++++++++++++++-------------------------- 1 file changed, 185 insertions(+), 189 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index 70973f60a..e9461d589 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -11,14 +11,14 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM @@ -170,6 +170,7 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -group AHB /testbench/dut/core/HRDATA add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE @@ -186,143 +187,143 @@ add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet +add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet +add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE @@ -389,18 +390,6 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/un add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL @@ -458,13 +447,14 @@ add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/d add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr @@ -592,32 +582,38 @@ add wave -noupdate -group {branch direction} -expand -group conditions /testbenc add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF -add wave -noupdate /testbench/dut/core/ifu/PCF -add wave -noupdate /testbench/reset -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPDirPredD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewBPDirPredM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem -add wave -noupdate /testbench/CurrState -add wave -noupdate /testbench/reset_ext -add wave -noupdate /testbench/ResetMem +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE add wave -noupdate /testbench/LoadMem -add wave -noupdate /testbench/DCacheFlushFSM/start -add wave -noupdate /testbench/DCacheFlushFSM/done -add wave -noupdate /testbench/begin_signature_addr -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/RAM -add wave -noupdate /testbench/DCacheFlushFSM/startD -add wave -noupdate {/testbench/DCacheFlushFSM/ShadowRAM[268441600]} -add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM -add wave -noupdate -expand /testbench/DCacheFlushFSM/genblk1/CacheData -add wave -noupdate -expand /testbench/DCacheFlushFSM/genblk1/CacheValid -add wave -noupdate -expand /testbench/DCacheFlushFSM/genblk1/CacheTag -add wave -noupdate /testbench/DCacheFlushFSM/genblk1/CacheDirty -add wave -noupdate /testbench/DCacheFlushFSM/genblk1/cacheline -add wave -noupdate /testbench/DCacheFlushFSM/genblk1/CacheAdr +add wave -noupdate /testbench/CurrState +add wave -noupdate /testbench/DCacheFlushStart +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/InstrMName +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/c/InstrValidM +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/a3 +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/rf +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/wd3 +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/we3 +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ifu/InstrM +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/ecf +add wave -noupdate /testbench/ecf +add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/ce +add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/we +add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/addr +add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/dout +add wave -noupdate /testbench/reset TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {144959 ns} 0} {{Cursor 4} {2536 ns} 1} +WaveRestoreCursors {{Cursor 4} {320072 ns} 0} {{Cursor 4} {19809168 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -633,4 +629,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {144870 ns} {145030 ns} +WaveRestoreZoom {319935 ns} {320329 ns} From 005307fc16e3d1e96ccdf5588a9b07c14015ec71 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 11:50:12 -0500 Subject: [PATCH 15/28] Resolved the duplicated check signature issue. --- testbench/testbench.sv | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9caf6417b..0a46dd64c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -169,7 +169,8 @@ module testbench; STATE_RUN_TEST, STATE_CHECK_TEST, STATE_CHECK_TEST_WAIT, - STATE_VALIDATE} statetype; + STATE_VALIDATE, + STATE_INCR_TEST} statetype; statetype CurrState, NextState; logic TestBenchReset; logic [2:0] ResetCount, ResetThreshold; @@ -296,7 +297,7 @@ module testbench; end end STATE_VALIDATE: begin - NextState = STATE_INIT_TEST; + NextState = STATE_INCR_TEST; if (TEST == "coremark") if (dut.core.EcallFaultM) begin $display("Benchmark: coremark is done."); @@ -308,6 +309,9 @@ module testbench; CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); end if(errors > 0) totalerrors = totalerrors + 1; + end + STATE_INCR_TEST: begin + NextState = STATE_INIT_TEST; test = test + 1; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); From 8caa4dfcfbd8ccbfb8d453e1fc4884836f8d03c7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 12:11:55 -0500 Subject: [PATCH 16/28] Continued improvements to testbench. --- testbench/testbench.sv | 90 ++++++++++++++++++++++++------------------ 1 file changed, 52 insertions(+), 38 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0a46dd64c..4652fd6ac 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -73,6 +73,8 @@ module testbench; logic DCacheFlushDone, DCacheFlushStart; logic riscofTest; logic StartSample, EndSample; + logic Validate; + logic SelectTest; flopenr #(P.XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); @@ -190,7 +192,7 @@ module testbench; TestBenchReset = 0; end - always_ff @(negedge clk) + always_ff @(posedge clk) if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET; else CurrState <= #1 NextState; @@ -201,6 +203,8 @@ module testbench; LoadMem = 0; ResetCntEn = 0; ResetCntRst = 0; + Validate = 0; + SelectTest = 0; // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests // and tests[0] == "2" refers to WallyRiscvArchTests riscofTest = tests[0] == "1" | tests[0] == "2"; @@ -209,12 +213,12 @@ module testbench; case(CurrState) STATE_TESTBENCH_RESET: begin NextState = STATE_INIT_TEST; - test = 1; reset_ext = 1; end STATE_INIT_TEST: begin NextState = STATE_RESET_MEMORIES; ResetCntRst = 1; + SelectTest = 1; // 4 major steps: select test, reset wally, reset memories, and load memories // 1: test selection @@ -229,22 +233,6 @@ module testbench; /* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; else pathname = tvpaths[1]; */ - if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; - else memfilename = {pathname, tests[test], ".elf.memfile"}; - if (riscofTest) begin - ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; - ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; - end else begin - ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; - ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; - end - - // declare memory labels that interest us, the updateProgramAddrLabelArray task will find - // the addr of each label and fill the array. To expand, add more elements to this array - // and initialize them to zero (also initilaize them to zero at the start of the next test) - if(!P.FPGA) begin - updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); - end // 2: reset wally reset_ext = 1; @@ -297,32 +285,59 @@ module testbench; end end STATE_VALIDATE: begin - NextState = STATE_INCR_TEST; - if (TEST == "coremark") - if (dut.core.EcallFaultM) begin - $display("Benchmark: coremark is done."); - $stop; - end - if (!begin_signature_addr) - $display("begin_signature addr not found in %s", ProgramLabelMapFile); - else begin - CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); - end - if(errors > 0) totalerrors = totalerrors + 1; + NextState = STATE_INIT_TEST; + Validate = '1; end STATE_INCR_TEST: begin NextState = STATE_INIT_TEST; - test = test + 1; - if (test == tests.size()) begin - if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); - else $display("FAIL: %d test programs had errors", totalerrors); - $stop; - end end default: NextState = STATE_TESTBENCH_RESET; endcase end // always_comb + always @(posedge clk) begin + + if(SelectTest) begin + if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; + else memfilename = {pathname, tests[test], ".elf.memfile"}; + if (riscofTest) begin + ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; + end else begin + ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + end + + // declare memory labels that interest us, the updateProgramAddrLabelArray task will find + // the addr of each label and fill the array. To expand, add more elements to this array + // and initialize them to zero (also initilaize them to zero at the start of the next test) + if(!P.FPGA) begin + updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); + end + end + + if(TestBenchReset) test = 1; + if(Validate) begin + if (TEST == "coremark") + if (dut.core.EcallFaultM) begin + $display("Benchmark: coremark is done."); + $stop; + end + if (!begin_signature_addr) + $display("begin_signature addr not found in %s", ProgramLabelMapFile); + else begin + CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); + end + if(errors > 0) totalerrors = totalerrors + 1; + test = test + 1; + if (test == tests.size()) begin + if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); + else $display("FAIL: %d test programs had errors", totalerrors); + $stop; + end + end + end + counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; @@ -369,8 +384,7 @@ module testbench; if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); $display("Read memfile %s", memfilename); end - end - + end logic [31:0] GPIOIN, GPIOOUT, GPIOEN; From 7fb58f5cacd9230eed15d9b4030c6a0926fb33f6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 12:23:26 -0500 Subject: [PATCH 17/28] more testbench improvements. --- testbench/testbench.sv | 87 ++++++++++++------------------------------ 1 file changed, 24 insertions(+), 63 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4652fd6ac..23dc05447 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -49,6 +49,9 @@ module testbench; int test, i, errors, totalerrors; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + string outputfile; + integer outputFilePointer; + logic [31:0] InstrW; string tests[]; @@ -219,30 +222,12 @@ module testbench; NextState = STATE_RESET_MEMORIES; ResetCntRst = 1; SelectTest = 1; - // 4 major steps: select test, reset wally, reset memories, and load memories - - // 1: test selection - // fill memory with defined values to reduce Xs in simulation - // Quick note the memory will need to be initialized. The C library does not - // guarantee the initialized reads. For example a strcmp can read 6 byte - // strings, but uses a load double to read them in. If the last 2 bytes are - // not initialized the compare results in an 'x' which propagates through - // the design. - - // read test vectors into memory - /* if (tests[0] == `IMPERASTEST) - pathname = tvpaths[0]; - else pathname = tvpaths[1]; */ - - // 2: reset wally reset_ext = 1; - end STATE_RESET_MEMORIES: begin NextState = STATE_RESET_MEMORIES2; reset_ext = 1; - // this initialization is very expensive, only do it for coremark. - if (TEST == "coremark") ResetMem = 1; + if (TEST == "coremark") ResetMem = 1; // this initialization is very expensive, only do it for coremark. end STATE_RESET_MEMORIES2: begin // Give the reset enough time to ensure the bus is reset before loading the memories. NextState = STATE_LOAD_MEMORIES; @@ -307,7 +292,6 @@ module testbench; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; end - // declare memory labels that interest us, the updateProgramAddrLabelArray task will find // the addr of each label and fill the array. To expand, add more elements to this array // and initialize them to zero (also initilaize them to zero at the start of the next test) @@ -323,6 +307,26 @@ module testbench; $display("Benchmark: coremark is done."); $stop; end + else if (TEST == "embench") begin + // Writes contents of begin_signature to .sim.output file + // this contains instret and cycles for start and end of test run, used by embench + // python speed script to calculate embench speed score. + // also, begin_signature contains the results of the self checking mechanism, + // which will be read by the python script for error checking + $display("Embench Benchmark: %s is done.", tests[test]); + if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; + else outputfile = {pathname, tests[test], ".sim.output"}; + outputFilePointer = $fopen(outputfile, "w"); + i = 0; + $fclose(outputFilePointer); + $display("Embench Benchmark: created output file: %s", outputfile); + end else if (TEST == "coverage64gc") begin + $display("Coverage tests don't get checked"); + end else begin + // for tests with no self checking mechanism, read .signature.output file and compare to check for errors + // clear signature to prevent contamination from previous tests + end + if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); else begin @@ -401,7 +405,6 @@ module testbench; logic HREADY; logic HSELEXT; - logic InReset; logic BeginSample; // instantiate device to be tested @@ -453,48 +456,6 @@ module testbench; // if ($time % 100000 == 0) $display("Time is %0t", $time); end - // check results - - // *** Probably need to take some of this code about embench and transfer to new fsm. -/* -----\/----- EXCLUDED -----\/----- - always @(negedge clk) - begin - if(InReset == 1) begin - end else begin - // Termination condition (i.e. we finished running current test) - if (DCacheFlushDone) begin - InReset = 1; - //begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; - if (!begin_signature_addr) - $display("begin_signature addr not found in %s", ProgramLabelMapFile); - testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); - testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); - #600; // give time for instructions in pipeline to finish - if (TEST == "embench") begin - // Writes contents of begin_signature to .sim.output file - // this contains instret and cycles for start and end of test run, used by embench - // python speed script to calculate embench speed score. - // also, begin_signature contains the results of the self checking mechanism, - // which will be read by the python script for error checking - $display("Embench Benchmark: %s is done.", tests[test]); - if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; - else outputfile = {pathname, tests[test], ".sim.output"}; - outputFilePointer = $fopen(outputfile, "w"); - i = 0; - $fclose(outputFilePointer); - $display("Embench Benchmark: created output file: %s", outputfile); - end else if (TEST == "coverage64gc") begin - $display("Coverage tests don't get checked"); - end else begin - // for tests with no self checking mechanism, read .signature.output file and compare to check for errors - // clear signature to prevent contamination from previous tests - end - end // if (DCacheFlushDone) - end - end // always @ (negedge clk) - -----/\----- EXCLUDED -----/\----- */ - - if(PrintHPMCounters & P.ZICOUNTERS_SUPPORTED) begin : HPMCSample integer HPMCindex; logic StartSampleFirst; From 19b7819d53daa7ddc9ee0ac9e678c5005822da65 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 14:11:25 -0500 Subject: [PATCH 18/28] Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 23dc05447..aef4e3f61 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -845,7 +845,7 @@ task automatic CheckSignature; input integer begin_signature_addr; output integer errors; - localparam SIGNATURESIZE = 50000000; + localparam SIGNATURESIZE = 5000000; integer i; logic [31:0] sig32[0:SIGNATURESIZE]; logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; From 6bb5f32eb9eaceea0678d48f9f1e2f8a7e7a66ca Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 15:28:58 -0500 Subject: [PATCH 19/28] Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s. --- src/ieu/bmu/bitmanipalu.sv | 5 ++++- src/ieu/bmu/zbc.sv | 10 ++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 228b23132..d3094377d 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -80,7 +80,10 @@ module bitmanipalu #(parameter WIDTH=32) ( // ZBC Unit if (`ZBC_SUPPORTED) begin: zbc - zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult); + logic ZBCSelect; // ZBC instruction + assign ZBCSelect = BSelect == 2'b11; + //assign ZBCSelect = 1'b0; + zbc #(WIDTH) ZBC(.A, .RevA, .B, .ZBCSelect, .Funct3, .ZBCResult); end else assign ZBCResult = 0; // ZBB Unit diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index b173a5f63..30f65258f 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -31,21 +31,23 @@ module zbc #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands + input logic ZBCSelect, // ZBC instruction input logic [2:0] Funct3, // Indicates operation to perform output logic [WIDTH-1:0] ZBCResult); // ZBC result logic [WIDTH-1:0] ClmulResult, RevClmulResult; logic [WIDTH-1:0] RevB; - logic [WIDTH-1:0] X, Y; + logic [WIDTH-1:0] X, Y, X1; bitreverse #(WIDTH) brB(B, RevB); - mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X); - mux2 #(WIDTH) ymux(RevB, B, ~Funct3[1], Y); + mux3 #(WIDTH) xmux1({RevA[WIDTH-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X1); + mux2 #(WIDTH) xmux(X1, '0, ~ZBCSelect, X); + mux3 #(WIDTH) ymux(RevB, B, '0, {~ZBCSelect, ~Funct3[1]}, Y); clmul #(WIDTH) clm(.X, .Y, .ClmulResult); bitreverse #(WIDTH) brClmulResult(ClmulResult, RevClmulResult); mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult); -endmodule \ No newline at end of file +endmodule From 7ac5239d6ab4696611675290e02c0f8393c35ece Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 16:35:55 -0500 Subject: [PATCH 20/28] Removed old configs from function name module. --- testbench/common/functionName.sv | 38 +++--- testbench/testbench.sv | 203 ++++++------------------------- 2 files changed, 53 insertions(+), 188 deletions(-) diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index c986c2e51..6f01471b3 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -21,21 +21,19 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - -module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile); +module FunctionName import cvw::*; #(parameter cvw_t P) ( + input logic reset, + input logic clk, + input string ProgramAddrMapFile, + input string ProgramLabelMapFile + ); - input logic reset; - input logic clk; - input string ProgramAddrMapFile; - input string ProgramLabelMapFile; - - logic [`XLEN-1:0] ProgramAddrMapMemory []; + logic [P.XLEN-1:0] ProgramAddrMapMemory []; string ProgramLabelMapMemory [integer]; string FunctionName; - logic [`XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld; + logic [P.XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld; logic StallD, StallE, StallM, FlushD, FlushE, FlushM; logic InstrValidM; integer ProgramAddrIndex, ProgramAddrIndexQ; @@ -53,21 +51,21 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile); // when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not // erroneously change. // also need to hold the old value not an erroneously fetched PC. - flopenr #(`XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD); - flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE); - flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp); - flopenr #(`XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld); + flopenr #(P.XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD); + flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE); + flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp); + flopenr #(P.XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld); assign PCM = InstrValidM ? PCM_temp : PCMOld; task automatic bin_search_min; - input logic [`XLEN-1:0] pc; - input logic [`XLEN-1:0] length; - ref logic [`XLEN-1:0] array []; - output logic [`XLEN-1:0] minval; - output logic [`XLEN-1:0] mid; + input logic [P.XLEN-1:0] pc; + input logic [P.XLEN-1:0] length; + ref logic [P.XLEN-1:0] array []; + output logic [P.XLEN-1:0] minval; + output logic [P.XLEN-1:0] mid; - logic [`XLEN-1:0] left, right; + logic [P.XLEN-1:0] left, right; begin if ( pc == 0 ) begin diff --git a/testbench/testbench.sv b/testbench/testbench.sv index aef4e3f61..7dd256e11 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -38,7 +38,6 @@ module testbench; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; - `include "parameter-defs.vh" @@ -46,41 +45,49 @@ module testbench; logic reset_ext, reset; logic ResetMem; - int test, i, errors, totalerrors; - - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - string outputfile; - integer outputFilePointer; - - logic [31:0] InstrW; - - string tests[]; - + // DUT signals logic [P.AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; + logic HREADYEXT, HRESPEXT; logic [P.PA_BITS-1:0] HADDR; logic [P.AHBW-1:0] HWDATA; logic [P.XLEN/8-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - logic [P.XLEN-1:0] PCW; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; + logic UARTSin, UARTSout; + + logic SDCCLK; + logic SDCCmdIn; + logic SDCCmdOut; + logic SDCCmdOE; + logic [3:0] SDCDatIn; + tri1 [3:0] SDCDat; + tri1 SDCCmd; + + logic HREADY; + logic HSELEXT; + + string ProgramAddrMapFile, ProgramLabelMapFile; integer ProgramAddrLabelArray [string]; + int test, i, errors, totalerrors; + + string outputfile; + integer outputFilePointer; + + string tests[]; logic DCacheFlushDone, DCacheFlushStart; logic riscofTest; logic StartSample, EndSample; logic Validate; logic SelectTest; - - flopenr #(P.XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); // check assertions for a legal configuration riscvassertions riscvassertions(); @@ -391,19 +398,6 @@ module testbench; end - logic [31:0] GPIOIN, GPIOOUT, GPIOEN; - logic UARTSin, UARTSout; - - logic SDCCLK; - logic SDCCmdIn; - logic SDCCmdOut; - logic SDCCmdOE; - logic [3:0] SDCDatIn; - tri1 [3:0] SDCDat; - tri1 SDCCmd; - - logic HREADY; - logic HSELEXT; logic BeginSample; @@ -442,13 +436,15 @@ module testbench; .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); // Track names of instructions + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, dut.core.ifu.InstrRawF[31:0], dut.core.ifu.InstrD, dut.core.ifu.InstrE, dut.core.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - // generate clock to sequence tests always begin @@ -541,7 +537,7 @@ module testbench; // track the current function or global label if (DEBUG == 1 | (PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName - FunctionName FunctionName(.reset(reset_ext | TestBenchReset), + FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); @@ -674,142 +670,13 @@ module testbench; end end - // check for hang up. - logic [P.XLEN-1:0] OldPCW; - integer WatchDogTimerCount; - localparam WatchDogTimerThreshold = 1000000; - logic WatchDogTimeOut; - always_ff @(posedge clk) begin - OldPCW <= PCW; - if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1; - else WatchDogTimerCount = '0; - end - - always_comb begin - WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold; - if(WatchDogTimeOut) begin - $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount); - $stop; - end - end + watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); endmodule /* verilator lint_on STMTDLY */ /* verilator lint_on WIDTH */ -module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) - (input logic clk, - input logic reset, - input logic start, - output logic done); - - genvar adr; - - logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; - logic startD; - - if(P.DCACHE_SUPPORTED) begin - localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; - localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; - localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; - localparam numwords = sramlen/P.XLEN; - localparam lognumlines = $clog2(numlines); - localparam loglinebytelen = $clog2(linebytelen); - localparam lognumways = $clog2(numways); - localparam tagstart = lognumlines + loglinebytelen; - - - - genvar index, way, cacheWord; - logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - logic [sramlen-1:0] cacheline; - logic [P.XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - logic [P.PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; - for(index = 0; index < numlines; index++) begin - for(way = 0; way < numways; way++) begin - for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin - copyShadow #(.P(P), .tagstart(tagstart), - .loglinebytelen(loglinebytelen), .sramlen(sramlen)) - copyShadow(.clk, - .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]), - .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), - .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), - // these dirty bit selections would be needed if dirty is moved inside the tag array. - //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]), - //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]), - .index(index), - .cacheWord(cacheWord), - .CacheData(CacheData[way][index][cacheWord]), - .CacheAdr(CacheAdr[way][index][cacheWord]), - .CacheTag(CacheTag[way][index][cacheWord]), - .CacheValid(CacheValid[way][index][cacheWord]), - .CacheDirty(CacheDirty[way][index][cacheWord])); - end - end - end - - integer i, j, k, l; - - always @(posedge clk) begin - if (startD) begin - for(i = 0; i < numlines; i++) begin - for(j = 0; j < numways; j++) begin - for(l = 0; l < cachesramwords; l++) begin - if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin - for(k = 0; k < numwords; k++) begin - //cacheline = CacheData[j][i][0]; - // does not work with modelsim - // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions. - // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions - //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k]; - ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + k] = CacheData[j][i][l][P.XLEN*k +: P.XLEN]; - end - end - end - end - end - end - end - end - flop #(1) doneReg1(.clk, .d(start), .q(startD)); - flop #(1) doneReg2(.clk, .d(startD), .q(done)); -endmodule - -module copyShadow import cvw::*; #(parameter cvw_t P, - parameter tagstart, loglinebytelen, sramlen) - (input logic clk, - input logic start, - input logic [P.PA_BITS-1:tagstart] tag, - input logic valid, dirty, - input logic [sramlen-1:0] data, - input logic [32-1:0] index, - input logic [32-1:0] cacheWord, - output logic [sramlen-1:0] CacheData, - output logic [P.PA_BITS-1:0] CacheAdr, - output logic [P.XLEN-1:0] CacheTag, - output logic CacheValid, - output logic CacheDirty); - - - always_ff @(posedge clk) begin - if(start) begin - CacheTag = tag; - CacheValid = valid; - CacheDirty = dirty; - CacheData = data; - CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8)); - end - end - -endmodule task automatic updateProgramAddrLabelArray; input string ProgramAddrMapFile, ProgramLabelMapFile; From d79c084a703bb9f50e5a76b0967ee7e4244d0a1b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 14 Jun 2023 17:02:49 -0500 Subject: [PATCH 21/28] Significant refactoring of testbench. --- testbench/common/checksignature.sv | 26 +++ testbench/common/functionName.sv | 4 +- testbench/common/loggers.sv | 234 ++++++++++++++++++++ testbench/common/shadowmem.sv | 139 ++++++++++++ testbench/common/watchdog.sv | 52 +++++ testbench/testbench.sv | 342 +++++++---------------------- 6 files changed, 529 insertions(+), 268 deletions(-) create mode 100644 testbench/common/checksignature.sv create mode 100644 testbench/common/loggers.sv create mode 100644 testbench/common/shadowmem.sv create mode 100644 testbench/common/watchdog.sv diff --git a/testbench/common/checksignature.sv b/testbench/common/checksignature.sv new file mode 100644 index 000000000..7fb589bb6 --- /dev/null +++ b/testbench/common/checksignature.sv @@ -0,0 +1,26 @@ +/////////////////////////////////////////// +// checksignature.sv +// +// Written: David Harris David_Harris@hmc.edu +// Modified: 14 June 2023 +// +// Purpose: Verifies the memory signature. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 6f01471b3..90157f255 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -1,6 +1,8 @@ /////////////////////////////////////////// // functionName.sv // +// Written: Ross Thompson ross1728@gmail.com +// // Purpose: decode name of function // // A component of the Wally configurable RISC-V project. @@ -56,7 +58,6 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp); flopenr #(P.XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld); assign PCM = InstrValidM ? PCM_temp : PCMOld; - task automatic bin_search_min; input logic [P.XLEN-1:0] pc; @@ -169,7 +170,6 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( initial ProgramAddrIndex = '0; assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex]; - endmodule // function_radix diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv new file mode 100644 index 000000000..0ab692385 --- /dev/null +++ b/testbench/common/loggers.sv @@ -0,0 +1,234 @@ +/////////////////////////////////////////// +// loggers.sv +// +// Written: Ross Thompson ross1728@gmail.com +// Modified: 14 June 2023 +// +// Purpose: Log branch instructions, log instruction fetches, +// log I$ misses, log data memory accesses, log D$ misses, and +// log other related operations +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module loggers import cvw::*; #(parameter cvw_t P, + parameter TEST, + parameter PrintHPMCounters, + parameter I_CACHE_ADDR_LOGGER, + parameter D_CACHE_ADDR_LOGGER, + parameter BPRED_LOGGER) ( + input logic clk, + input logic reset, + input logic DCacheFlushStart, + input logic DCacheFlushDone, +// input logic BeginSample, +// input logic StartSample, +// input logic EndSample, + input string memfilename + ); + + // performance counter logging + logic BeginSample; + logic StartSample, EndSample; + if(PrintHPMCounters & P.ZICOUNTERS_SUPPORTED) begin : HPMCSample + integer HPMCindex; + logic StartSampleFirst; + logic StartSampleDelayed, BeginDelayed; + logic EndSampleFirst, EndSampleDelayed; + logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0]; + + string HPMCnames[] = '{"Mcycle", + "------", + "InstRet", + "Br Count", + "Jump Not Return", + "Return", + "BP Wrong", + "BP Dir Wrong", + "BP Target Wrong", + "RAS Wrong", + "Instr Class Wrong", + "Load Stall", + "Store Stall", + "D Cache Access", + "D Cache Miss", + "D Cache Cycles", + "I Cache Access", + "I Cache Miss", + "I Cache Cycles", + "CSR Write", + "FenceI", + "SFenceVMA", + "Interrupt", + "Exception", + "Divide Cycles" + }; + + if(TEST == "embench") begin + // embench runs warmup then runs start_trigger + // embench end with stop_trigger. + assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; + flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + assign StartSample = StartSampleFirst & ~ StartSampleDelayed; + + assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; + flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); + assign EndSample = EndSampleFirst & ~ EndSampleDelayed; + + end else if(TEST == "coremark") begin + // embench runs warmup then runs start_trigger + // embench end with stop_trigger. + assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; + flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + assign StartSample = StartSampleFirst & ~ StartSampleDelayed; + + assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; + flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); + assign EndSample = EndSampleFirst & ~ EndSampleDelayed; + + end else begin + // default start condiction is reset + // default end condiction is end of test (DCacheFlushDone) + assign StartSampleFirst = reset; + flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + assign StartSample = StartSampleFirst & ~ StartSampleDelayed; + assign EndSample = DCacheFlushStart & ~DCacheFlushDone; + + flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); + assign BeginSample = StartSampleFirst & ~BeginDelayed; + + end + always @(negedge clk) begin + if(StartSample) begin + for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin + InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex]; + end + end + if(EndSample) begin + for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin + // unlikely to have more than 10M in any counter. + $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]); + end + end + end + end + + if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger + int file; + string LogFile; + logic resetD, resetEdge; + logic Enable; + logic InvalDelayed, InvalEdge; + + assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & + dut.core.ifu.immu.immu.pmachecker.Cacheable & + ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage & + ~reset; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + + flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed); + assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed; + + initial begin + LogFile = "ICache.log"; + file = $fopen(LogFile, "w"); + $fwrite(file, "BEGIN %s\n", memfilename); + end + string AccessTypeString, HitMissString; + assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : + dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(Enable) begin // only log i cache reads + $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString); + end + if(InvalEdge) $fwrite(file, "0 I X\n"); + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end + end + + + if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger + int file; + string LogFile; + logic resetD, resetEdge; + logic Enabled; + string AccessTypeString, HitMissString; + + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : + (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : + dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; + assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" : + dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" : + dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : + dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : + "NULL"; + + assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & + ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & + dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & + (AccessTypeString != "NULL"); + + initial begin + LogFile = "DCache.log"; + file = $fopen(LogFile, "w"); + $fwrite(file, "BEGIN %s\n", memfilename); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(Enabled) begin + $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString); + end + if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n"); + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end + end + + if (P.BPRED_SUPPORTED) begin : BranchLogger + if (BPRED_LOGGER) begin + string direction; + int file; + logic PCSrcM; + string LogFile; + logic resetD, resetEdge; + flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + initial begin + LogFile = "branch.log"; // will break some of Ross's research analysis scripts + //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE); + file = $fopen(LogFile, "w"); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + direction = PCSrcM ? "t" : "n"; + $fwrite(file, "%h %s\n", dut.core.PCM, direction); + end + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end + end + end + +endmodule diff --git a/testbench/common/shadowmem.sv b/testbench/common/shadowmem.sv new file mode 100644 index 000000000..021d4b82f --- /dev/null +++ b/testbench/common/shadowmem.sv @@ -0,0 +1,139 @@ +/////////////////////////////////////////// +// shadowmem.sv +// +// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com +// Modified: 14 June 2023 +// +// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty +// line before the end of test. Signature based regression tests need to check the L1 data cache +// in addition to the main memory. These modules create a shadow memory with a projection of the +// D$ contents. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) + (input logic clk, + input logic reset, + input logic start, + output logic done); + + genvar adr; + + logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)]; + logic startD; + + if(P.DCACHE_SUPPORTED) begin + localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; + localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; + localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; + localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; + localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; + localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + localparam numwords = sramlen/P.XLEN; + localparam lognumlines = $clog2(numlines); + localparam loglinebytelen = $clog2(linebytelen); + localparam lognumways = $clog2(numways); + localparam tagstart = lognumlines + loglinebytelen; + + genvar index, way, cacheWord; + logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [sramlen-1:0] cacheline; + logic [P.XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [P.PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + for(index = 0; index < numlines; index++) begin + for(way = 0; way < numways; way++) begin + for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin + copyShadow #(.P(P), .tagstart(tagstart), + .loglinebytelen(loglinebytelen), .sramlen(sramlen)) + copyShadow(.clk, + .start, + .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]), + .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), + .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), + // these dirty bit selections would be needed if dirty is moved inside the tag array. + //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]), + //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]), + .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]), + .index(index), + .cacheWord(cacheWord), + .CacheData(CacheData[way][index][cacheWord]), + .CacheAdr(CacheAdr[way][index][cacheWord]), + .CacheTag(CacheTag[way][index][cacheWord]), + .CacheValid(CacheValid[way][index][cacheWord]), + .CacheDirty(CacheDirty[way][index][cacheWord])); + end + end + end + + integer i, j, k, l; + + always @(posedge clk) begin + if (startD) begin + for(i = 0; i < numlines; i++) begin + for(j = 0; j < numways; j++) begin + for(l = 0; l < cachesramwords; l++) begin + if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin + for(k = 0; k < numwords; k++) begin + //cacheline = CacheData[j][i][0]; + // does not work with modelsim + // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions. + // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions + //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k]; + ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + k] = CacheData[j][i][l][P.XLEN*k +: P.XLEN]; + end + end + end + end + end + end + end + end + flop #(1) doneReg1(.clk, .d(start), .q(startD)); + flop #(1) doneReg2(.clk, .d(startD), .q(done)); +endmodule + +module copyShadow import cvw::*; #(parameter cvw_t P, + parameter tagstart, loglinebytelen, sramlen) + (input logic clk, + input logic start, + input logic [P.PA_BITS-1:tagstart] tag, + input logic valid, dirty, + input logic [sramlen-1:0] data, + input logic [32-1:0] index, + input logic [32-1:0] cacheWord, + output logic [sramlen-1:0] CacheData, + output logic [P.PA_BITS-1:0] CacheAdr, + output logic [P.XLEN-1:0] CacheTag, + output logic CacheValid, + output logic CacheDirty); + + + always_ff @(posedge clk) begin + if(start) begin + CacheTag = tag; + CacheValid = valid; + CacheDirty = dirty; + CacheData = data; + CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8)); + end + end + +endmodule diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv new file mode 100644 index 000000000..51ed8c30f --- /dev/null +++ b/testbench/common/watchdog.sv @@ -0,0 +1,52 @@ +/////////////////////////////////////////// +// watchdog.sv +// +// Written: Ross Thompson ross1728@gmail.com +// Modified: 14 June 2023 +// +// Purpose: Detects if the processor is stuck and halts the simulation +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module watchdog #(parameter XLEN, WatchDogTimerThreshold) + (input clk, + input reset + ); + + // check for hang up. + logic [XLEN-1:0] PCW; + flopenr #(XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); + logic [XLEN-1:0] OldPCW; + integer WatchDogTimerCount; + logic WatchDogTimeOut; + always_ff @(posedge clk) begin + OldPCW <= PCW; + if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1; + else WatchDogTimerCount = '0; + end + + always_comb begin + WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold; + if(WatchDogTimeOut) begin + $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount); + $stop; + end + end + +endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 7dd256e11..04e41b158 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -25,7 +25,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" `include "config.vh" `include "tests.vh" @@ -85,7 +84,6 @@ module testbench; string tests[]; logic DCacheFlushDone, DCacheFlushStart; logic riscofTest; - logic StartSample, EndSample; logic Validate; logic SelectTest; @@ -396,11 +394,8 @@ module testbench; $display("Read memfile %s", memfilename); end end - - - logic BeginSample; - + // instantiate device to be tested assign GPIOIN = 0; assign UARTSin = 1; @@ -451,89 +446,7 @@ module testbench; clk = 1; # 5; clk = 0; # 5; // if ($time % 100000 == 0) $display("Time is %0t", $time); end - - if(PrintHPMCounters & P.ZICOUNTERS_SUPPORTED) begin : HPMCSample - integer HPMCindex; - logic StartSampleFirst; - logic StartSampleDelayed, BeginDelayed; - logic EndSampleFirst, EndSampleDelayed; - logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0]; - - string HPMCnames[] = '{"Mcycle", - "------", - "InstRet", - "Br Count", - "Jump Not Return", - "Return", - "BP Wrong", - "BP Dir Wrong", - "BP Target Wrong", - "RAS Wrong", - "Instr Class Wrong", - "Load Stall", - "Store Stall", - "D Cache Access", - "D Cache Miss", - "D Cache Cycles", - "I Cache Access", - "I Cache Miss", - "I Cache Cycles", - "CSR Write", - "FenceI", - "SFenceVMA", - "Interrupt", - "Exception", - "Divide Cycles" - }; - - if(TEST == "embench") begin - // embench runs warmup then runs start_trigger - // embench end with stop_trigger. - assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); - assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - - assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; - flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); - assign EndSample = EndSampleFirst & ~ EndSampleDelayed; - - end else if(TEST == "coremark") begin - // embench runs warmup then runs start_trigger - // embench end with stop_trigger. - assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); - assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - - assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; - flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); - assign EndSample = EndSampleFirst & ~ EndSampleDelayed; - - end else begin - // default start condiction is reset - // default end condiction is end of test (DCacheFlushDone) - assign StartSampleFirst = reset; - flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); - assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - assign EndSample = DCacheFlushStart & ~DCacheFlushDone; - - flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); - assign BeginSample = StartSampleFirst & ~BeginDelayed; - - end - always @(negedge clk) begin - if(StartSample) begin - for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin - InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex]; - end - end - if(EndSample) begin - for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin - // unlikely to have more than 10M in any counter. - $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]); - end - end - end - end + // track the current function or global label if (DEBUG == 1 | (PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName @@ -564,120 +477,87 @@ module testbench; .start(DCacheFlushStart), .done(DCacheFlushDone)); - - - - if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger - int file; - string LogFile; - logic resetD, resetEdge; - logic Enable; - logic InvalDelayed, InvalEdge; - - assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & - dut.core.ifu.immu.immu.pmachecker.Cacheable & - ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage & - ~reset; - flop #(1) ResetDReg(clk, reset, resetD); - assign resetEdge = ~reset & resetD; - - flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed); - assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed; - - initial begin - LogFile = "ICache.log"; - file = $fopen(LogFile, "w"); - $fwrite(file, "BEGIN %s\n", memfilename); - end - string AccessTypeString, HitMissString; - assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : - dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; - always @(posedge clk) begin - if(resetEdge) $fwrite(file, "TRAIN\n"); - if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(Enable) begin // only log i cache reads - $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString); - end - if(InvalEdge) $fwrite(file, "0 I X\n"); - if(EndSample) $fwrite(file, "END %s\n", memfilename); - end - end - - - if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger - int file; - string LogFile; - logic resetD, resetEdge; - logic Enabled; - string AccessTypeString, HitMissString; - - flop #(1) ResetDReg(clk, reset, resetD); - assign resetEdge = ~reset & resetD; - assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : - (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : - dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; - assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" : - dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" : - dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : - dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : - "NULL"; - - assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & - ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & - dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & - (AccessTypeString != "NULL"); - - initial begin - LogFile = "DCache.log"; - file = $fopen(LogFile, "w"); - $fwrite(file, "BEGIN %s\n", memfilename); - end - always @(posedge clk) begin - if(resetEdge) $fwrite(file, "TRAIN\n"); - if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(Enabled) begin - $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString); - end - if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n"); - if(EndSample) $fwrite(file, "END %s\n", memfilename); - end - end - - if (P.BPRED_SUPPORTED) begin : BranchLogger - if (BPRED_LOGGER) begin - string direction; - int file; - logic PCSrcM; - string LogFile; - logic resetD, resetEdge; - flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); - flop #(1) ResetDReg(clk, reset, resetD); - assign resetEdge = ~reset & resetD; - initial begin - LogFile = "branch.log"; // will break some of Ross's research analysis scripts - //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE); - file = $fopen(LogFile, "w"); - end - always @(posedge clk) begin - if(resetEdge) $fwrite(file, "TRAIN\n"); - if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin - direction = PCSrcM ? "t" : "n"; - $fwrite(file, "%h %s\n", dut.core.PCM, direction); - end - if(EndSample) $fwrite(file, "END %s\n", memfilename); - end - end - end - watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); + loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) + loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename); + + task automatic CheckSignature; + // This task must be declared inside this module as it needs access to parameter P. There is + // no way to pass P to the task unless we convert it to a module. + + input string pathname; + input string TestName; + input logic riscofTest; + input integer begin_signature_addr; + output integer errors; + + localparam SIGNATURESIZE = 5000000; + integer i; + logic [31:0] sig32[0:SIGNATURESIZE]; + logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; + string signame, pathname; + logic [P.XLEN-1:0] testadr, testadrNoBase; + + // for tests with no self checking mechanism, read .signature.output file and compare to check for errors + // clear signature to prevent contamination from previous tests + for(i=0; i Date: Thu, 15 Jun 2023 13:09:07 -0500 Subject: [PATCH 22/28] Found a whole bunch of files still using the old `define configurations. --- src/cache/cache.sv | 4 +- src/cache/cacheway.sv | 6 +-- src/generic/flop/flop.sv | 2 - src/generic/flop/flopen.sv | 2 - src/generic/flop/flopenl.sv | 2 - src/generic/flop/flopenr.sv | 2 - src/generic/flop/flopenrc.sv | 2 - src/generic/flop/flopens.sv | 2 - src/generic/flop/flopr.sv | 2 - src/generic/flop/floprc.sv | 2 - src/generic/flop/synchronizer.sv | 2 - src/generic/mem/ram1p1rwbe.sv | 6 +-- src/generic/mem/ram1p1rwe.sv | 10 ++-- src/generic/mem/ram2p1r1wbe.sv | 10 ++-- src/generic/mem/rom1p1r.sv | 2 - src/ieu/alu.sv | 12 ++--- src/ieu/bmu/bitmanipalu.sv | 15 +++--- src/ieu/bmu/bitreverse.sv | 1 - src/ieu/bmu/byteop.sv | 4 +- src/ieu/bmu/clmul.sv | 2 - src/ieu/bmu/cnt.sv | 4 +- src/ieu/bmu/ext.sv | 4 +- src/ieu/bmu/zbb.sv | 4 +- src/ieu/bmu/zbc.sv | 2 - src/ieu/comparator.sv | 2 - src/ieu/datapath.sv | 2 +- src/ieu/shifter.sv | 30 ++++++------ src/ifu/bpred/btb.sv | 2 +- src/ifu/bpred/gshare.sv | 5 +- src/ifu/bpred/gsharebasic.sv | 5 +- src/ifu/bpred/localaheadbp.sv | 7 +-- src/ifu/bpred/localbpbasic.sv | 5 +- src/ifu/bpred/localrepairbp.sv | 7 +-- src/ifu/bpred/twoBitPredictor.sv | 5 +- src/ifu/decompress.sv | 13 +++-- src/ifu/ifu.sv | 2 +- src/ifu/spill.sv | 2 - src/lsu/dtim.sv | 2 +- src/lsu/lsu.sv | 2 +- src/mdu/div.sv | 2 +- src/mdu/divstep.sv | 24 +++++----- src/mmu/tlb/vm64check.sv | 2 - testbench/common/riscvassertions.sv | 74 ++++++++++++++--------------- testbench/testbench.sv | 2 +- 44 files changed, 128 insertions(+), 171 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 9dbc876fa..4ec5a1372 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -27,7 +27,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) ( +module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, USE_SRAM, READ_ONLY_CACHE) ( input logic clk, input logic reset, input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY @@ -112,7 +112,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, W AdrSelMuxSel, CacheSet); // Array of cache ways, along with victim, hit, dirty, and read merging logic - cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( + cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, USE_SRAM, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache); diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 47c3de69c..9687e478a 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26, - OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( + OFFSETLEN = 5, INDEXLEN = 9, USE_SRAM = 1, READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) @@ -109,7 +109,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), + ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN), .USE_SRAM(USE_SRAM)) CacheTagMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadTag), .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); @@ -137,7 +137,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end else begin:wordram // no byte-enable needed for i$. - ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), + ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN), .USE_SRAM(USE_SRAM)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn)); diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv index 1e906dca8..97e0ac7e4 100644 --- a/src/generic/flop/flop.sv +++ b/src/generic/flop/flop.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flop #(parameter WIDTH = 8) ( input logic clk, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv index 32e0d7dd3..2e6432519 100644 --- a/src/generic/flop/flopen.sv +++ b/src/generic/flop/flopen.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopen #(parameter WIDTH = 8) ( input logic clk, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv index 094779c74..562c4565a 100644 --- a/src/generic/flop/flopenl.sv +++ b/src/generic/flop/flopenl.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( input logic clk, load, en, input TYPE d, diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv index 3b8129e40..2c2144ab8 100644 --- a/src/generic/flop/flopenr.sv +++ b/src/generic/flop/flopenr.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopenr #(parameter WIDTH = 8) ( input logic clk, reset, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv index b3d5a1e8e..94b2b3cb0 100644 --- a/src/generic/flop/flopenrc.sv +++ b/src/generic/flop/flopenrc.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopenrc #(parameter WIDTH = 8) ( input logic clk, reset, clear, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv index 1f4c18051..c4fc5d01b 100644 --- a/src/generic/flop/flopens.sv +++ b/src/generic/flop/flopens.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopens #(parameter WIDTH = 8) ( input logic clk, set, en, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv index b2f99b3cd..2e39ee8d6 100644 --- a/src/generic/flop/flopr.sv +++ b/src/generic/flop/flopr.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module flopr #(parameter WIDTH = 8) ( input logic clk, reset, input logic [WIDTH-1:0] d, diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv index 8275a8f96..b35e9ccce 100644 --- a/src/generic/flop/floprc.sv +++ b/src/generic/flop/floprc.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module floprc #(parameter WIDTH = 8) ( input logic clk, input logic reset, diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv index f10efaeaf..f99088af4 100644 --- a/src/generic/flop/synchronizer.sv +++ b/src/generic/flop/synchronizer.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module synchronizer ( input logic clk, input logic d, diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 8905cc551..6cd9dae05 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -30,11 +30,11 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words - `include "wally-config.vh" -module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( +// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words + +module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index f3a8a2248..f819ac0ce 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -30,9 +30,7 @@ // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words -`include "wally-config.vh" - -module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) ( +module ram1p1rwe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, @@ -46,19 +44,19 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray + if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray // 64 x 128-bit SRAM ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB('0), .Q(dout)); - end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag + end else if ((USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag // 64 x 44-bit SRAM ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB('0), .Q(dout)); - end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag + end else if ((USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag // 64 x 22-bit SRAM ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 51e2871b4..18ed9d5ea 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -29,11 +29,11 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words - `include "wally-config.vh" -module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( +// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words + +module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( input logic clk, input logic ce1, ce2, input logic [$clog2(DEPTH)-1:0] ra1, @@ -52,7 +52,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( // TRUE Smem macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin + if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( .QA(rd1), .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin + end else if ((USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index ef9c6da37..497356788 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -25,8 +25,6 @@ // This model actually works correctly with vivado. -`include "wally-config.vh" - module rom1p1r #(parameter ADDR_WIDTH = 8, parameter DATA_WIDTH = 32, parameter PRELOAD_ENABLED = 0) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 43df83b60..c3ad75551 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" -module alu #(parameter WIDTH=32) ( +module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) ( input logic [WIDTH-1:0] A, B, // Operands input logic W64, // W64-type instruction input logic SubArith, // Subtraction or arithmetic shift @@ -56,7 +56,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); + shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -76,7 +76,7 @@ module alu #(parameter WIDTH=32) ( 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv - 3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) + 3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & CondMaskInvB; // and, bclr endcase @@ -87,8 +87,8 @@ module alu #(parameter WIDTH=32) ( else assign PreALUResult = FullResult; // Final Result B instruction select mux - if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, + if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu + bitmanipalu #(P, WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, .Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, .CondMaskB, .CondShiftA, .ALUResult); end else begin @@ -96,4 +96,4 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = B; assign CondShiftA = A; end -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index d3094377d..75b8bed02 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -27,9 +27,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - -module bitmanipalu #(parameter WIDTH=32) ( +module bitmanipalu import cvw::*; #(parameter cvw_t P, + parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic W64, // W64-type instruction input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction @@ -56,13 +55,13 @@ module bitmanipalu #(parameter WIDTH=32) ( assign {Mask, PreShift} = BALUControl[1:0]; // Mask Generation Mux - if (`ZBS_SUPPORTED) begin: zbsdec + if (P.ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen(B[$clog2(WIDTH)-1:0], MaskB); mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; // 0-3 bit Pre-Shift Mux - if (`ZBA_SUPPORTED) begin: zbapreshift + if (P.ZBA_SUPPORTED) begin: zbapreshift if (WIDTH == 64) begin mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA); end else assign CondZextA = A; @@ -74,12 +73,12 @@ module bitmanipalu #(parameter WIDTH=32) ( end // Bit reverse needed for some ZBB, ZBC instructions - if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse + if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse bitreverse #(WIDTH) brA(.A, .RevA); end // ZBC Unit - if (`ZBC_SUPPORTED) begin: zbc + if (P.ZBC_SUPPORTED) begin: zbc logic ZBCSelect; // ZBC instruction assign ZBCSelect = BSelect == 2'b11; //assign ZBCSelect = 1'b0; @@ -87,7 +86,7 @@ module bitmanipalu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; // ZBB Unit - if (`ZBB_SUPPORTED) begin: zbb + if (P.ZBB_SUPPORTED) begin: zbb zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index e2afb0c95..fc2530aab 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -27,7 +27,6 @@ // either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" module bitreverse #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index e6099533b..2879ba042 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module byteop #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands input logic ByteSelect, // LSB of Immediate @@ -43,4 +41,4 @@ module byteop #(parameter WIDTH=32) ( end mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index cf3e1c6b1..675387577 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] X, Y, // Operands output logic [WIDTH-1:0] ClmulResult); // ZBS result diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index a1f82eb7e..d015c1195 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -28,8 +28,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module cnt #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, RevA, // Operands input logic [1:0] B, // Last 2 bits of immediate @@ -62,4 +60,4 @@ module cnt #(parameter WIDTH = 32) ( assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0; mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 438addaa8..1feca6e1e 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -28,8 +28,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module ext #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, // Operands input logic [1:0] ExtSelect, // B[2], B[0] of immediate @@ -42,4 +40,4 @@ module ext #(parameter WIDTH = 32) ( assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 3d7bcedd9..9ae3df42d 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -28,8 +28,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands input logic W64, // Indicates word operation @@ -55,4 +53,4 @@ module zbb #(parameter WIDTH=32) ( // ZBB Result select mux mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 30f65258f..9ecbde3ca 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module zbc #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, RevA, B, // Operands input logic ZBCSelect, // ZBC instruction diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 5f504dced..0803d8b2f 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // This comparator is best module comparator #(parameter WIDTH=64) ( input logic [WIDTH-1:0] a, b, // Operands diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index cb013ee9d..0c315dbdb 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -112,7 +112,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE); + alu #(P, P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, ALUResultE, IEUAdrE); mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 11ae1cf0a..40dd7d788 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -27,21 +27,19 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - -module shifter ( - input logic [`XLEN-1:0] A, // shift Source - input logic [`LOG_XLEN-1:0] Amt, // Shift amount +module shifter import cvw::*; #(parameter cvw_t P) ( + input logic [P.XLEN-1:0] A, // shift Source + input logic [P.LOG_XLEN-1:0] Amt, // Shift amount input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift - output logic [`XLEN-1:0] Y); // Shifted result + output logic [P.XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount + logic [2*P.XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [P.LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount logic Sign; // Sign bit for sign extension - assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension - if (`XLEN==32) begin // rv32 - if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates + assign Sign = A[P.XLEN-1] & SubArith; // sign bit for sign extension + if (P.XLEN==32) begin // rv32 + if (P.ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates always_comb // funnel mux case({Right, Rotate}) 2'b00: Z = {A[31:0], 31'b0}; @@ -56,12 +54,12 @@ module shifter ( end assign TruncAmt = Amt; // shift amount end else begin // rv64 - logic [`XLEN-1:0] A64; + logic [P.XLEN-1:0] A64; mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux - if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates + if (P.ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates // shifter rotate source select mux - logic [`XLEN-1:0] RotA; // rotate source - mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons + logic [P.XLEN-1:0] RotA; // rotate source + mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons always_comb // funnel mux case ({Right, Rotate}) 2'b00: Z = {A64[63:0],{63'b0}}; @@ -82,7 +80,7 @@ module shifter ( // Funnel operation assign ZShift = Z >> Offset; - assign Y = ZShift[`XLEN-1:0]; + assign Y = ZShift[P.XLEN-1:0]; endmodule diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 5279f867a..d0e4db45e 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -92,7 +92,7 @@ module btb import cvw::*; #(parameter cvw_t P, // An optimization may be using a PC relative address. - ram2p1r1wbe #(2**Depth, P.XLEN+4) memory( + ram2p1r1wbe #(2**Depth, P.XLEN+4, P.USE_SRAM) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF), .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1)); diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index dcd94e2a2..640ddb273 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -30,7 +30,8 @@ module gshare #(parameter XLEN, parameter k = 10, - parameter integer TYPE = 1) ( + parameter integer TYPE = 1, + parameter USE_SRAM = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -83,7 +84,7 @@ module gshare #(parameter XLEN, assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableBPDirPredF), diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 165915ce2..636e5408c 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -29,7 +29,8 @@ module gsharebasic #(parameter XLEN, parameter k = 10, - parameter TYPE = 1) ( + parameter TYPE = 1, + parameter USE_SRAM = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -57,7 +58,7 @@ module gsharebasic #(parameter XLEN, assign IndexM = GHRM; end - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 6fdf7c3f5..2ba9ef960 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -27,7 +27,8 @@ module localaheadbp #(parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10) ( // number of past branches stored + parameter k = 10, + parameter USE_SRAM = 1) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -58,7 +59,7 @@ module localaheadbp #(parameter XLEN, //assign IndexNextF = LHR; assign IndexM = LHRW; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -91,7 +92,7 @@ module localaheadbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k) BHT(.clk(clk), + ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRF), diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index 827b756e6..1fc302d1c 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -28,7 +28,8 @@ module localbpbasic #(parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10) ( // number of past branches stored + parameter k = 10, + parameter USE_SRAM = 1) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -55,7 +56,7 @@ module localbpbasic #(parameter XLEN, assign IndexNextF = LHR; assign IndexM = LHRM; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index f7be7e71e..835096452 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -27,7 +27,8 @@ module localrepairbp #(parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10) ( // number of past branches stored + parameter k = 10, + parameter USE_SRAM = 1) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -57,7 +58,7 @@ module localrepairbp #(parameter XLEN, logic SpeculativeFlushedF; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -88,7 +89,7 @@ module localrepairbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k) BHT(.clk(clk), + ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRCommittedF), diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 7cb3f4173..aeae77f14 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -27,7 +27,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module twoBitPredictor #(parameter XLEN, - parameter k = 10) ( + parameter k = 10, + parameter USE_SRAM = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -53,7 +54,7 @@ module twoBitPredictor #(parameter XLEN, assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 582dbecbe..c2088ae67 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -29,7 +29,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" module decompress #(parameter XLEN)( input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half @@ -91,18 +90,18 @@ module decompress #(parameter XLEN)( end 5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld 5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw - 5'b00011: if (`XLEN==32) + 5'b00011: if (XLEN==32) InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw else InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld; 5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd 5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw - 5'b00111: if (`XLEN==32) + 5'b00111: if (XLEN==32) InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw else InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd 5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi - 5'b01001: if (`XLEN==32) + 5'b01001: if (XLEN==32) InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal else InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw @@ -126,7 +125,7 @@ module decompress #(parameter XLEN)( InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or else // if (instr16[6:5] == 2'b11) InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and - else if (`XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] + else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] if (instr16[6:5] == 2'b00) InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw else if (instr16[6:5] == 2'b01) @@ -151,7 +150,7 @@ module decompress #(parameter XLEN)( 5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli 5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp 5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp - 5'b10011: if (`XLEN == 32) + 5'b10011: if (XLEN == 32) InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp else InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp @@ -170,7 +169,7 @@ module decompress #(parameter XLEN)( InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add 5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp 5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp - 5'b10111: if (`XLEN==32) + 5'b10111: if (XLEN==32) InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp else InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index f33c150d0..571b2121d 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -234,7 +234,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), - .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) + .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(1)) icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 27eaa4107..4a04d51e1 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -29,8 +29,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module spill import cvw::*; #(parameter cvw_t P) ( input logic clk, input logic reset, diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 36b3af1a3..8ee5d3174 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -49,7 +49,7 @@ module dtim import cvw::*; #(parameter cvw_t P) ( assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. - ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN)) + ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN), .USE_SRAM(P.USE_SRAM)) ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); endmodule diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 595f1eec4..02a88beb4 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -262,7 +262,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW); cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( + .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), diff --git a/src/mdu/div.sv b/src/mdu/div.sv index a05e88f6d..a2d7f893d 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -105,7 +105,7 @@ module div import cvw::*; #(parameter cvw_t P) ( // one copy of divstep for each bit produced per cycle genvar i; for (i=0; i XLEN because AHB bus width is XLEN"); - assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN || `DCACHE_SUPPORTED || `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 || (!`DCACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 || (!`ICACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 || (`S_SUPPORTED == 0 && `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); - assert (`U_SUPPORTED || (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - assert (`VIRTMEM_SUPPORTED == 0 || (`DTIM_SUPPORTED == 0 && `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); - assert (`DCACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`ICACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert ((`DCACHE_SUPPORTED == 0 && `ICACHE_SUPPORTED == 0) || `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); - assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (`DCACHE_SUPPORTED || (`A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); - assert (`IDIV_ON_FPU == 0 || `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); - assert (`SSTC_SUPPORTED == 0 || (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); - assert ((`ZMMUL_SUPPORTED == 0) || (`M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); + assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); + assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); + assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); + assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); + assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); + assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); + assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported"); + assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); + assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); + assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); + assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); + assert (P.UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); + assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); + assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); + assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); + assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); + assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED."); + assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); + assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally."); + assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); + assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); + assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); end endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 04e41b158..1b95b5cc4 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -88,7 +88,7 @@ module testbench; logic SelectTest; // check assertions for a legal configuration - riscvassertions riscvassertions(); + riscvassertions #(P) riscvassertions(); // pick tests based on modes supported initial begin From 2fc80801020915ca13f695e70f348ccdf8c3713d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jun 2023 13:42:24 -0500 Subject: [PATCH 23/28] Got the srams parameterized correctly now. --- src/cache/cache.sv | 5 +++-- src/cache/cacheway.sv | 11 ++++++----- src/generic/mem/ram1p1rwbe.sv | 8 ++++---- src/generic/mem/ram1p1rwe.sv | 11 ++++++----- src/ifu/ifu.sv | 4 ++-- src/lsu/dtim.sv | 2 +- src/lsu/lsu.sv | 4 ++-- src/uncore/ram_ahb.sv | 2 +- 8 files changed, 25 insertions(+), 22 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 4ec5a1372..941da58ab 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -27,7 +27,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, USE_SRAM, READ_ONLY_CACHE) ( +module cache import cvw::*; #(parameter cvw_t P, + parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) ( input logic clk, input logic reset, input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY @@ -112,7 +113,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN, NUMLINES, NUMWAYS, LOGBWPL, W AdrSelMuxSel, CacheSet); // Array of cache ways, along with victim, hit, dirty, and read merging logic - cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, USE_SRAM, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( + cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache); diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 9687e478a..c697ccd30 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -27,8 +27,9 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26, - OFFSETLEN = 5, INDEXLEN = 9, USE_SRAM = 1, READ_ONLY_CACHE = 0) ( +module cacheway import cvw::*; #(parameter cvw_t P, + parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26, + OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) @@ -109,7 +110,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN), .USE_SRAM(USE_SRAM)) CacheTagMem(.clk, .ce(CacheEn), + ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadTag), .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); @@ -131,13 +132,13 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = for(words = 0; words < NUMSRAM; words++) begin: word if (!READ_ONLY_CACHE) begin:wordram - ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), + ram1p1rwbe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end else begin:wordram // no byte-enable needed for i$. - ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN), .USE_SRAM(USE_SRAM)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), + ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn)); diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 6cd9dae05..95ba152f7 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -34,7 +34,7 @@ // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words -module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( +module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=44) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, @@ -49,7 +49,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray + if ((P.USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -59,7 +59,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag + end else if ((P.USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag genvar index; // 64 x 44-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -69,7 +69,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag + end else if ((P.USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag genvar index; // 64 x 22-bit SRAM logic [WIDTH-1:0] BitWriteMask; diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index f819ac0ce..24d92ff7f 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -30,7 +30,8 @@ // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words -module ram1p1rwe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( +module ram1p1rwe import cvw::* ; #(parameter cvw_t P, + parameter DEPTH=64, WIDTH=44) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, @@ -44,21 +45,21 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44, USE_SRAM=1) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray + if ((P.USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray // 64 x 128-bit SRAM ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB('0), .Q(dout)); - end else if ((USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag + end else if ((P.USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag // 64 x 44-bit SRAM ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB('0), .Q(dout)); - end else if ((USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag + end else if ((P.USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag // 64 x 22-bit SRAM - ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB('0), .Q(dout)); diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 571b2121d..f47587ed0 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -232,9 +232,9 @@ module ifu import cvw::*; #(parameter cvw_t P) ( assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; - cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), + cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS), .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS), - .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(1)) + .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1)) icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 8ee5d3174..ec5a1f95a 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -49,7 +49,7 @@ module dtim import cvw::*; #(parameter cvw_t P) ( assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. - ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN), .USE_SRAM(P.USE_SRAM)) + ram1p1rwbe #(.P(P), .DEPTH(DEPTH), .WIDTH(P.LLEN)) ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); endmodule diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 02a88beb4..3a6d24621 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -261,8 +261,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0; assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW); - cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .USE_SRAM(P.USE_SRAM), .READ_ONLY_CACHE(0)) dcache( + cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), + .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index b7ec13457..047cdf979 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -71,7 +71,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); // single-ported RAM - ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1), + ram1p1rwbe #(.P(P), .DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); From 44c72c20e27300a2613098896ecee36e1be8aced Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jun 2023 14:05:44 -0500 Subject: [PATCH 24/28] Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. --- config/rv64gc/wally-config.vh | 159 ----------------------------- src/cache/cacheLRU.sv | 2 - src/cache/cachefsm.sv | 2 - src/cache/subcachelineread.sv | 2 - src/generic/adder.sv | 2 - src/generic/aplusbeq0.sv | 4 +- src/generic/arrs.sv | 2 - src/generic/clockgater.sv | 6 +- src/generic/counter.sv | 2 - src/generic/decoder.sv | 2 - src/generic/mem/ram1p1rwbe.sv | 2 - src/generic/mem/ram2p1r1wbe.sv | 11 +- src/generic/mux.sv | 1 - src/generic/neg.sv | 2 - src/generic/onehotdecoder.sv | 2 - src/generic/or_rows.sv | 2 - src/generic/priorityonehot.sv | 2 - src/generic/prioritythermometer.sv | 2 - src/ieu/alu.sv | 2 - src/ifu/bpred/bpred.sv | 16 +-- src/ifu/bpred/btb.sv | 2 +- src/ifu/bpred/gshare.sv | 8 +- src/ifu/bpred/gsharebasic.sv | 8 +- src/ifu/bpred/localaheadbp.sv | 10 +- src/ifu/bpred/localbpbasic.sv | 8 +- src/ifu/bpred/localrepairbp.sv | 12 +-- src/ifu/bpred/twoBitPredictor.sv | 7 +- testbench/common/wallyTracer.sv | 34 +++--- testbench/wallywrapper.sv | 1 - 29 files changed, 60 insertions(+), 255 deletions(-) delete mode 100644 config/rv64gc/wally-config.vh diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh deleted file mode 100644 index 1dd3d7f4f..000000000 --- a/config/rv64gc/wally-config.vh +++ /dev/null @@ -1,159 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -// IEEE 754 compliance -`define IEEE754 0 - -// MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 1 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 1 -`define ICACHE_SUPPORTED 1 -`define VIRTMEM_SUPPORTED 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 64'h0000000080000000 - -// Bus Interface width -`define AHBW 64 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Physical Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h007FFFFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h007FFFFF -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 -`define UNCORE_RAM_BASE 56'h80000000 -`define UNCORE_RAM_RANGE 56'h7FFFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 1 -//`define BPRED_TYPE "BP_GLOBAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_TYPE "BP_GSHARE" // "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 4 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 1 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 1 -`define ZBB_SUPPORTED 1 -`define ZBC_SUPPORTED 1 -`define ZBS_SUPPORTED 1 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index e84c34dee..146a67cd1 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module cacheLRU #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) ( input logic clk, diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 544e3454e..0909ae82d 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index ea305fb6c..0c0e11c29 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module subcachelineread #(parameter LINELEN, WORDLEN, parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address diff --git a/src/generic/adder.sv b/src/generic/adder.sv index 7acd20df0..13b649a48 100644 --- a/src/generic/adder.sv +++ b/src/generic/adder.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module adder #(parameter WIDTH=8) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index d322216b3..f8d675b33 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module aplusbeq0 #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] a, b, output logic zero @@ -40,4 +38,4 @@ module aplusbeq0 #(parameter WIDTH = 8) ( assign x = a ^ b; assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0}; assign zero = (x == orshift); -endmodule \ No newline at end of file +endmodule diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index 5a9cf21f0..dd473b307 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module arrs( input logic clk, input logic areset, diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index c09f98f2c..c0150133c 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -24,16 +24,14 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - -module clockgater ( +module clockgater #(parameter FPGA) ( input logic E, input logic SE, input logic CLK, output logic ECLK ); - if (`FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK)); + if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK)); else begin // *** BUG // VERY IMPORTANT. diff --git a/src/generic/counter.sv b/src/generic/counter.sv index 1480dc929..7957976ee 100644 --- a/src/generic/counter.sv +++ b/src/generic/counter.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module counter #(parameter WIDTH=8) ( input logic clk, reset, en, output logic [WIDTH-1:0] q diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 807a6d6ca..6284a454c 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -23,8 +23,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" - module decoder #(parameter BINARY_BITS = 3) ( input logic [BINARY_BITS-1:0] binary, output logic [(2**BINARY_BITS)-1:0] onehot diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 95ba152f7..56637c0ce 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -30,8 +30,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=44) ( diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 18ed9d5ea..202d0432b 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -29,11 +29,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words -module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( +module ram2p1r1wbe import cvw::*; #(parameter cvw_t P, + parameter DEPTH=1024, WIDTH=68) ( input logic clk, input logic ce1, ce2, input logic [$clog2(DEPTH)-1:0] ra1, @@ -52,7 +51,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( // TRUE Smem macro // *************************************************************************** - if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin + if ((P.USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -64,7 +63,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( .QA(rd1), .QB()); - end else if ((USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin + end else if ((P.USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -76,7 +75,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( .QA(rd1), .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin + end else if ((P.USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMWriteData; diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 223d41afc..9c1dfe335 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -24,7 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" /* verilator lint_off DECLFILENAME */ module mux2 #(parameter WIDTH = 8) ( diff --git a/src/generic/neg.sv b/src/generic/neg.sv index 66be9e073..df2a9b9c7 100644 --- a/src/generic/neg.sv +++ b/src/generic/neg.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module neg #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] a, output logic [WIDTH-1:0] y); diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 5e8f01c26..b672a08e5 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module onehotdecoder #(parameter WIDTH = 2) ( input logic [WIDTH-1:0] bin, output logic [2**WIDTH-1:0] decoded diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv index 160bc7447..9a8aeb8cc 100644 --- a/src/generic/or_rows.sv +++ b/src/generic/or_rows.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // perform an OR of all the rows in an array, producing one output for each column // equivalent to assign y = a.or module or_rows #(parameter ROWS = 8, COLS=2) ( diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv index ba5ebb90f..1cddb2bfc 100644 --- a/src/generic/priorityonehot.sv +++ b/src/generic/priorityonehot.sv @@ -33,8 +33,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" - module priorityonehot #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index d1970a805..6fe261265 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -29,8 +29,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" - module prioritythermometer #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index c3ad75551..4269a9af6 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) ( input logic [WIDTH-1:0] A, B, // Operands input logic W64, // W64-type instruction diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 2bc65caa6..2477f0cae 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -97,45 +97,45 @@ module bpred import cvw::*; #(parameter cvw_t P) ( // Part 1 branch direction prediction if (P.BPRED_TYPE == BP_TWOBIT) begin:Predictor - twoBitPredictor #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, + twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_GSHARE) begin:Predictor - gshare #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == BP_GLOBAL) begin:Predictor - gshare #(P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == BP_GSHARE_BASIC) begin:Predictor - gsharebasic #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_GLOBAL_BASIC) begin:Predictor - gsharebasic #(P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_LOCAL_BASIC) begin:Predictor - localbpbasic #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, + localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_LOCAL_AHEAD) begin:Predictor - localaheadbp #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, + localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_LOCAL_REPAIR) begin:Predictor - localrepairbp #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, + localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, .BranchD, .BranchE, .BranchM, .PCSrcE); diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index d0e4db45e..e93c1decb 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -92,7 +92,7 @@ module btb import cvw::*; #(parameter cvw_t P, // An optimization may be using a PC relative address. - ram2p1r1wbe #(2**Depth, P.XLEN+4, P.USE_SRAM) memory( + ram2p1r1wbe #(P, 2**Depth, P.XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF), .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1)); diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 640ddb273..460acbcbf 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -28,10 +28,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module gshare #(parameter XLEN, +module gshare import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter k = 10, - parameter integer TYPE = 1, - parameter USE_SRAM = 1) ( + parameter integer TYPE = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -84,7 +84,7 @@ module gshare #(parameter XLEN, assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableBPDirPredF), diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 636e5408c..2914c3e3f 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -27,10 +27,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gsharebasic #(parameter XLEN, +module gsharebasic import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter k = 10, - parameter TYPE = 1, - parameter USE_SRAM = 1) ( + parameter TYPE = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -58,7 +58,7 @@ module gsharebasic #(parameter XLEN, assign IndexM = GHRM; end - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 2ba9ef960..266219416 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -25,10 +25,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module localaheadbp #(parameter XLEN, +module localaheadbp import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10, - parameter USE_SRAM = 1) ( // number of past branches stored + parameter k = 10) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -59,7 +59,7 @@ module localaheadbp #(parameter XLEN, //assign IndexNextF = LHR; assign IndexM = LHRW; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -92,7 +92,7 @@ module localaheadbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), + ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRF), diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index 1fc302d1c..8037b743d 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -26,10 +26,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module localbpbasic #(parameter XLEN, +module localbpbasic import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10, - parameter USE_SRAM = 1) ( // number of past branches stored + parameter k = 10) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -56,7 +56,7 @@ module localbpbasic #(parameter XLEN, assign IndexNextF = LHR; assign IndexM = LHRM; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 835096452..3af6d7b9f 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -25,10 +25,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module localrepairbp #(parameter XLEN, +module localrepairbp import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10, - parameter USE_SRAM = 1) ( // number of past branches stored + parameter k = 10) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -58,7 +58,7 @@ module localrepairbp #(parameter XLEN, logic SpeculativeFlushedF; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -89,7 +89,7 @@ module localrepairbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), + ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRCommittedF), @@ -101,7 +101,7 @@ module localrepairbp #(parameter XLEN, assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]}; assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE; // *** replace with a small CAM - ram2p1r1wbe #(2**m, k) SHB(.clk(clk), + ram2p1r1wbe #(P, 2**m, k) SHB(.clk(clk), .ce1(~StallF), .ce2(~StallE & ~FlushE), .ra1(IndexLHRNextF), .rd1(LHRSpeculativeF), diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index aeae77f14..52e24d901 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -26,9 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module twoBitPredictor #(parameter XLEN, - parameter k = 10, - parameter USE_SRAM = 1) ( +module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, + parameter k = 10) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -54,7 +53,7 @@ module twoBitPredictor #(parameter XLEN, assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 221c8d7f8..142434de9 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -19,7 +19,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" `define NUM_REGS 32 `define NUM_CSRS 4096 @@ -29,9 +28,10 @@ `define PRINT_ALL 0 `define PRINT_CSRS 0 -module wallyTracer(rvviTrace rvvi); - localparam NUMREGS = `E_SUPPORTED ? 16 : 32; +module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); + + localparam NUMREGS = P.E_SUPPORTED ? 16 : 32; // wally specific signals logic reset; @@ -39,8 +39,8 @@ module wallyTracer(rvviTrace rvvi); logic InstrValidD, InstrValidE; logic StallF, StallD; logic STATUS_SXL, STATUS_UXL; - logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; - logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; + logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; + logic [P.XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic InstrValidM, InstrValidW; logic StallE, StallM, StallW; logic FlushD, FlushE, FlushM, FlushW; @@ -48,16 +48,16 @@ module wallyTracer(rvviTrace rvvi); logic IntrF, IntrD, IntrE, IntrM, IntrW; logic HaltM, HaltW; logic [1:0] PrivilegeModeW; - logic [`XLEN-1:0] rf[NUMREGS]; + logic [P.XLEN-1:0] rf[NUMREGS]; logic [NUMREGS-1:0] rf_wb; logic [4:0] rf_a3; logic rf_we3; - logic [`XLEN-1:0] frf[32]; + logic [P.XLEN-1:0] frf[32]; logic [`NUM_REGS-1:0] frf_wb; logic [4:0] frf_a4; logic frf_we4; - logic [`XLEN-1:0] CSRArray [logic[11:0]]; - logic [`XLEN-1:0] CSRArrayOld [logic[11:0]]; + logic [P.XLEN-1:0] CSRArray [logic[11:0]]; + logic [P.XLEN-1:0] CSRArrayOld [logic[11:0]]; logic [`NUM_CSRS-1:0] CSR_W; logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; @@ -102,8 +102,8 @@ module wallyTracer(rvviTrace rvvi); // PMPCFG space is 0-15 3a0 - 3af int i, i4, i8, csrid; - logic [`XLEN-1:0] pmp; - for (i=0; i<`PMP_ENTRIES; i+=8) begin + logic [P.XLEN-1:0] pmp; + for (i=0; i Date: Thu, 15 Jun 2023 14:08:13 -0500 Subject: [PATCH 25/28] Deleted remaining old configs except fpga as I still need to create the parameterized version. --- config/rv32e/wally-config.vh | 156 ----------------------------- config/rv32gc/wally-config.vh | 155 ----------------------------- config/rv32i/wally-config.vh | 156 ----------------------------- config/rv32imc/wally-config.vh | 155 ----------------------------- config/rv64fpquad/wally-config.vh | 158 ------------------------------ config/rv64i/wally-config.vh | 158 ------------------------------ 6 files changed, 938 deletions(-) delete mode 100644 config/rv32e/wally-config.vh delete mode 100644 config/rv32gc/wally-config.vh delete mode 100644 config/rv32i/wally-config.vh delete mode 100644 config/rv32imc/wally-config.vh delete mode 100644 config/rv64fpquad/wally-config.vh delete mode 100644 config/rv64i/wally-config.vh diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh deleted file mode 100644 index 700117e3d..000000000 --- a/config/rv32e/wally-config.vh +++ /dev/null @@ -1,156 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -// E -`define MISA (32'h00000010) -`define ZICSR_SUPPORTED 0 -`define ZIFENCEI_SUPPORTED 0 -`define COUNTERS 0 -`define ZICOUNTERS_SUPPORTED 0 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 0 -`define ICACHE_SUPPORTED 0 -`define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 0 -`define BIGENDIAN_SUPPORTED 0 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 0 -`define DTLB_ENTRIES 0 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 1 -`define IDIV_ON_FPU 0 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 32'h80000000 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h007FFFFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h007FFFFF -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 -`define UNCORE_RAM_BASE 34'h80000000 -`define UNCORE_RAM_RANGE 34'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 34'h80000000 -`define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b0 -`define CLINT_BASE 34'h02000000 -`define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b0 -`define GPIO_BASE 34'h10060000 -`define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b0 -`define UART_BASE 34'h10000000 -`define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b0 -`define PLIC_BASE 34'h0C000000 -`define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 34'h00012100 -`define SDC_RANGE 34'h0000001F - -// Bus Interface width -`define AHBW 32 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 6 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 0 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh deleted file mode 100644 index 4eb71c54e..000000000 --- a/config/rv32gc/wally-config.vh +++ /dev/null @@ -1,155 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 1 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 1 -`define ICACHE_SUPPORTED 1 -`define VIRTMEM_SUPPORTED 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 32'h80000000 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h007FFFFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h007FFFFF -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 -`define UNCORE_RAM_BASE 34'h80000000 -`define UNCORE_RAM_RANGE 34'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 34'h80000000 -`define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 34'h02000000 -`define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 34'h10060000 -`define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 34'h10000000 -`define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 34'h0C000000 -`define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 34'h00012100 -`define SDC_RANGE 34'h0000001F - -// Bus Interface width -`define AHBW 32 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE" // "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 16 -`define BPRED_NUM_LHR 8 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 1 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 1 -`define ZBB_SUPPORTED 1 -`define ZBC_SUPPORTED 1 -`define ZBS_SUPPORTED 1 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh deleted file mode 100644 index 585499169..000000000 --- a/config/rv32i/wally-config.vh +++ /dev/null @@ -1,156 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -// I -`define MISA (32'h00000104) -`define ZICSR_SUPPORTED 0 -`define ZIFENCEI_SUPPORTED 0 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 0 -`define DCACHE_SUPPORTED 0 -`define ICACHE_SUPPORTED 0 -`define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 0 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 0 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 32'h80000000 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define DTIM_SUPPORTED 1'b1 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h007FFFFF -`define IROM_SUPPORTED 1'b1 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h007FFFFF -`define BOOTROM_SUPPORTED 1'b0 -`define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b0 -`define UNCORE_RAM_BASE 34'h80000000 -`define UNCORE_RAM_RANGE 34'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 34'h80000000 -`define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b0 -`define CLINT_BASE 34'h02000000 -`define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b0 -`define GPIO_BASE 34'h10060000 -`define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b0 -`define UART_BASE 34'h10000000 -`define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b0 -`define PLIC_BASE 34'h0C000000 -`define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 34'h00012100 -`define SDC_RANGE 34'h0000001F - -// Bus Interface width -`define AHBW 32 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 6 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 0 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh deleted file mode 100644 index 093d92bd7..000000000 --- a/config/rv32imc/wally-config.vh +++ /dev/null @@ -1,155 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 0 -`define ICACHE_SUPPORTED 0 -`define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 0 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 0 -`define DTLB_ENTRIES 0 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 2 -`define IDIV_ON_FPU 0 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 32'h80000000 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define DTIM_SUPPORTED 1'b1 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h007FFFFF -`define IROM_SUPPORTED 1'b1 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h007FFFFF -`define BOOTROM_SUPPORTED 1'b0 -`define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b0 -`define UNCORE_RAM_BASE 34'h80000000 -`define UNCORE_RAM_RANGE 34'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 34'h80000000 -`define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 34'h02000000 -`define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 34'h10060000 -`define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 34'h10000000 -`define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 34'h0C000000 -`define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 34'h00012100 -`define SDC_RANGE 34'h0000001F - -// Bus Interface width -`define AHBW 32 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 6 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 0 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh deleted file mode 100644 index 45725645f..000000000 --- a/config/rv64fpquad/wally-config.vh +++ /dev/null @@ -1,158 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -// IEEE 754 compliance -`define IEEE754 0 - -// MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 1 -`define SSTC_SUPPORTED 0 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 1 -`define ICACHE_SUPPORTED 1 -`define VIRTMEM_SUPPORTED 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 64'h0000000080000000 - -// Bus Interface width -`define AHBW 64 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h007FFFFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h007FFFFF -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 -`define UNCORE_RAM_BASE 56'h80000000 -`define UNCORE_RAM_RANGE 56'h7FFFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 6 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 0 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh deleted file mode 100644 index 61ac725db..000000000 --- a/config/rv64i/wally-config.vh +++ /dev/null @@ -1,158 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -// IEEE 754 compliance -`define IEEE754 0 - -// MISA RISC-V configuration per specification -`define MISA (32'h00000104) -`define ZICSR_SUPPORTED 0 -`define ZIFENCEI_SUPPORTED 0 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 0 -`define DCACHE_SUPPORTED 0 -`define ICACHE_SUPPORTED 0 -`define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 0 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 0 -`define DTLB_ENTRIES 0 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 0 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 64'h0000000080000000 - -// Bus Interface width -`define AHBW (`XLEN) - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Physiccal Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -`define DTIM_SUPPORTED 1'b1 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h007FFFFF -`define IROM_SUPPORTED 1'b1 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h007FFFFF -`define BOOTROM_SUPPORTED 1'b0 -`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b0 -`define UNCORE_RAM_BASE 56'h80000000 -`define UNCORE_RAM_RANGE 56'h7FFFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b0 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b0 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b0 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b0 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 6 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 0 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 - -// Memory synthesis configuration -`define USE_SRAM 0 From 3c4677ef6370f6ac4f03626b83b7e768a3207f60 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jun 2023 14:57:05 -0500 Subject: [PATCH 26/28] Major cleanup of testbench. --- testbench/testbench.sv | 189 ++++++++++++++++------------------------- 1 file changed, 74 insertions(+), 115 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 1b95b5cc4..b85bdb4c5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -87,8 +87,6 @@ module testbench; logic Validate; logic SelectTest; - // check assertions for a legal configuration - riscvassertions #(P) riscvassertions(); // pick tests based on modes supported initial begin @@ -204,89 +202,52 @@ module testbench; if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET; else CurrState <= #1 NextState; - + // fsm next state logic always_comb begin - reset_ext = 0; - ResetMem = 0; - LoadMem = 0; - ResetCntEn = 0; - ResetCntRst = 0; - Validate = 0; - SelectTest = 0; // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests // and tests[0] == "2" refers to WallyRiscvArchTests riscofTest = tests[0] == "1" | tests[0] == "2"; pathname = tvpaths[tests[0].atoi()]; case(CurrState) - STATE_TESTBENCH_RESET: begin - NextState = STATE_INIT_TEST; - reset_ext = 1; - end - STATE_INIT_TEST: begin - NextState = STATE_RESET_MEMORIES; - ResetCntRst = 1; - SelectTest = 1; - reset_ext = 1; - end - STATE_RESET_MEMORIES: begin - NextState = STATE_RESET_MEMORIES2; - reset_ext = 1; - if (TEST == "coremark") ResetMem = 1; // this initialization is very expensive, only do it for coremark. - end - STATE_RESET_MEMORIES2: begin // Give the reset enough time to ensure the bus is reset before loading the memories. - NextState = STATE_LOAD_MEMORIES; - reset_ext = 1; - // this initialization is very expensive, only do it for coremark. - if (TEST == "coremark") ResetMem = 1; - end - STATE_LOAD_MEMORIES: begin - NextState = STATE_RESET_TEST; - reset_ext = 1; - LoadMem = 1; - end - STATE_RESET_TEST: begin - reset_ext = 1; - ResetCntEn = 1; - if(ResetCount < ResetThreshold) begin - NextState = STATE_RESET_TEST; - end else begin - NextState = STATE_RUN_TEST; - end - end - STATE_RUN_TEST: - if(DCacheFlushStart) begin - NextState = STATE_CHECK_TEST; - end else begin - NextState = STATE_RUN_TEST; - end - STATE_CHECK_TEST: begin - if (DCacheFlushDone) begin - NextState = STATE_VALIDATE; - end else begin - NextState = STATE_CHECK_TEST_WAIT; - end - end - STATE_CHECK_TEST_WAIT: begin - if(DCacheFlushDone) begin - NextState = STATE_VALIDATE; - end else begin - NextState = STATE_CHECK_TEST_WAIT; - end - end - STATE_VALIDATE: begin - NextState = STATE_INIT_TEST; - Validate = '1; - end - STATE_INCR_TEST: begin - NextState = STATE_INIT_TEST; - end - default: NextState = STATE_TESTBENCH_RESET; + STATE_TESTBENCH_RESET: NextState = STATE_INIT_TEST; + STATE_INIT_TEST: NextState = STATE_RESET_MEMORIES; + STATE_RESET_MEMORIES: NextState = STATE_RESET_MEMORIES2; + STATE_RESET_MEMORIES2: NextState = STATE_LOAD_MEMORIES; // Give the reset enough time to ensure the bus is reset before loading the memories. + STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST; + STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST; + else NextState = STATE_RUN_TEST; + STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST; + else NextState = STATE_RUN_TEST; + STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE; + else NextState = STATE_CHECK_TEST_WAIT; + STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE; + else NextState = STATE_CHECK_TEST_WAIT; + STATE_VALIDATE: NextState = STATE_INIT_TEST; + STATE_INCR_TEST: NextState = STATE_INIT_TEST; + default: NextState = STATE_TESTBENCH_RESET; endcase end // always_comb + // fsm output control logic + assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | + CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | + CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST; + // this initialization is very expensive, only do it for coremark. + assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark"; + assign LoadMem = CurrState == STATE_LOAD_MEMORIES; + assign ResetCntRst = CurrState == STATE_INIT_TEST; + assign ResetCntEn = CurrState == STATE_RESET_TEST; + assign Validate = CurrState == STATE_VALIDATE; + assign SelectTest = CurrState == STATE_INIT_TEST; + // fsm reset counter + counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); + + //////////////////////////////////////////////////////////////////////////////// + // Find the test vector files and populate the PC to function label converter + //////////////////////////////////////////////////////////////////////////////// + assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; always @(posedge clk) begin - if(SelectTest) begin if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"}; @@ -305,14 +266,17 @@ module testbench; end end + //////////////////////////////////////////////////////////////////////////////// + // Verify the test ran correctly by checking the memory against a known signature. + //////////////////////////////////////////////////////////////////////////////// if(TestBenchReset) test = 1; + if (TEST == "coremark") + if (dut.core.EcallFaultM) begin + $display("Benchmark: coremark is done."); + $stop; + end if(Validate) begin - if (TEST == "coremark") - if (dut.core.EcallFaultM) begin - $display("Benchmark: coremark is done."); - $stop; - end - else if (TEST == "embench") begin + if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file // this contains instret and cycles for start and end of test run, used by embench // python speed script to calculate embench speed score. @@ -347,13 +311,10 @@ module testbench; end end - counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); - assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; //////////////////////////////////////////////////////////////////////////////// // Some memories are not reset, but should be zeros or set to some initial value for simulation //////////////////////////////////////////////////////////////////////////////// - integer adrindex; always @(posedge clk) begin if (ResetMem) // program memory is sometimes reset @@ -394,8 +355,11 @@ module testbench; $display("Read memfile %s", memfilename); end end - + //////////////////////////////////////////////////////////////////////////////// + // Actual hardware + //////////////////////////////////////////////////////////////////////////////// + // instantiate device to be tested assign GPIOIN = 0; assign UARTSin = 1; @@ -403,12 +367,10 @@ module testbench; if(P.EXT_MEM_SUPPORTED) begin ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), - .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, - .HWSTRB); + .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); end else begin assign HREADYEXT = 1; - assign HRESPEXT = 0; - assign HRDATAEXT = 0; + assign {HRESPEXT, HRDATAEXT} = '0; end if(P.FPGA) begin : sdcard @@ -426,9 +388,29 @@ module testbench; end wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); + .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, + .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); + + // generate clock to sequence tests + always begin + clk = 1; # 5; clk = 0; # 5; + end + + //////////////////////////////////////////////////////////////////////////////// + // Support logic + //////////////////////////////////////////////////////////////////////////////// + + watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck + riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration + loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) + loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename); + + // track the current function or global label + if (DEBUG == 1 | (PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName + FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), + .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); + end // Track names of instructions string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; @@ -440,22 +422,6 @@ module testbench; dut.core.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - // generate clock to sequence tests - always - begin - clk = 1; # 5; clk = 0; # 5; - // if ($time % 100000 == 0) $display("Time is %0t", $time); - end - - - // track the current function or global label - if (DEBUG == 1 | (PrintHPMCounters & P.ZICOUNTERS_SUPPORTED)) begin : FunctionName - FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), - .clk(clk), - .ProgramAddrMapFile(ProgramAddrMapFile), - .ProgramLabelMapFile(ProgramLabelMapFile)); - end - // Termination condition // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed // or sw gp,-56(t0) for new Imperas tests @@ -472,14 +438,7 @@ module testbench; ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); - DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), - .reset(reset), - .start(DCacheFlushStart), - .done(DCacheFlushDone)); - - watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); - loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) - loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename); + DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); task automatic CheckSignature; // This task must be declared inside this module as it needs access to parameter P. There is From 6d31936e895f392bc3e2456b3c0107b054b9220d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jun 2023 15:39:51 -0500 Subject: [PATCH 27/28] Added comment to uart LCR to check reset value after updating FPGA. --- src/uncore/uartPC16550D.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv index 46f20386d..ad1e0f259 100644 --- a/src/uncore/uartPC16550D.sv +++ b/src/uncore/uartPC16550D.sv @@ -138,7 +138,7 @@ module uartPC16550D #(parameter UART_PRESCALE) ( if (~PRESETn) begin // Table 3 Reset Configuration IER <= #1 4'b0; FCR <= #1 8'b0; - LCR <= #1 8'b11; // spec says to reset to 0, but FPGA needs to reset to 8 data bits + LCR <= #1 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed. MCR <= #1 5'b0; LSR <= #1 8'b01100000; MSR <= #1 4'b0; From 110a41c04644cce35e9e2280484c9c458ca07b67 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jun 2023 16:18:37 -0500 Subject: [PATCH 28/28] Have the linux testbench working in the mean time. Before the consolidation. --- testbench/testbench-linux.sv | 100 +++++++++++++++++------------------ testbench/testbench.sv | 3 -- 2 files changed, 48 insertions(+), 55 deletions(-) diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index 908660ffe..5c83aca29 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -24,7 +24,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" +`include "config.vh" +import cvw::*; `define DEBUG_TRACE 0 // Debug Levels @@ -47,12 +48,7 @@ module testbench; parameter NO_SPOOFING = 0; - - - - - - +`include "parameter-defs.vh" //////////////////////////////////////////////////////////////////////////////////// @@ -85,40 +81,40 @@ module testbench; integer TokenIndex``STAGE; \ integer MarkerIndex``STAGE; \ integer NumCSR``STAGE; \ - logic [`XLEN-1:0] ExpectedPC``STAGE; \ + logic [P.XLEN-1:0] ExpectedPC``STAGE; \ logic [31:0] ExpectedInstr``STAGE; \ string text``STAGE; \ string MemOp``STAGE; \ string RegWrite``STAGE; \ integer ExpectedRegAdr``STAGE; \ - logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ - logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ + logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \ + logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ string ExpectedCSRArray``STAGE[10:0]; \ - logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? + logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? `DECLARE_TRACE_SCANNER_SIGNALS(E) `DECLARE_TRACE_SCANNER_SIGNALS(M) // M-stage expected values logic checkInstrM; integer MIPexpected, SIPexpected; string name; - logic [`AHBW-1:0] readDataExpected; + logic [P.AHBW-1:0] readDataExpected; // W-stage expected values logic checkInstrW; - logic [`XLEN-1:0] ExpectedPCW; + logic [P.XLEN-1:0] ExpectedPCW; logic [31:0] ExpectedInstrW; string textW; string RegWriteW; integer ExpectedRegAdrW; - logic [`XLEN-1:0] ExpectedRegValueW; + logic [P.XLEN-1:0] ExpectedRegValueW; string MemOpW; - logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; + logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; integer NumCSRW; string ExpectedCSRArrayW[10:0]; - logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0]; - logic [`XLEN-1:0] ExpectedIntType; + logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0]; + logic [P.XLEN-1:0] ExpectedIntType; integer NumCSRWIndex; integer NumCSRPostWIndex; - logic [`XLEN-1:0] InstrCountW; + logic [P.XLEN-1:0] InstrCountW; // ========== Interrupt parsing & spoofing ========== string interrupt; string interruptLine; @@ -132,7 +128,7 @@ module testbench; string interruptDesc; integer NextMIPexpected, NextSIPexpected; integer NextMepcExpected; - logic [`XLEN-1:0] AttemptedInstructionCount; + logic [P.XLEN-1:0] AttemptedInstructionCount; // ========== Misc Aliases ========== `define RF dut.core.ieu.dp.regf.rf `define PC dut.core.ifu.pcreg.q @@ -238,14 +234,14 @@ module testbench; initial begin reset_ext <= 1; # 22; reset_ext <= 0; end always begin clk <= 1; # 5; clk <= 0; # 5; end // Wally Interface - logic [`AHBW-1:0] HRDATAEXT; + logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic HCLK, HRESETn; logic HREADY; logic HSELEXT; - logic [`PA_BITS-1:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic [`XLEN/8-1:0] HWSTRB; + logic [P.PA_BITS-1:0] HADDR; + logic [P.AHBW-1:0] HWDATA; + logic [P.XLEN/8-1:0] HWSTRB; logic HWRITE; logic [2:0] HSIZE; logic [2:0] HBURST; @@ -268,7 +264,7 @@ module testbench; assign UARTSin = 1; // Wally - wallypipelinedsoc dut(.clk, .reset, .reset_ext, + wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext, .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, @@ -278,18 +274,18 @@ module testbench; // W-stage hardware not needed by Wally itself parameter nop = 'h13; - logic [`XLEN-1:0] PCW; + logic [P.XLEN-1:0] PCW; logic [31:0] InstrW; logic InstrValidW; - logic [`XLEN-1:0] IEUAdrW, WriteDataW; + logic [P.XLEN-1:0] IEUAdrW, WriteDataW; logic TrapW; `define FLUSHW dut.core.FlushW `define STALLW dut.core.StallW - flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); + flopenrc #(P.XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW); flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); - flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); - flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); + flopenrc #(P.XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); + flopenrc #(P.XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); @@ -365,29 +361,29 @@ module testbench; end genvar i; - `INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1); - `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0); - `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); + `INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [P.XLEN-1:0],31,1); + `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [P.XLEN-1:0],P.COUNTERS-1,0); + `INIT_CHECKPOINT_VAL(PC, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(MEDELEG, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(MIDELEG, [P.XLEN-1:0]); if(!NO_SPOOFING) begin `INIT_CHECKPOINT_VAL(MIE, [11:0]); `INIT_CHECKPOINT_VAL(MIP, [11:0]); end - `INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(SEPC, [`XLEN-1:0]); + `INIT_CHECKPOINT_VAL(MCAUSE, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(SCAUSE, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(MEPC, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(SEPC, [P.XLEN-1:0]); `INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]); `INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]); - `INIT_CHECKPOINT_VAL(MSCRATCH, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(SSCRATCH, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(MTVEC, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(STVEC, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]); + `INIT_CHECKPOINT_VAL(MSCRATCH, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(SSCRATCH, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(MTVEC, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(STVEC, [P.XLEN-1:0]); + `INIT_CHECKPOINT_VAL(SATP, [P.XLEN-1:0]); `INIT_CHECKPOINT_VAL(PRIV, [1:0]); - `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); - `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:0],1,0); + `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],P.PLIC_NUM_SRC,1); + `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [P.PLIC_NUM_SRC:0],1,0); `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0); // UART checkpointing does not cover entire UART state // Many UART registers are difficult to initialize because under the hood @@ -402,8 +398,8 @@ module testbench; `INIT_CHECKPOINT_VAL(UART_SCR, [7:0]); // xSTATUS need to be handled manually because the most upstream signals // are made of individual bits, not registers - `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0); - `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0); + `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [P.XLEN-1:0],0,0); + `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [P.XLEN-1:0],0,0); // ========== INITIALIZATION ========== initial begin @@ -458,7 +454,7 @@ module testbench; force {`STATUS_SPIE} = initMSTATUS[0][5]; force {`STATUS_MIE} = initMSTATUS[0][3]; force {`STATUS_SIE} = initMSTATUS[0][1]; - force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts + force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][P.PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][P.PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts force `INSTRET = CHECKPOINT; while (reset!==1) #1; while (reset!==0) #1; @@ -789,7 +785,7 @@ module testbench; //////////////////////////////// Extra Features /////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // Function Tracking - FunctionName FunctionName(.reset(reset), + FunctionName #(P) FunctionName(.reset(reset), .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); @@ -814,12 +810,12 @@ module testbench; * explanation of the below algorithm. */ logic SvMode, PTE_R, PTE_X; - logic [`XLEN-1:0] SATP, PTE; + logic [P.XLEN-1:0] SATP, PTE; logic [55:0] BaseAdr, PAdr; logic [8:0] VPN [2:0]; logic [11:0] Offset; - function logic [`XLEN-1:0] adrTranslator( - input logic [`XLEN-1:0] adrIn); + function logic [P.XLEN-1:0] adrTranslator( + input logic [P.XLEN-1:0] adrIn); begin int i; // Grab the SATP register from privileged unit diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 636135a99..2cdde5129 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,9 +30,6 @@ import cvw::*; -import cvw::*; - - module testbench; /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */