diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
deleted file mode 100644
index 700117e3d..000000000
--- a/config/rv32e/wally-config.vh
+++ /dev/null
@@ -1,156 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// E
-`define MISA (32'h00000010) 
-`define ZICSR_SUPPORTED 0
-`define ZIFENCEI_SUPPORTED 0
-`define COUNTERS 0
-`define ZICOUNTERS_SUPPORTED 0
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 0 
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 0
-`define DTLB_ENTRIES 0
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 1
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b0
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b0
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b0
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b0
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10 
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BPRED_NUM_LHR 6
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
deleted file mode 100644
index 4eb71c54e..000000000
--- a/config/rv32gc/wally-config.vh
+++ /dev/null
@@ -1,155 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 1
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 1
-`define ICACHE_SUPPORTED 1
-`define VIRTMEM_SUPPORTED 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE" // "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 16
-`define BPRED_NUM_LHR 8
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 1
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 1
-`define ZBB_SUPPORTED 1
-`define ZBC_SUPPORTED 1
-`define ZBS_SUPPORTED 1
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
deleted file mode 100644
index 585499169..000000000
--- a/config/rv32i/wally-config.vh
+++ /dev/null
@@ -1,156 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// I
-`define MISA (32'h00000104)
-`define ZICSR_SUPPORTED 0
-`define ZIFENCEI_SUPPORTED 0
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 0
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 0
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b1
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b1
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b0
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b0
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b0
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b0
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b0
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b0
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10 
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BPRED_NUM_LHR 6
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
deleted file mode 100644
index 093d92bd7..000000000
--- a/config/rv32imc/wally-config.vh
+++ /dev/null
@@ -1,155 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 0
-`define DTLB_ENTRIES 0
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 2
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define DTIM_SUPPORTED 1'b1
-`define DTIM_BASE       34'h80000000
-`define DTIM_RANGE      34'h007FFFFF
-`define IROM_SUPPORTED 1'b1
-`define IROM_BASE       34'h80000000
-`define IROM_RANGE      34'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b0
-`define BOOTROM_BASE   34'h00001000 
-`define BOOTROM_RANGE  34'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b0
-`define UNCORE_RAM_BASE       34'h80000000
-`define UNCORE_RAM_RANGE      34'h07FFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       34'h80000000
-`define EXT_MEM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   34'h10060000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BPRED_NUM_LHR 6
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
deleted file mode 100644
index 45725645f..000000000
--- a/config/rv64fpquad/wally-config.vh
+++ /dev/null
@@ -1,158 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 1
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 1
-`define ICACHE_SUPPORTED 1
-`define VIRTMEM_SUPPORTED 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 64'h0000000080000000
-
-// Bus Interface width
-`define AHBW 64
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Physiccal Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       56'h80000000
-`define DTIM_RANGE      56'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       56'h80000000
-`define IROM_RANGE      56'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTROM_RANGE  56'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       56'h80000000
-`define UNCORE_RAM_RANGE      56'h7FFFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       56'h80000000
-`define EXT_MEM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   56'h10060000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BPRED_NUM_LHR 6
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
deleted file mode 100644
index 1dd3d7f4f..000000000
--- a/config/rv64gc/wally-config.vh
+++ /dev/null
@@ -1,159 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 1
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 1
-`define DCACHE_SUPPORTED 1
-`define ICACHE_SUPPORTED 1
-`define VIRTMEM_SUPPORTED 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 1
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 64'h0000000080000000
-
-// Bus Interface width
-`define AHBW 64
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define DTIM_SUPPORTED 1'b0
-`define DTIM_BASE       56'h80000000
-`define DTIM_RANGE      56'h007FFFFF
-`define IROM_SUPPORTED 1'b0
-`define IROM_BASE       56'h80000000
-`define IROM_RANGE      56'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b1
-`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTROM_RANGE  56'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b1
-`define UNCORE_RAM_BASE       56'h80000000
-`define UNCORE_RAM_RANGE      56'h7FFFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       56'h80000000
-`define EXT_MEM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   56'h10060000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 1
-//`define BPRED_TYPE "BP_GLOBAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_TYPE "BP_GSHARE" // "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BPRED_NUM_LHR 4
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 1
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 1
-`define ZBB_SUPPORTED 1
-`define ZBC_SUPPORTED 1
-`define ZBS_SUPPORTED 1
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
deleted file mode 100644
index 61ac725db..000000000
--- a/config/rv64i/wally-config.vh
+++ /dev/null
@@ -1,158 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define FPGA 0
-`define QEMU 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// IEEE 754 compliance
-`define IEEE754 0
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104)
-`define ZICSR_SUPPORTED 0
-`define ZIFENCEI_SUPPORTED 0
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 0
-`define ZFH_SUPPORTED 0
-`define SSTC_SUPPORTED 0
-
-// LSU microarchitectural Features
-`define BUS_SUPPORTED 0
-`define DCACHE_SUPPORTED 0
-`define ICACHE_SUPPORTED 0
-`define VIRTMEM_SUPPORTED 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1 
-`define BIGENDIAN_SUPPORTED 0
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 0
-`define DTLB_ENTRIES 0
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_LINELENINBITS 512
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_LINELENINBITS 512
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
-`define IDIV_ON_FPU 0
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 0
-
-// Address space
-`define RESET_VECTOR 64'h0000000080000000
-
-// Bus Interface width
-`define AHBW (`XLEN)
-
-// WFI Timeout Wait
-`define WFI_TIMEOUT_BIT 16
-
-// Peripheral Physiccal Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define DTIM_SUPPORTED 1'b1
-`define DTIM_BASE       56'h80000000
-`define DTIM_RANGE      56'h007FFFFF
-`define IROM_SUPPORTED 1'b1
-`define IROM_BASE       56'h80000000
-`define IROM_RANGE      56'h007FFFFF
-`define BOOTROM_SUPPORTED 1'b0
-`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTROM_RANGE  56'h00000FFF
-`define UNCORE_RAM_SUPPORTED 1'b0
-`define UNCORE_RAM_BASE       56'h80000000
-`define UNCORE_RAM_RANGE      56'h7FFFFFFF
-`define EXT_MEM_SUPPORTED 1'b0
-`define EXT_MEM_BASE       56'h80000000
-`define EXT_MEM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b0
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b0
-`define GPIO_BASE   56'h10060000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b0
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b0
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b0
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 10
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 10
-
-`define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BPRED_NUM_LHR 6
-`define BTB_SIZE 10
-
-`define SVADU_SUPPORTED 0
-`define ZMMUL_SUPPORTED 0
-
-// FPU division architecture
-`define RADIX 32'h4
-`define DIVCOPIES 32'h4
-
-// bit manipulation
-`define ZBA_SUPPORTED 0
-`define ZBB_SUPPORTED 0
-`define ZBC_SUPPORTED 0
-`define ZBS_SUPPORTED 0
-
-// Memory synthesis configuration
-`define USE_SRAM 0
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
index e897f3dd0..713a947e8 100644
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@@ -81,7 +81,7 @@ parameter cvw_t P = '{
                        // *** definitely need to fix this.
                        // it thinks we are casting from the enum type to BPRED_TYPE.
   BPRED_TYPE :        BPRED_TYPE,
-                       /* verilator lint_off ENUMVALUE */
+                       /* verilator lint_on ENUMVALUE */
   BPRED_SIZE :        BPRED_SIZE,
   BPRED_NUM_LHR : BPRED_NUM_LHR,                       
   BTB_SIZE :        BTB_SIZE,
diff --git a/sim/lint-wally b/sim/lint-wally
index 7dd635328..6db56b0a9 100755
--- a/sim/lint-wally
+++ b/sim/lint-wally
@@ -8,7 +8,7 @@ basepath=$(dirname $0)/..
 for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
 #for config in  rv64gc; do
     echo "$config linting..."
-    if !($verilator --no-timing --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+    if !($verilator --no-timing --lint-only "$@" --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch
index 46c35c75c..f2c2a3c30 100755
--- a/sim/sim-wally-batch
+++ b/sim/sim-wally-batch
@@ -1 +1 @@
-vsim -c -do "do wally-batch.do rv32gc wally32priv"
+vsim -c -do "do wally-batch.do rv64gc wally64priv"
diff --git a/sim/verilate b/sim/verilate
index 345e17ab9..9555322f9 100755
--- a/sim/verilate
+++ b/sim/verilate
@@ -7,8 +7,8 @@ verilator=`which verilator`
 basepath=$(dirname $0)/..
 #for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
 for config in  rv64gc; do
-    echo "$config linting..."
-    if !($verilator --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+    echo "$config simulating..."
+    if !($verilator --timescale "1ns/1ns" --timing --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/common/*.sv $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
diff --git a/sim/wave.do b/sim/wave.do
index 2a48308ef..e9461d589 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -11,14 +11,14 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
 add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
@@ -61,10 +61,10 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
 add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
@@ -94,13 +94,13 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
-add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
 add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
@@ -170,6 +170,7 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/core/HRDATA
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
@@ -177,200 +178,200 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
-add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
-add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CacheSet
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM[62]}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CacheSet
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
+add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
+add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -389,18 +390,6 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/un
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
 add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
 add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
 add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
@@ -458,13 +447,14 @@ add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/d
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
-add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
+add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HRDATA
 add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
@@ -592,16 +582,39 @@ add wave -noupdate -group {branch direction} -expand -group conditions /testbenc
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate /testbench/dut/core/ifu/PCF
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
+add wave -noupdate /testbench/LoadMem
+add wave -noupdate /testbench/CurrState
+add wave -noupdate /testbench/DCacheFlushStart
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/InstrMName
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/c/InstrValidM
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/ecf
+add wave -noupdate /testbench/ecf
+add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/ce
+add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/we
+add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/addr
+add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/dout
 add wave -noupdate /testbench/reset
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPDirPredD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewBPDirPredM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {12208 ns} 1} {{Cursor 4} {1472797 ns} 0}
-quietly wave cursor active 2
+WaveRestoreCursors {{Cursor 4} {320072 ns} 0} {{Cursor 4} {19809168 ns} 1}
+quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
 configure wave -justifyvalue left
@@ -616,4 +629,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {1472724 ns} {1472832 ns}
+WaveRestoreZoom {319935 ns} {320329 ns}
diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index 55e2ef03d..1275d0cbc 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -27,7 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module cache #(parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
+module cache import cvw::*; #(parameter cvw_t P,
+                              parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
   input  logic                   clk,
   input  logic                   reset,
   input  logic                   Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
@@ -112,7 +113,7 @@ module cache #(parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, W
     AdrSelMuxSel, CacheSet);
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
-  cacheway #(PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
+  cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
     .SetValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay,
     .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index bf7d16834..5fb00dc90 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module cacheLRU
   #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
   input  logic                clk, 
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 544e3454e..0909ae82d 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   input  logic       clk,
   input  logic       reset,
diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 81431c3b0..0a5c7b6e5 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -27,7 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
+module cacheway import cvw::*; #(parameter cvw_t P, 
+                  parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
                   OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
   input  logic                        clk,
   input  logic                        reset,
@@ -108,7 +109,7 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
   // Tag Array
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
+  ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
     .addr(CacheSet), .dout(ReadTag),
     .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
 
@@ -130,12 +131,12 @@ module cacheway #(parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN =
   
   for(words = 0; words < NUMSRAM; words++) begin: word
     if (!READ_ONLY_CACHE) begin:wordram
-      ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
+      ram1p1rwbe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
     end else begin:wordram // no byte-enable needed for i$.
-      ram1p1rwe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
+      ram1p1rwe #(.P(P), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSet),
       .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
       .we(SelectedWriteWordEn));
diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv
index a70a80b1e..db80cfc83 100644
--- a/src/cache/subcachelineread.sv
+++ b/src/cache/subcachelineread.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module subcachelineread #(parameter LINELEN, WORDLEN, 
   parameter MUXINTERVAL )(     // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
   input  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,       // Physical address 
diff --git a/src/generic/adder.sv b/src/generic/adder.sv
index 81b6f5043..4d341d6c1 100644
--- a/src/generic/adder.sv
+++ b/src/generic/adder.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module adder #(parameter WIDTH=8) (
   input  logic [WIDTH-1:0] a, b,
   output logic [WIDTH-1:0] y
diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv
index d322216b3..f8d675b33 100644
--- a/src/generic/aplusbeq0.sv
+++ b/src/generic/aplusbeq0.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module aplusbeq0 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] a, b,
   output logic             zero
@@ -40,4 +38,4 @@ module aplusbeq0 #(parameter WIDTH = 8) (
   assign x = a ^ b;
   assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0};
   assign zero = (x == orshift);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv
index 5a9cf21f0..dd473b307 100644
--- a/src/generic/arrs.sv
+++ b/src/generic/arrs.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module arrs(
   input  logic  clk,
   input  logic  areset,
diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv
index c09f98f2c..c0150133c 100644
--- a/src/generic/clockgater.sv
+++ b/src/generic/clockgater.sv
@@ -24,16 +24,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module clockgater (
+module clockgater #(parameter FPGA) (
   input  logic E,
   input  logic SE,
   input  logic CLK,
   output logic ECLK
 );
 
-  if (`FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
+  if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
   else begin
     // *** BUG 
     // VERY IMPORTANT.
diff --git a/src/generic/counter.sv b/src/generic/counter.sv
index 3e63d87ee..faba2e5e5 100644
--- a/src/generic/counter.sv
+++ b/src/generic/counter.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module counter #(parameter WIDTH=8) (
   input  logic             clk, reset, en,
   output logic [WIDTH-1:0] q
diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv
index 807a6d6ca..6284a454c 100644
--- a/src/generic/decoder.sv
+++ b/src/generic/decoder.sv
@@ -23,8 +23,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module decoder #(parameter BINARY_BITS = 3) (
   input  logic [BINARY_BITS-1:0]      binary,
   output logic [(2**BINARY_BITS)-1:0] onehot
diff --git a/src/generic/flop/flop.sv b/src/generic/flop/flop.sv
index 1e906dca8..97e0ac7e4 100644
--- a/src/generic/flop/flop.sv
+++ b/src/generic/flop/flop.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv
index 32e0d7dd3..2e6432519 100644
--- a/src/generic/flop/flopen.sv
+++ b/src/generic/flop/flopen.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopen #(parameter WIDTH = 8) (
   input  logic             clk, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv
index 094779c74..562c4565a 100644
--- a/src/generic/flop/flopenl.sv
+++ b/src/generic/flop/flopenl.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   input  logic clk, load, en,
   input  TYPE d,
diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv
index 3b8129e40..2c2144ab8 100644
--- a/src/generic/flop/flopenr.sv
+++ b/src/generic/flop/flopenr.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv
index b3d5a1e8e..94b2b3cb0 100644
--- a/src/generic/flop/flopenrc.sv
+++ b/src/generic/flop/flopenrc.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopenrc #(parameter WIDTH = 8) (
   input  logic             clk, reset, clear, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv
index 1f4c18051..c4fc5d01b 100644
--- a/src/generic/flop/flopens.sv
+++ b/src/generic/flop/flopens.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopens #(parameter WIDTH = 8) (
   input  logic             clk, set, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv
index b2f99b3cd..2e39ee8d6 100644
--- a/src/generic/flop/flopr.sv
+++ b/src/generic/flop/flopr.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 
diff --git a/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv
index 8275a8f96..b35e9ccce 100644
--- a/src/generic/flop/floprc.sv
+++ b/src/generic/flop/floprc.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module floprc #(parameter WIDTH = 8) (
   input  logic clk,
   input  logic reset,
diff --git a/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv
index f10efaeaf..f99088af4 100644
--- a/src/generic/flop/synchronizer.sv
+++ b/src/generic/flop/synchronizer.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module synchronizer ( 
   input  logic clk,
   input  logic d, 
diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index 8905cc551..56637c0ce 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -32,9 +32,7 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-`include "wally-config.vh"
-
-module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
+module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=44) (
   input logic                     clk,
   input logic                     ce,
   input logic [$clog2(DEPTH)-1:0] addr,
@@ -49,7 +47,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
   // ***************************************************************************
   // TRUE SRAM macro
   // ***************************************************************************
-  if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
+  if ((P.USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
     genvar index;
     // 64 x 128-bit SRAM
     logic [WIDTH-1:0] BitWriteMask;
@@ -59,7 +57,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
       .A(addr), .D(din), 
       .BWEB(~BitWriteMask), .Q(dout));
     
-  end else if ((`USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
     genvar index;
     // 64 x 44-bit SRAM
     logic [WIDTH-1:0] BitWriteMask;
@@ -69,7 +67,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
       .A(addr), .D(din), 
       .BWEB(~BitWriteMask), .Q(dout));
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
     genvar index;
     // 64 x 22-bit SRAM
     logic [WIDTH-1:0] BitWriteMask;
diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv
index f3a8a2248..24d92ff7f 100644
--- a/src/generic/mem/ram1p1rwe.sv
+++ b/src/generic/mem/ram1p1rwe.sv
@@ -30,9 +30,8 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-`include "wally-config.vh"
-
-module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
+module ram1p1rwe import cvw::* ; #(parameter cvw_t P,
+                   parameter DEPTH=64, WIDTH=44) (
   input logic                     clk,
   input logic                     ce,
   input logic [$clog2(DEPTH)-1:0] addr,
@@ -46,21 +45,21 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
   // ***************************************************************************
   // TRUE SRAM macro
   // ***************************************************************************
-  if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
+  if ((P.USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
     // 64 x 128-bit SRAM
     ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
       .BWEB('0), .Q(dout));
     
-  end else if ((`USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
     // 64 x 44-bit SRAM
     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
       .BWEB('0), .Q(dout));
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
     // 64 x 22-bit SRAM
-    ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
+    ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
       .BWEB('0), .Q(dout));     
     
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index 51e2871b4..202d0432b 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -31,9 +31,8 @@
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
 
-`include "wally-config.vh"
-
-module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
+module ram2p1r1wbe import cvw::*; #(parameter cvw_t P,
+                                    parameter DEPTH=1024, WIDTH=68) (
   input  logic                     clk,
   input  logic                     ce1, ce2,
   input  logic [$clog2(DEPTH)-1:0] ra1,
@@ -52,7 +51,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
   // TRUE Smem macro
   // ***************************************************************************
 
-  if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
+  if ((P.USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
     
     ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
@@ -64,7 +63,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
       .QA(rd1),
       .QB());
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
     
     ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
@@ -76,7 +75,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
       .QA(rd1),
       .QB());      
 
-  end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin
+  end else if ((P.USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin
 
     logic [SRAMWIDTH-1:0]     SRAMReadData;      
     logic [SRAMWIDTH-1:0]     SRAMWriteData;      
diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
index ef9c6da37..497356788 100644
--- a/src/generic/mem/rom1p1r.sv
+++ b/src/generic/mem/rom1p1r.sv
@@ -25,8 +25,6 @@
 
 // This model actually works correctly with vivado.
 
-`include "wally-config.vh"
-
 module rom1p1r #(parameter ADDR_WIDTH = 8,
      parameter DATA_WIDTH = 32, 
      parameter PRELOAD_ENABLED = 0)
diff --git a/src/generic/mux.sv b/src/generic/mux.sv
index 223d41afc..9c1dfe335 100644
--- a/src/generic/mux.sv
+++ b/src/generic/mux.sv
@@ -24,7 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 /* verilator lint_off DECLFILENAME */
 
 module mux2 #(parameter WIDTH = 8) (
diff --git a/src/generic/neg.sv b/src/generic/neg.sv
index 787817af8..e971fc232 100644
--- a/src/generic/neg.sv
+++ b/src/generic/neg.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module neg #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] a,
   output logic [WIDTH-1:0] y);
diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv
index 5e8f01c26..b672a08e5 100644
--- a/src/generic/onehotdecoder.sv
+++ b/src/generic/onehotdecoder.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module onehotdecoder #(parameter WIDTH = 2) (
   input  logic [WIDTH-1:0]    bin,
   output logic [2**WIDTH-1:0] decoded
diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv
index a98c79a3d..476b62586 100644
--- a/src/generic/or_rows.sv
+++ b/src/generic/or_rows.sv
@@ -24,8 +24,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 // perform an OR of all the rows in an array, producing one output for each column
 // equivalent to assign y = a.or
 module or_rows #(parameter ROWS = 8, COLS=2) (
diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv
index ba5ebb90f..1cddb2bfc 100644
--- a/src/generic/priorityonehot.sv
+++ b/src/generic/priorityonehot.sv
@@ -33,8 +33,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module priorityonehot #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv
index 059792b7d..f779d4748 100644
--- a/src/generic/prioritythermometer.sv
+++ b/src/generic/prioritythermometer.sv
@@ -29,8 +29,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module prioritythermometer #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index 1114245e9..1906c85e5 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -27,9 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module alu #(parameter WIDTH=32) (
+module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
   input  logic [WIDTH-1:0] A, B,        // Operands
   input  logic             W64,         // W64-type instruction
   input  logic             SubArith,    // Subtraction or arithmetic shift
@@ -57,7 +55,7 @@ module alu #(parameter WIDTH=32) (
   assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // Shifts (configurable for rotation)
-  shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
+  shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
 
   // Condition code flags are based on subtraction output Sum = A-B.
   // Overflow occurs when the numbers being subtracted have the opposite sign 
@@ -77,7 +75,7 @@ module alu #(parameter WIDTH=32) (
       3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT};       // slt
       3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU};      // sltu
       3'b100: FullResult = A ^ CondMaskInvB;              // xor, xnor, binv
-      3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
+      3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
       3'b110: FullResult = A | CondMaskInvB;              // or, orn, bset
       3'b111: FullResult = A & CondMaskInvB;              // and, bclr
     endcase
@@ -88,8 +86,8 @@ module alu #(parameter WIDTH=32) (
   else              assign PreALUResult = FullResult;
 
   // Final Result B instruction select mux
-  if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
-    bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActiveE,
+  if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu
+    bitmanipalu #(P, WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActiveE,
       .Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
       .CondMaskB, .CondShiftA, .ALUResult);
   end else begin
@@ -97,4 +95,4 @@ module alu #(parameter WIDTH=32) (
     assign CondMaskB = B;
     assign CondShiftA = A;
   end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv
index c8757e65a..706ebdb21 100644
--- a/src/ieu/bmu/bitmanipalu.sv
+++ b/src/ieu/bmu/bitmanipalu.sv
@@ -27,9 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module bitmanipalu #(parameter WIDTH=32) (
+module bitmanipalu import cvw::*; #(parameter cvw_t P, 
+                     parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, B,                    // Operands
   input  logic             W64,                     // W64-type instruction
   input  logic [1:0]       BSelect,                 // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
@@ -62,13 +61,13 @@ module bitmanipalu #(parameter WIDTH=32) (
   assign {Mask, PreShift} = BALUControl[1:0];
 
   // Mask Generation Mux
-  if (`ZBS_SUPPORTED) begin: zbsdec
+  if (P.ZBS_SUPPORTED) begin: zbsdec
     decoder #($clog2(WIDTH)) maskgen(BBMU[$clog2(WIDTH)-1:0], MaskB);
     mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB);
   end else assign CondMaskB = B;
  
   // 0-3 bit Pre-Shift Mux
-  if (`ZBA_SUPPORTED) begin: zbapreshift
+  if (P.ZBA_SUPPORTED) begin: zbapreshift
     if (WIDTH == 64) begin
       mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA); 
     end else assign CondZextA = A;
@@ -80,17 +79,17 @@ module bitmanipalu #(parameter WIDTH=32) (
   end
 
   // Bit reverse needed for some ZBB, ZBC instructions
-  if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse
+  if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
     bitreverse #(WIDTH) brA(.A(ABMU), .RevA);
   end
 
   // ZBC Unit
-  if (`ZBC_SUPPORTED) begin: zbc
+  if (P.ZBC_SUPPORTED) begin: zbc
     zbc #(WIDTH) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
   end else assign ZBCResult = 0;
 
   // ZBB Unit
-  if (`ZBB_SUPPORTED) begin: zbb
+  if (P.ZBB_SUPPORTED) begin: zbb
     zbb #(WIDTH) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
   end else assign ZBBResult = 0;
 
diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv
index e2afb0c95..fc2530aab 100644
--- a/src/ieu/bmu/bitreverse.sv
+++ b/src/ieu/bmu/bitreverse.sv
@@ -27,7 +27,6 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
 
 module bitreverse #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A,
diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv
index e6099533b..2879ba042 100644
--- a/src/ieu/bmu/byteop.sv
+++ b/src/ieu/bmu/byteop.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module byteop #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A,             // Operands
   input  logic             ByteSelect,    // LSB of Immediate
@@ -43,4 +41,4 @@ module byteop #(parameter WIDTH=32) (
   end
 
   mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv
index cf3e1c6b1..675387577 100644
--- a/src/ieu/bmu/clmul.sv
+++ b/src/ieu/bmu/clmul.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module clmul #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] X, Y,             // Operands
   output logic [WIDTH-1:0] ClmulResult);     // ZBS result
diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv
index a1f82eb7e..d015c1195 100644
--- a/src/ieu/bmu/cnt.sv
+++ b/src/ieu/bmu/cnt.sv
@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module cnt #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A, RevA,    // Operands
   input  logic [1:0]       B,          // Last 2 bits of immediate
@@ -62,4 +60,4 @@ module cnt #(parameter WIDTH = 32) (
   assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0;
 
   mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv
index 438addaa8..1feca6e1e 100644
--- a/src/ieu/bmu/ext.sv
+++ b/src/ieu/bmu/ext.sv
@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module ext #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A,            // Operands
   input  logic [1:0]       ExtSelect,    // B[2], B[0] of immediate
@@ -42,4 +40,4 @@ module ext #(parameter WIDTH = 32) (
   assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]};
 
   mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv
index 3d7bcedd9..9ae3df42d 100644
--- a/src/ieu/bmu/zbb.sv
+++ b/src/ieu/bmu/zbb.sv
@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module zbb #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, RevA, B,   // Operands
   input  logic             W64,          // Indicates word operation
@@ -55,4 +53,4 @@ module zbb #(parameter WIDTH=32) (
 
   // ZBB Result select mux
   mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv
index b173a5f63..4dc3ad1bd 100644
--- a/src/ieu/bmu/zbc.sv
+++ b/src/ieu/bmu/zbc.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module zbc #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A, RevA, B,       // Operands
   input  logic [2:0]       Funct3,           // Indicates operation to perform
@@ -48,4 +46,4 @@ module zbc #(parameter WIDTH=32) (
   bitreverse  #(WIDTH) brClmulResult(ClmulResult, RevClmulResult);
 
   mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv
index 5f504dced..0803d8b2f 100644
--- a/src/ieu/comparator.sv
+++ b/src/ieu/comparator.sv
@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 // This comparator is best
 module comparator #(parameter WIDTH=64) (
   input  logic [WIDTH-1:0] a, b,    // Operands
diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv
index e48bd2c38..799a25988 100644
--- a/src/ieu/datapath.sv
+++ b/src/ieu/datapath.sv
@@ -113,7 +113,7 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
   mux2  #(P.XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(P.XLEN)  srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
-  alu   #(P.XLEN)  alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, ALUResultE, IEUAdrE);
+  alu   #(P, P.XLEN)  alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, ALUResultE, IEUAdrE);
   mux2  #(P.XLEN)  altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
   mux2  #(P.XLEN)  ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
 
diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv
index d28989243..bb0160c71 100644
--- a/src/ieu/shifter.sv
+++ b/src/ieu/shifter.sv
@@ -27,21 +27,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module shifter (
-  input  logic [`XLEN-1:0]     A,                             // shift Source
-  input  logic [`LOG_XLEN-1:0] Amt,                           // Shift amount
+module shifter import cvw::*; #(parameter cvw_t P) (
+  input  logic [P.XLEN-1:0]     A,                             // shift Source
+  input  logic [P.LOG_XLEN-1:0] Amt,                           // Shift amount
   input  logic                 Right, Rotate, W64, SubArith,  // Shift right, rotate, W64-type operation, arithmetic shift
-  output logic [`XLEN-1:0]     Y);                            // Shifted result
+  output logic [P.XLEN-1:0]     Y);                            // Shifted result
 
-  logic [2*`XLEN-2:0]          Z, ZShift;                     // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
-  logic [`LOG_XLEN-1:0]        TruncAmt, Offset;              // Shift amount adjusted for RV64, right-shift amount
+  logic [2*P.XLEN-2:0]          Z, ZShift;                     // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
+  logic [P.LOG_XLEN-1:0]        TruncAmt, Offset;              // Shift amount adjusted for RV64, right-shift amount
   logic                        Sign;                          // Sign bit for sign extension
 
-  assign Sign = A[`XLEN-1] & SubArith;  // sign bit for sign extension
-  if (`XLEN==32) begin // rv32
-    if (`ZBB_SUPPORTED) begin: rotfunnel32 // rv32 shifter with rotates
+  assign Sign = A[P.XLEN-1] & SubArith;  // sign bit for sign extension
+  if (P.XLEN==32) begin // rv32
+    if (P.ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
       always_comb  // funnel mux
         case({Right, Rotate})
           2'b00: Z = {A[31:0], 31'b0};
@@ -56,12 +54,12 @@ module shifter (
     end
     assign TruncAmt = Amt; // shift amount
   end else begin // rv64
-    logic [`XLEN-1:0]         A64;                            
+    logic [P.XLEN-1:0]         A64;                            
     mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
-    if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
+    if (P.ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
       // shifter rotate source select mux
-      logic [`XLEN-1:0]   RotA;                          // rotate source
-      mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
+      logic [P.XLEN-1:0]   RotA;                          // rotate source
+      mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
       always_comb  // funnel mux
         case ({Right, Rotate})
           2'b00: Z = {A64[63:0],{63'b0}};
@@ -82,5 +80,5 @@ module shifter (
   
   // Funnel operation
   assign ZShift = Z >> Offset;
-  assign Y = ZShift[`XLEN-1:0];    
+  assign Y = ZShift[P.XLEN-1:0];    
 endmodule
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 7493c5ccc..13439cd43 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -97,45 +97,45 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
   
   // Part 1 branch direction prediction
   if (P.BPRED_TYPE == BP_TWOBIT) begin:Predictor
-    twoBitPredictor #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, 
+    twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, 
       .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
 
   end else if (P.BPRED_TYPE == BP_GSHARE) begin:Predictor
-    gshare #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, 
       .PCSrcE);
 
   end else if (P.BPRED_TYPE == BP_GLOBAL) begin:Predictor
-    gshare #(P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW,
       .PCSrcE);
 
   end else if (P.BPRED_TYPE == BP_GSHARE_BASIC) begin:Predictor
-    gsharebasic #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
 
   end else if (P.BPRED_TYPE == BP_GLOBAL_BASIC) begin:Predictor
-    gsharebasic #(P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   
   end else if (P.BPRED_TYPE == BP_LOCAL_BASIC) begin:Predictor
-    localbpbasic #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
+    localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end else if (P.BPRED_TYPE == BP_LOCAL_AHEAD) begin:Predictor
-    localaheadbp #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
+    localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end else if (P.BPRED_TYPE == BP_LOCAL_REPAIR) begin:Predictor
-    localrepairbp #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
+    localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
       .BranchD, .BranchE, .BranchM, .PCSrcE);
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 5279f867a..e93c1decb 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -92,7 +92,7 @@ module btb import cvw::*;  #(parameter cvw_t P,
 
 
   // An optimization may be using a PC relative address.
-  ram2p1r1wbe #(2**Depth, P.XLEN+4) memory(
+  ram2p1r1wbe #(P, 2**Depth, P.XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
      .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
 
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index dcd94e2a2..460acbcbf 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -28,7 +28,8 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 
-module gshare #(parameter XLEN, 
+module gshare import cvw::*; #(parameter cvw_t P,
+                               parameter XLEN, 
                 parameter k = 10,
                 parameter integer TYPE = 1) (
   input logic             clk,
@@ -83,7 +84,7 @@ module gshare #(parameter XLEN,
   
   assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF;
 
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(TableBPDirPredF),
diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv
index 165915ce2..2914c3e3f 100644
--- a/src/ifu/bpred/gsharebasic.sv
+++ b/src/ifu/bpred/gsharebasic.sv
@@ -27,7 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module gsharebasic #(parameter XLEN,
+module gsharebasic import cvw::*; #(parameter cvw_t P,
+                     parameter XLEN,
                      parameter k = 10,
                      parameter TYPE = 1) (
   input logic             clk,
@@ -57,7 +58,7 @@ module gsharebasic #(parameter XLEN,
   assign IndexM = GHRM;
   end
   
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(BPDirPredF),
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
index 6fdf7c3f5..266219416 100644
--- a/src/ifu/bpred/localaheadbp.sv
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -25,7 +25,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module localaheadbp #(parameter XLEN,
+module localaheadbp import cvw::*; #(parameter cvw_t P, 
+                                     parameter XLEN,
                       parameter m = 6, // 2^m = number of local history branches 
                       parameter k = 10) ( // number of past branches stored
   input logic             clk,
@@ -58,7 +59,7 @@ module localaheadbp #(parameter XLEN,
   //assign IndexNextF = LHR;
   assign IndexM = LHRW;
   
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallD), .ce2(~StallW & ~FlushW),
     .ra1(LHRF),
     .rd1(BPDirPredD),
@@ -91,7 +92,7 @@ module localaheadbp #(parameter XLEN,
   assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
   assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
 
-  ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexLHRNextF),
     .rd1(LHRF),
diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv
index 827b756e6..8037b743d 100644
--- a/src/ifu/bpred/localbpbasic.sv
+++ b/src/ifu/bpred/localbpbasic.sv
@@ -26,7 +26,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module localbpbasic #(parameter XLEN,
+module localbpbasic import cvw::*; #(parameter cvw_t P,
+                                     parameter XLEN,
                       parameter m = 6, // 2^m = number of local history branches 
                       parameter k = 10) ( // number of past branches stored
   input logic             clk,
@@ -55,7 +56,7 @@ module localbpbasic #(parameter XLEN,
   assign IndexNextF = LHR;
   assign IndexM = LHRM;
   
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(BPDirPredF),
diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv
index f7be7e71e..3af6d7b9f 100644
--- a/src/ifu/bpred/localrepairbp.sv
+++ b/src/ifu/bpred/localrepairbp.sv
@@ -25,7 +25,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module localrepairbp #(parameter XLEN,
+module localrepairbp import cvw::*; #(parameter cvw_t P,
+                                      parameter XLEN,
                        parameter m = 6, // 2^m = number of local history branches 
                        parameter k = 10) ( // number of past branches stored
   input logic             clk,
@@ -57,7 +58,7 @@ module localrepairbp #(parameter XLEN,
   logic                   SpeculativeFlushedF;
   
   
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallD), .ce2(~StallW & ~FlushW),
     .ra1(LHRF),
     .rd1(BPDirPredD),
@@ -88,7 +89,7 @@ module localrepairbp #(parameter XLEN,
   assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
   assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
 
-  ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexLHRNextF),
     .rd1(LHRCommittedF),
@@ -100,7 +101,7 @@ module localrepairbp #(parameter XLEN,
   assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]};
   assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE;
   // *** replace with a small CAM
-  ram2p1r1wbe #(2**m, k) SHB(.clk(clk),
+  ram2p1r1wbe #(P, 2**m, k) SHB(.clk(clk),
     .ce1(~StallF), .ce2(~StallE & ~FlushE),
     .ra1(IndexLHRNextF),
     .rd1(LHRSpeculativeF),
diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv
index 7cb3f4173..52e24d901 100644
--- a/src/ifu/bpred/twoBitPredictor.sv
+++ b/src/ifu/bpred/twoBitPredictor.sv
@@ -26,7 +26,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module twoBitPredictor #(parameter XLEN,
+module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN,
                          parameter k = 10) (
   input  logic             clk,
   input  logic             reset,
@@ -53,7 +53,7 @@ module twoBitPredictor #(parameter XLEN,
   assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};  
 
 
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+  ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
     .rd1(BPDirPredF),
diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv
index 5ce5ab683..1605ed039 100644
--- a/src/ifu/decompress.sv
+++ b/src/ifu/decompress.sv
@@ -29,7 +29,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 
 module decompress #(parameter XLEN)(
   input  logic [31:0] InstrRawD,         // 32-bit instruction or raw compressed 16-bit instruction in bottom half
@@ -91,18 +90,18 @@ module decompress #(parameter XLEN)(
                   end
         5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
         5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
-        5'b00011: if (`XLEN==32)
+        5'b00011: if (XLEN==32)
                     InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
                   else
                     InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
         5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
         5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
-        5'b00111: if (`XLEN==32)
+        5'b00111: if (XLEN==32)
                     InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
                   else
                     InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
         5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
-        5'b01001: if (`XLEN==32) 
+        5'b01001: if (XLEN==32) 
                     InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
                   else
                     InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
@@ -126,7 +125,7 @@ module decompress #(parameter XLEN)(
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
                     else // if (instr16[6:5] == 2'b11) 
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
-                  else if (`XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] 
+                  else if (XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10] 
                     if (instr16[6:5] == 2'b00)
                       InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
                     else if (instr16[6:5] == 2'b01)
@@ -151,7 +150,7 @@ module decompress #(parameter XLEN)(
         5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
         5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
         5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
-        5'b10011: if (`XLEN == 32)
+        5'b10011: if (XLEN == 32)
                     InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
                   else 
                     InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
@@ -170,7 +169,7 @@ module decompress #(parameter XLEN)(
                       InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
         5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
         5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
-        5'b10111: if (`XLEN==32)
+        5'b10111: if (XLEN==32)
                     InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
                   else
                     InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index e47115ed1..de0200058 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -232,7 +232,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
       
       assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
       assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
-      cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
               .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
               .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
       icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
index d499b1db3..bb018406a 100644
--- a/src/ifu/spill.sv
+++ b/src/ifu/spill.sv
@@ -29,8 +29,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module spill import cvw::*;  #(parameter cvw_t P) (
   input logic               clk,               
   input logic               reset,
diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv
index 896a047c2..c8668e767 100644
--- a/src/lsu/dtim.sv
+++ b/src/lsu/dtim.sv
@@ -49,6 +49,6 @@ module dtim import cvw::*;  #(parameter cvw_t P) (
 
   assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
 
-  ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN)) 
+  ram1p1rwbe #(.P(P), .DEPTH(DEPTH), .WIDTH(P.LLEN)) 
     ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 5a4358605..9c0d00543 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -260,7 +260,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0;
     assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW);
       
-      cache #(.PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
         .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
         .FlushCache(FlushDCache), .NextSet(IEUAdrE[11:0]), .PAdr(PAdrM), 
diff --git a/src/mdu/div.sv b/src/mdu/div.sv
index a6eb0a686..c550c06fc 100644
--- a/src/mdu/div.sv
+++ b/src/mdu/div.sv
@@ -105,7 +105,7 @@ module div import cvw::*;  #(parameter cvw_t P) (
   // one copy of divstep for each bit produced per cycle
   genvar i;
   for (i=0; i<P.IDIV_BITSPERCYCLE; i = i+1)
-    divstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
+    divstep #(P.XLEN) divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
 
   //////////////////////////////
   // Memory Stage: output sign correction and special cases
diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv
index cb06efda2..712e98866 100644
--- a/src/mdu/divstep.sv
+++ b/src/mdu/divstep.sv
@@ -26,26 +26,24 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 /* verilator lint_off UNOPTFLAT */
 
-module divstep(
-  input  logic [`XLEN-1:0] W,     // Residual in
-  input  logic [`XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
-  input  logic [`XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
-  output logic [`XLEN-1:0] WOut,  // Residual out
-  output logic [`XLEN-1:0] XQOut  // bits of dividend and quotient out: discard one bit of X, append one bit of Q
+module divstep #(parameter XLEN) (
+  input  logic [XLEN-1:0] W,     // Residual in
+  input  logic [XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
+  input  logic [XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
+  output logic [XLEN-1:0] WOut,  // Residual out
+  output logic [XLEN-1:0] XQOut  // bits of dividend and quotient out: discard one bit of X, append one bit of Q
 );
 
-  logic [`XLEN-1:0] WShift;       // Shift W left by one bit, bringing in most significant bit of X
-  logic [`XLEN-1:0] WPrime;       // WShift - D, for comparison and possible result
+  logic [XLEN-1:0] WShift;       // Shift W left by one bit, bringing in most significant bit of X
+  logic [XLEN-1:0] WPrime;       // WShift - D, for comparison and possible result
   logic qi, qib;                  // Quotient digit and its complement
   
-  assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};  // shift W and X/Q left, insert quotient bit at bottom
-  adder #(`XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
+  assign {WShift, XQOut} = {W[XLEN-2:0], XQ, qi};  // shift W and X/Q left, insert quotient bit at bottom
+  adder #(XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
   assign qi = ~qib;
-  mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
+  mux2 #(XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
 endmodule
 
 /* verilator lint_on UNOPTFLAT */
diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv
index 10ca759a0..a089031c2 100644
--- a/src/mmu/tlb/vm64check.sv
+++ b/src/mmu/tlb/vm64check.sv
@@ -26,8 +26,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module vm64check import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.SVMODE_BITS-1:0] SATP_MODE,
   input  logic [P.XLEN-1:0]        VAdr,
diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv
index e6857d042..78de50aa1 100644
--- a/src/uncore/ram_ahb.sv
+++ b/src/uncore/ram_ahb.sv
@@ -71,7 +71,7 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
   mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
 
   // single-ported RAM
-  ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1), 
+  ram1p1rwbe #(.P(P), .DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1), 
     .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
   
   // use this to add arbitrary latency to ram. Helps test AHB controller correctness
diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv
index 46f20386d..ad1e0f259 100644
--- a/src/uncore/uartPC16550D.sv
+++ b/src/uncore/uartPC16550D.sv
@@ -138,7 +138,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
     if (~PRESETn) begin // Table 3 Reset Configuration
       IER <= #1 4'b0;
       FCR <= #1 8'b0;
-      LCR <= #1 8'b11; // spec says to reset to 0, but FPGA needs to reset to 8 data bits
+      LCR <= #1 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed.
       MCR <= #1 5'b0;
       LSR <= #1 8'b01100000;
       MSR <= #1 4'b0;
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index a01bba009..39f780a60 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -26,7 +26,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module wallypipelinedcore import cvw::*;  #(parameter cvw_t P) (
+module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
    input  logic                  clk, reset,
    // Privileged
    input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
index af8c18ed1..014b93687 100644
--- a/src/wally/wallypipelinedsoc.sv
+++ b/src/wally/wallypipelinedsoc.sv
@@ -26,22 +26,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "config.vh"
-//import cvw::*;  // global CORE-V-Wally parameters
-
-module wallypipelinedsoc import cvw::*;  (
+module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   input  logic                clk, 
   input  logic                reset_ext,        // external asynchronous reset pin
   output logic                reset,            // reset synchronized to clk to prevent races on release
   // AHB Interface
-  input  logic [AHBW-1:0]     HRDATAEXT,
+  input  logic [P.AHBW-1:0]     HRDATAEXT,
   input  logic                HREADYEXT, HRESPEXT,
   output logic                HSELEXT,
   // outputs to external memory, shared with uncore memory
   output logic                HCLK, HRESETn,
-  output logic [PA_BITS-1:0]  HADDR,
-  output logic [AHBW-1:0]     HWDATA,
-  output logic [XLEN/8-1:0]   HWSTRB,
+  output logic [P.PA_BITS-1:0]  HADDR,
+  output logic [P.AHBW-1:0]     HWDATA,
+  output logic [P.XLEN/8-1:0]   HWSTRB,
   output logic                HWRITE,
   output logic [2:0]          HSIZE,
   output logic [2:0]          HBURST,
@@ -64,14 +61,12 @@ module wallypipelinedsoc import cvw::*;  (
 );
 
   // Uncore signals
-  logic [AHBW-1:0]            HRDATA;           // from AHB mux in uncore
+  logic [P.AHBW-1:0]            HRDATA;           // from AHB mux in uncore
   logic                       HRESP;            // response from AHB
   logic                       MTimerInt, MSwInt;// timer and software interrupts from CLINT
   logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
   logic                       MExtInt,SExtInt;  // from PLIC
 
-  `include "parameter-defs.vh"
-
   // synchronize reset to SOC clock domain
   synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
    
@@ -83,7 +78,7 @@ module wallypipelinedsoc import cvw::*;  (
    );
 
   // instantiate uncore if a bus interface exists
-  if (BUS_SUPPORTED) begin : uncore
+  if (P.BUS_SUPPORTED) begin : uncore
     uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
       .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
diff --git a/testbench/common/checksignature.sv b/testbench/common/checksignature.sv
new file mode 100644
index 000000000..7fb589bb6
--- /dev/null
+++ b/testbench/common/checksignature.sv
@@ -0,0 +1,26 @@
+///////////////////////////////////////////
+// checksignature.sv
+//
+// Written: David Harris David_Harris@hmc.edu
+// Modified: 14 June 2023
+//
+// Purpose: Verifies the memory signature.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv
index c986c2e51..90157f255 100644
--- a/testbench/common/functionName.sv
+++ b/testbench/common/functionName.sv
@@ -1,6 +1,8 @@
 ///////////////////////////////////////////
 // functionName.sv
 //
+// Written: Ross Thompson ross1728@gmail.com
+// 
 // Purpose: decode name of function
 // 
 // A component of the Wally configurable RISC-V project.
@@ -21,21 +23,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
+module FunctionName import cvw::*; #(parameter cvw_t P) (
+  input logic reset,
+  input logic clk,
+  input string ProgramAddrMapFile,
+  input string ProgramLabelMapFile
+  );
   
-  input logic reset;
-  input logic clk;
-  input string ProgramAddrMapFile;
-  input string ProgramLabelMapFile;
-
-  logic [`XLEN-1:0] ProgramAddrMapMemory [];
+  logic [P.XLEN-1:0] ProgramAddrMapMemory [];
   string 	    ProgramLabelMapMemory [integer];
   string 	    FunctionName;
   
 
-  logic [`XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld;
+  logic [P.XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld;
   logic 	    StallD, StallE, StallM, FlushD, FlushE, FlushM;
   logic 		InstrValidM;
   integer 	    ProgramAddrIndex, ProgramAddrIndexQ;
@@ -53,21 +53,20 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
   // when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not
   // erroneously change.
   // also need to hold the old value not an erroneously fetched PC.
-  flopenr #(`XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD);
-  flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE);
-  flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp);
-  flopenr #(`XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld);
+  flopenr #(P.XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD);
+  flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE);
+  flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp);
+  flopenr #(P.XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld);
   assign PCM = InstrValidM ? PCM_temp : PCMOld;
-  
 
   task automatic bin_search_min;
-    input logic [`XLEN-1:0] pc;
-    input logic [`XLEN-1:0] length;
-    ref logic [`XLEN-1:0]   array [];
-    output logic [`XLEN-1:0] minval;
-    output     logic [`XLEN-1:0] mid;
+    input logic [P.XLEN-1:0] pc;
+    input logic [P.XLEN-1:0] length;
+    ref logic [P.XLEN-1:0]   array [];
+    output logic [P.XLEN-1:0] minval;
+    output     logic [P.XLEN-1:0] mid;
 
-    logic [`XLEN-1:0] 	     left, right;
+    logic [P.XLEN-1:0] 	     left, right;
 
     begin
       if ( pc == 0 ) begin
@@ -171,7 +170,6 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
   initial ProgramAddrIndex = '0;
 
   assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
-  
 
 endmodule // function_radix
 
diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
index 6834e1b17..1529de5e6 100644
--- a/testbench/common/instrNameDecTB.sv
+++ b/testbench/common/instrNameDecTB.sv
@@ -305,7 +305,10 @@ module instrNameDecTB(
                        else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
                        else if (funct7[6:2] == 5'b10100) name = "FEQ";
                        else                              name = "ILLEGAL";
+      /* verilator lint_off CASEOVERLAP */
+      // *** RT: definitely take a look at this.  This overlaps with 10'b1010011_000
       10'b1010011_???: if      (funct7[6:2] == 5'b00000) name = "FADD";
+      /* verilator lint_on CASEOVERLAP */
                        else if (funct7[6:2] == 5'b00001) name = "FSUB";
                        else if (funct7[6:2] == 5'b00010) name = "FMUL";
                        else if (funct7[6:2] == 5'b00011) name = "FDIV";
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
new file mode 100644
index 000000000..cf42fe4ec
--- /dev/null
+++ b/testbench/common/loggers.sv
@@ -0,0 +1,234 @@
+///////////////////////////////////////////
+// loggers.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Modified: 14 June 2023
+// 
+// Purpose: Log branch instructions, log instruction fetches,
+//          log I$ misses, log data memory accesses, log D$ misses, and
+//          log other related operations
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module loggers import cvw::*; #(parameter cvw_t P,
+                                parameter TEST,
+                                parameter PrintHPMCounters,
+                                parameter I_CACHE_ADDR_LOGGER,
+                                parameter D_CACHE_ADDR_LOGGER,
+                                parameter BPRED_LOGGER) (
+  input logic  clk,
+  input logic  reset,
+  input logic  DCacheFlushStart,
+  input logic  DCacheFlushDone,                                                         
+//  input logic BeginSample,
+//  input logic StartSample,
+//  input logic EndSample,
+  input string memfilename
+  );
+  
+  // performance counter logging 
+  logic        BeginSample;
+  logic StartSample, EndSample;
+  if(PrintHPMCounters & P.ZICNTR_SUPPORTED) begin : HPMCSample
+    integer           HPMCindex;
+    logic             StartSampleFirst;
+    logic             StartSampleDelayed, BeginDelayed;
+    logic             EndSampleFirst, EndSampleDelayed;
+    logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
+
+    string  HPMCnames[] = '{"Mcycle",
+                            "------",
+                            "InstRet",
+                            "Br Count",
+                            "Jump Not Return",
+                            "Return",
+                            "BP Wrong",
+                            "BP Dir Wrong",
+                            "BP Target Wrong",
+                            "RAS Wrong",
+                            "Instr Class Wrong",
+                            "Load Stall",
+                            "Store Stall",
+                            "D Cache Access",
+                            "D Cache Miss",
+                            "D Cache Cycles",
+                            "I Cache Access",
+                            "I Cache Miss",
+                            "I Cache Cycles",
+                            "CSR Write",
+                            "FenceI",
+                            "SFenceVMA",
+                            "Interrupt",
+                            "Exception",
+                            "Divide Cycles"
+                          };
+
+    if(TEST == "embench") begin
+      // embench runs warmup then runs start_trigger
+      // embench end with stop_trigger.
+      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+
+      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
+      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+
+    end else if(TEST == "coremark") begin
+      // embench runs warmup then runs start_trigger
+	    // embench end with stop_trigger.
+      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+
+      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
+      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+
+    end else begin
+      // default start condiction is reset
+      // default end condiction is end of test (DCacheFlushDone)
+      assign StartSampleFirst = reset;
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+      assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
+
+      flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
+      assign BeginSample = StartSampleFirst & ~BeginDelayed;
+
+    end
+    always @(negedge clk) begin
+      if(StartSample) begin
+        for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
+          InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
+        end
+      end
+      if(EndSample) begin
+        for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
+          // unlikely to have more than 10M in any counter.
+          $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
+        end
+      end
+    end
+  end
+
+  if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger
+    int    file;
+    string LogFile;
+    logic  resetD, resetEdge;
+    logic  Enable;
+    logic  InvalDelayed, InvalEdge;
+    
+    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
+                    dut.core.ifu.immu.immu.pmachecker.Cacheable &
+                    ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
+                    ~reset;
+    flop #(1) ResetDReg(clk, reset, resetD);
+    assign resetEdge = ~reset & resetD;
+
+    flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
+    assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
+
+    initial begin
+      LogFile = "ICache.log";
+      file = $fopen(LogFile, "w");
+      $fwrite(file, "BEGIN %s\n", memfilename);
+    end
+    string AccessTypeString, HitMissString;
+    assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
+                           dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
+    always @(posedge clk) begin
+    if(resetEdge) $fwrite(file, "TRAIN\n");
+    if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
+    if(Enable) begin  // only log i cache reads
+      $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
+    end
+    if(InvalEdge) $fwrite(file, "0 I X\n");
+    if(EndSample) $fwrite(file, "END %s\n", memfilename);
+    end
+  end
+
+
+  if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger
+    int    file;
+    string LogFile;
+    logic  resetD, resetEdge;
+    logic  Enabled;
+    string AccessTypeString, HitMissString;
+
+    flop #(1) ResetDReg(clk, reset, resetD);
+    assign resetEdge = ~reset & resetD;
+    assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
+                           (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
+                           dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
+    assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
+                              dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
+                              dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
+                              dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
+                              "NULL";
+    
+    assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
+                     ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
+                     dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
+                     (AccessTypeString != "NULL");
+
+    initial begin
+      LogFile = "DCache.log";
+      file = $fopen(LogFile, "w");
+      $fwrite(file, "BEGIN %s\n", memfilename);
+    end
+    always @(posedge clk) begin
+      if(resetEdge) $fwrite(file, "TRAIN\n");
+      if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
+      if(Enabled) begin
+        $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
+      end
+      if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
+      if(EndSample) $fwrite(file, "END %s\n", memfilename);
+    end
+  end
+
+  if (P.BPRED_SUPPORTED) begin : BranchLogger
+    if (BPRED_LOGGER) begin
+      string direction;
+      int    file;
+      logic  PCSrcM;
+      string LogFile;
+      logic  resetD, resetEdge;
+      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
+      flop #(1) ResetDReg(clk, reset, resetD);
+      assign resetEdge = ~reset & resetD;
+      initial begin
+        LogFile = "branch.log"; // will break some of Ross's research analysis scripts
+        //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
+        file = $fopen(LogFile, "w");
+      end
+      always @(posedge clk) begin
+        if(resetEdge) $fwrite(file, "TRAIN\n");
+        if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
+        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+          direction = PCSrcM ? "t" : "n";
+          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
+        end
+        if(EndSample) $fwrite(file, "END %s\n", memfilename);
+      end
+    end
+  end
+
+endmodule
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index b3bc8f96f..24a7e223c 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -19,45 +19,43 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
-module riscvassertions;
+module riscvassertions import cvw::*; #(parameter cvw_t P);
   initial begin
-    assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
-    assert (`S_SUPPORTED || `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
-    assert (`IDIV_BITSPERCYCLE == 1 || `IDIV_BITSPERCYCLE==2 || `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
-    assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
-    assert (`D_SUPPORTED || ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
-    assert (`F_SUPPORTED || ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
-    assert (`DCACHE_SUPPORTED || ~`F_SUPPORTED || `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
-    assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
-    assert (`FLEN<=`XLEN || `DCACHE_SUPPORTED || `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
-    assert (`DCACHE_WAYSIZEINBYTES <= 4096 || (!`DCACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`DCACHE_LINELENINBITS >= 128 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
-    assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
-    assert (`ICACHE_WAYSIZEINBYTES <= 4096 || (!`ICACHE_SUPPORTED) || `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (`ICACHE_LINELENINBITS >= 32 || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
-    assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
-    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES || (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS || (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES || (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
-    assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES || `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
-    assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
-	  assert (`ZICSR_SUPPORTED == 1 || (`PMP_ENTRIES == 0 && `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
-    assert (`ZICSR_SUPPORTED == 1 || (`S_SUPPORTED == 0 && `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
-    assert (`U_SUPPORTED || (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
-    assert (`VIRTMEM_SUPPORTED == 0 || (`DTIM_SUPPORTED == 0 && `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
-    assert (`DCACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
-    assert (`ICACHE_SUPPORTED || `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    assert ((`DCACHE_SUPPORTED == 0 && `ICACHE_SUPPORTED == 0) || `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
-    assert (`DCACHE_LINELENINBITS <= `XLEN*16 || (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
-    assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
-    assert (`DCACHE_SUPPORTED || (`A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally.");
-    assert (`IDIV_ON_FPU == 0 || `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
-    assert (`SSTC_SUPPORTED == 0 || (`S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
-    assert ((`ZMMUL_SUPPORTED == 0) || (`M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
+    assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
+    assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
+    assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
+    assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
+    assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
+    assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
+    assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
+    assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $error("Exactly one of I and E must be supported");
+    assert (P.FLEN<=P.XLEN || P.DCACHE_SUPPORTED || P.DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
+    assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
+    assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
+    assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
+    assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
+    assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
+    assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
+    assert (P.UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
+	  assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
+    assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported");
+    assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
+    assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
+    assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
+    assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
+    assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
+    assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
+    assert (P.DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
+    assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $error("Atomic extension (A) requires cache on Wally.");
+    assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
+    assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
+    assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
   end
 
 endmodule
diff --git a/testbench/common/shadowmem.sv b/testbench/common/shadowmem.sv
new file mode 100644
index 000000000..021d4b82f
--- /dev/null
+++ b/testbench/common/shadowmem.sv
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// shadowmem.sv
+//
+// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com
+// Modified: 14 June 2023
+//
+// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty
+//          line before the end of test.  Signature based regression tests need to check the L1 data cache
+//          in addition to the main memory.  These modules create a shadow memory with a projection of the
+//          D$ contents.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) 
+  (input logic clk,
+   input logic reset,
+   input logic start,
+   output logic done);
+
+  genvar adr;
+
+  logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)];
+  logic         startD;
+  
+  if(P.DCACHE_SUPPORTED) begin
+    localparam numlines       = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+    localparam numways        = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+    localparam linebytelen    = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+    localparam linelen        = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
+    localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
+    localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+    localparam numwords       = sramlen/P.XLEN;
+    localparam lognumlines    = $clog2(numlines);
+    localparam loglinebytelen = $clog2(linebytelen);
+    localparam lognumways     = $clog2(numways);
+    localparam tagstart       = lognumlines + loglinebytelen;
+    
+    genvar               index, way, cacheWord;
+    logic [sramlen-1:0]  CacheData  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic [sramlen-1:0]  cacheline;
+    logic [P.XLEN-1:0]    CacheTag   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic                CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic                CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic [P.PA_BITS-1:0] CacheAdr   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    for(index = 0; index < numlines; index++) begin
+      for(way = 0; way < numways; way++) begin
+        for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
+          copyShadow #(.P(P), .tagstart(tagstart),
+          .loglinebytelen(loglinebytelen), .sramlen(sramlen))
+          copyShadow(.clk,
+          .start,
+          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]),
+          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
+          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
+                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]),
+          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
+          .index(index),
+          .cacheWord(cacheWord),
+          .CacheData(CacheData[way][index][cacheWord]),
+          .CacheAdr(CacheAdr[way][index][cacheWord]),
+          .CacheTag(CacheTag[way][index][cacheWord]),
+          .CacheValid(CacheValid[way][index][cacheWord]),
+          .CacheDirty(CacheDirty[way][index][cacheWord]));
+        end
+      end
+    end
+
+    integer i, j, k, l;
+
+    always @(posedge clk) begin
+      if (startD) begin 
+        for(i = 0; i < numlines; i++) begin
+          for(j = 0; j < numways; j++) begin
+            for(l = 0; l < cachesramwords; l++) begin
+              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
+                for(k = 0; k < numwords; k++) begin
+                  //cacheline = CacheData[j][i][0];
+                  // does not work with modelsim
+                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
+                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
+                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k];
+                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + k] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
+                end
+              end
+            end
+          end
+        end
+      end
+    end  
+  end
+  flop #(1) doneReg1(.clk, .d(start), .q(startD));
+  flop #(1) doneReg2(.clk, .d(startD), .q(done));
+endmodule
+
+module copyShadow import cvw::*; #(parameter cvw_t P,
+  parameter tagstart, loglinebytelen, sramlen)
+  (input  logic                       clk,
+   input  logic                       start,
+   input  logic [P.PA_BITS-1:tagstart] tag,
+   input  logic                       valid, dirty,
+   input  logic [sramlen-1:0]         data,
+   input  logic [32-1:0]              index,
+   input  logic [32-1:0]              cacheWord,
+   output logic [sramlen-1:0]         CacheData,
+   output logic [P.PA_BITS-1:0]        CacheAdr,
+   output logic [P.XLEN-1:0]           CacheTag,
+   output logic                       CacheValid,
+   output logic                       CacheDirty);
+  
+
+  always_ff @(posedge clk) begin
+    if(start) begin
+      CacheTag = tag;
+      CacheValid = valid;
+      CacheDirty = dirty;
+      CacheData = data;
+      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
+    end
+  end
+  
+endmodule
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 8801f5119..a1dc318ec 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -19,7 +19,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
 
 `define NUM_REGS 32
 `define NUM_CSRS 4096
@@ -29,9 +28,10 @@
 `define PRINT_ALL 0
 `define PRINT_CSRS 0
 
-module wallyTracer(rvviTrace rvvi);
 
-  localparam NUMREGS = `E_SUPPORTED ? 16 : 32;
+module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
+
+  localparam NUMREGS = P.E_SUPPORTED ? 16 : 32;
   
   // wally specific signals
   logic 						 reset;
@@ -39,8 +39,8 @@ module wallyTracer(rvviTrace rvvi);
   logic                          InstrValidD, InstrValidE;
   logic                          StallF, StallD;
   logic                          STATUS_SXL, STATUS_UXL;
-  logic [`XLEN-1:0] 			 PCNextF, PCF, PCD, PCE, PCM, PCW;
-  logic [`XLEN-1:0] 			 InstrRawD, InstrRawE, InstrRawM, InstrRawW;
+  logic [P.XLEN-1:0] 			 PCNextF, PCF, PCD, PCE, PCM, PCW;
+  logic [P.XLEN-1:0] 			 InstrRawD, InstrRawE, InstrRawM, InstrRawW;
   logic 						 InstrValidM, InstrValidW;
   logic 						 StallE, StallM, StallW;
   logic 						 FlushD, FlushE, FlushM, FlushW;
@@ -48,16 +48,16 @@ module wallyTracer(rvviTrace rvvi);
   logic 						 IntrF, IntrD, IntrE, IntrM, IntrW;
   logic 						 HaltM, HaltW;
   logic [1:0] 					 PrivilegeModeW;
-  logic [`XLEN-1:0] 			 rf[NUMREGS];
+  logic [P.XLEN-1:0] 			 rf[NUMREGS];
   logic [NUMREGS-1:0] 			 rf_wb;
   logic [4:0] 					 rf_a3;
   logic 						 rf_we3;
-  logic [`XLEN-1:0] 			 frf[32];
+  logic [P.XLEN-1:0] 			 frf[32];
   logic [`NUM_REGS-1:0] 		 frf_wb;
   logic [4:0] 					 frf_a4;
   logic 						 frf_we4;
-  logic [`XLEN-1:0]              CSRArray [logic[11:0]];
-  logic [`XLEN-1:0] 			 CSRArrayOld [logic[11:0]];
+  logic [P.XLEN-1:0]              CSRArray [logic[11:0]];
+  logic [P.XLEN-1:0] 			 CSRArrayOld [logic[11:0]];
   logic [`NUM_CSRS-1:0] 		 CSR_W;
   logic 						 CSRWriteM, CSRWriteW;
   logic [11:0] 					 CSRAdrM, CSRAdrW;
@@ -102,8 +102,8 @@ module wallyTracer(rvviTrace rvvi);
 	
       // PMPCFG  space is 0-15 3a0 - 3af
 	  int i, i4, i8, csrid;
-      logic [`XLEN-1:0] pmp;
-      for (i=0; i<`PMP_ENTRIES; i+=8) begin
+      logic [P.XLEN-1:0] pmp;
+      for (i=0; i<P.PMP_ENTRIES; i+=8) begin
         i4 = i / 4;
         i8 = (i / 8) * 8;
         pmp = 0;
@@ -121,7 +121,7 @@ module wallyTracer(rvviTrace rvvi);
       end
 
       // PMPADDR space is 0-63 3b0 - 3ef
-      for (i=0; i<`PMP_ENTRIES; i++) begin
+      for (i=0; i<P.PMP_ENTRIES; i++) begin
         pmp = testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[i];
         
         csrid = 12'h3B0 + i;
@@ -146,7 +146,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
 	  CSRArray[12'hF11] = 0;
 	  CSRArray[12'hF12] = 0;
-	  CSRArray[12'hF13] = `XLEN'h100;
+	  CSRArray[12'hF13] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100;
 	  CSRArray[12'hF15] = 0;
 	  CSRArray[12'h34A] = 0;
 	  // MCYCLE and MINSTRET
@@ -254,10 +254,10 @@ module wallyTracer(rvviTrace rvvi);
   assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
   
   // pipeline to writeback stage
-  flopenrc #(`XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
-  flopenrc #(`XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(`XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
-  flopenrc #(`XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
+  flopenrc #(P.XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
+  flopenrc #(P.XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
+  flopenrc #(P.XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
+  flopenrc #(P.XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
   flopenrc #(1)     InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
   flopenrc #(1)     TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
   flopenrc #(1)     HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv
new file mode 100644
index 000000000..51ed8c30f
--- /dev/null
+++ b/testbench/common/watchdog.sv
@@ -0,0 +1,52 @@
+///////////////////////////////////////////
+// watchdog.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Modified: 14 June 2023
+//
+// Purpose: Detects if the processor is stuck and halts the simulation
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module watchdog #(parameter XLEN, WatchDogTimerThreshold) 
+  (input clk,
+   input reset
+   );
+  
+  // check for hang up.
+  logic [XLEN-1:0]    PCW;
+  flopenr #(XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  logic [XLEN-1:0]    OldPCW;
+  integer               WatchDogTimerCount;
+  logic                 WatchDogTimeOut;
+  always_ff @(posedge clk) begin
+    OldPCW <= PCW;
+    if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
+    else WatchDogTimerCount = '0;
+  end
+
+  always_comb begin
+    WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
+    if(WatchDogTimeOut) begin
+      $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
+      $stop;
+	end
+  end
+
+endmodule
diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv
index 908660ffe..5c83aca29 100644
--- a/testbench/testbench-linux.sv
+++ b/testbench/testbench-linux.sv
@@ -24,7 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+`include "config.vh"
+import cvw::*;
 
 `define DEBUG_TRACE 0
 // Debug Levels
@@ -47,12 +48,7 @@ module testbench;
   parameter NO_SPOOFING = 0;
 
 
-
-
-
-
-
-
+`include "parameter-defs.vh"
 
 
   ////////////////////////////////////////////////////////////////////////////////////
@@ -85,40 +81,40 @@ module testbench;
       integer TokenIndex``STAGE; \
       integer MarkerIndex``STAGE; \
       integer NumCSR``STAGE; \
-      logic [`XLEN-1:0] ExpectedPC``STAGE; \
+      logic [P.XLEN-1:0] ExpectedPC``STAGE; \
       logic [31:0]      ExpectedInstr``STAGE; \
       string            text``STAGE; \
       string            MemOp``STAGE; \
       string            RegWrite``STAGE; \
       integer           ExpectedRegAdr``STAGE; \
-      logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
-      logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
+      logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \
+      logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
       string            ExpectedCSRArray``STAGE[10:0]; \
-      logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
+      logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
   `DECLARE_TRACE_SCANNER_SIGNALS(E)
   `DECLARE_TRACE_SCANNER_SIGNALS(M)
   //  M-stage expected values
   logic             checkInstrM;
   integer           MIPexpected, SIPexpected;
   string            name;
-  logic [`AHBW-1:0] readDataExpected;
+  logic [P.AHBW-1:0] readDataExpected;
   // W-stage expected values
   logic             checkInstrW;
-  logic [`XLEN-1:0] ExpectedPCW;
+  logic [P.XLEN-1:0] ExpectedPCW;
   logic [31:0]      ExpectedInstrW;
   string            textW;
   string            RegWriteW;
   integer           ExpectedRegAdrW;
-  logic [`XLEN-1:0] ExpectedRegValueW;
+  logic [P.XLEN-1:0] ExpectedRegValueW;
   string            MemOpW;
-  logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
+  logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
   integer           NumCSRW;
   string            ExpectedCSRArrayW[10:0];
-  logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
-  logic [`XLEN-1:0] ExpectedIntType;
+  logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0];
+  logic [P.XLEN-1:0] ExpectedIntType;
   integer           NumCSRWIndex;
   integer           NumCSRPostWIndex;
-  logic [`XLEN-1:0] InstrCountW;
+  logic [P.XLEN-1:0] InstrCountW;
   // ========== Interrupt parsing & spoofing ==========
   string  interrupt;
   string  interruptLine;
@@ -132,7 +128,7 @@ module testbench;
   string  interruptDesc;
   integer           NextMIPexpected, NextSIPexpected;
   integer           NextMepcExpected;
-  logic [`XLEN-1:0] AttemptedInstructionCount;
+  logic [P.XLEN-1:0] AttemptedInstructionCount;
   // ========== Misc Aliases ==========
   `define RF dut.core.ieu.dp.regf.rf
   `define PC dut.core.ifu.pcreg.q
@@ -238,14 +234,14 @@ module testbench;
   initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
   always begin clk <= 1; # 5; clk <= 0; # 5; end
   // Wally Interface
-  logic [`AHBW-1:0] HRDATAEXT;
+  logic [P.AHBW-1:0] HRDATAEXT;
   logic             HREADYEXT, HRESPEXT;
   logic             HCLK, HRESETn;
   logic             HREADY;
   logic 	    HSELEXT;
-  logic [`PA_BITS-1:0] HADDR;
-  logic [`AHBW-1:0] HWDATA;
-  logic [`XLEN/8-1:0] HWSTRB;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0] HWDATA;
+  logic [P.XLEN/8-1:0] HWSTRB;
   logic             HWRITE;
   logic [2:0]       HSIZE;
   logic [2:0]       HBURST;
@@ -268,7 +264,7 @@ module testbench;
   assign UARTSin = 1;
 
   // Wally
-  wallypipelinedsoc dut(.clk, .reset, .reset_ext,
+  wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
                         .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, 
 			.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, 
 			.HTRANS, .HMASTLOCK, 
@@ -278,18 +274,18 @@ module testbench;
 
   // W-stage hardware not needed by Wally itself 
   parameter nop = 'h13;
-  logic [`XLEN-1:0] PCW;
+  logic [P.XLEN-1:0] PCW;
   logic [31:0]      InstrW;
   logic             InstrValidW;
-  logic [`XLEN-1:0] IEUAdrW, WriteDataW;
+  logic [P.XLEN-1:0] IEUAdrW, WriteDataW;
   logic             TrapW;
   `define FLUSHW dut.core.FlushW
   `define STALLW dut.core.StallW
-  flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
+  flopenrc #(P.XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
   flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
   flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
-  flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
-  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
+  flopenrc #(P.XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
+  flopenrc #(P.XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
   flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
 
 
@@ -365,29 +361,29 @@ module testbench;
     end
 
   genvar i;
-  `INIT_CHECKPOINT_SIMPLE_ARRAY(RF,         [`XLEN-1:0],31,1);
-  `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
-  `INIT_CHECKPOINT_VAL(PC,         [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MEDELEG,    [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MIDELEG,    [`XLEN-1:0]);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(RF,         [P.XLEN-1:0],31,1);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [P.XLEN-1:0],P.COUNTERS-1,0);
+  `INIT_CHECKPOINT_VAL(PC,         [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEDELEG,    [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MIDELEG,    [P.XLEN-1:0]);
   if(!NO_SPOOFING) begin
     `INIT_CHECKPOINT_VAL(MIE,        [11:0]);
     `INIT_CHECKPOINT_VAL(MIP,        [11:0]);
     end
-  `INIT_CHECKPOINT_VAL(MCAUSE,     [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SCAUSE,     [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MEPC,       [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SEPC,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MCAUSE,     [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SCAUSE,     [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEPC,       [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SEPC,       [P.XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]);
   `INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]);
-  `INIT_CHECKPOINT_VAL(MSCRATCH,   [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SSCRATCH,   [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(MTVEC,      [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(STVEC,      [`XLEN-1:0]);
-  `INIT_CHECKPOINT_VAL(SATP,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MSCRATCH,   [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SSCRATCH,   [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MTVEC,      [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(STVEC,      [P.XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SATP,       [P.XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(PRIV,       [1:0]);
-  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
-  `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:0],1,0);
+  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],P.PLIC_NUM_SRC,1);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [P.PLIC_NUM_SRC:0],1,0);
   `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
   // UART checkpointing does not cover entire UART state
   //     Many UART registers are difficult to initialize because under the hood
@@ -402,8 +398,8 @@ module testbench;
   `INIT_CHECKPOINT_VAL(UART_SCR,   [7:0]);
   // xSTATUS need to be handled manually because the most upstream signals
   // are made of individual bits, not registers
-  `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
-  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);  
+  `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [P.XLEN-1:0],0,0);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [P.XLEN-1:0],0,0);  
 
   // ========== INITIALIZATION ==========
   initial begin
@@ -458,7 +454,7 @@ module testbench;
       force {`STATUS_SPIE} = initMSTATUS[0][5];
       force {`STATUS_MIE} = initMSTATUS[0][3];
       force {`STATUS_SIE} = initMSTATUS[0][1];
-      force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
+      force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][P.PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][P.PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
       force `INSTRET = CHECKPOINT;
       while (reset!==1) #1;
       while (reset!==0) #1;
@@ -789,7 +785,7 @@ module testbench;
   //////////////////////////////// Extra Features ///////////////////////////////
   ///////////////////////////////////////////////////////////////////////////////
   // Function Tracking
-  FunctionName FunctionName(.reset(reset),
+  FunctionName #(P) FunctionName(.reset(reset),
                             .clk(clk),
                             .ProgramAddrMapFile(ProgramAddrMapFile),
                             .ProgramLabelMapFile(ProgramLabelMapFile));
@@ -814,12 +810,12 @@ module testbench;
    * explanation of the below algorithm.
    */
   logic             SvMode, PTE_R, PTE_X;
-  logic [`XLEN-1:0] SATP, PTE;
+  logic [P.XLEN-1:0] SATP, PTE;
   logic [55:0]      BaseAdr, PAdr;
   logic [8:0]       VPN [2:0];
   logic [11:0]      Offset;
-  function logic [`XLEN-1:0] adrTranslator( 
-    input logic [`XLEN-1:0] adrIn);
+  function logic [P.XLEN-1:0] adrTranslator( 
+    input logic [P.XLEN-1:0] adrIn);
     begin
       int i;
       // Grab the SATP register from privileged unit
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 9712693ec..2cdde5129 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -25,136 +25,40 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+`include "config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 0
-`define BPRED_LOGGER 0
-`define I_CACHE_ADDR_LOGGER 0
-`define D_CACHE_ADDR_LOGGER 0
+import cvw::*;
 
 module testbench;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
   parameter DEBUG=0;
   parameter TEST="none";
+  parameter PrintHPMCounters=0;
+  parameter BPRED_LOGGER=0;
+  parameter I_CACHE_ADDR_LOGGER=0;
+  parameter D_CACHE_ADDR_LOGGER=0;
  
+`include "parameter-defs.vh"
+
   logic        clk;
   logic        reset_ext, reset;
+  logic        ResetMem;
 
-  parameter SIGNATURESIZE = 5000000;
-
-  int test, i, errors, totalerrors;
-  logic [31:0] sig32[0:SIGNATURESIZE];
-  logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
-  logic [`XLEN-1:0] testadr, testadrNoBase;
-  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  logic [31:0] InstrW;
-
-  string tests[];
-  logic [3:0] dummy;
-
-  logic [`AHBW-1:0]    HRDATAEXT;
-  logic                HREADYEXT, HRESPEXT;
-  logic [`PA_BITS-1:0] HADDR;
-  logic [`AHBW-1:0]    HWDATA;
-  logic [`XLEN/8-1:0]  HWSTRB;
-  logic                HWRITE;
-  logic [2:0]          HSIZE;
-  logic [2:0]          HBURST;
-  logic [3:0]          HPROT;
-  logic [1:0]          HTRANS;
-  logic                HMASTLOCK;
-  logic                HCLK, HRESETn;
-  logic [`XLEN-1:0]    PCW;
-
-  string  ProgramAddrMapFile, ProgramLabelMapFile;
-  integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
-
-  logic DCacheFlushDone, DCacheFlushStart;
-  logic riscofTest; 
-  logic StartSample, EndSample;
-    
-  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
-  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
-
-  // check assertions for a legal configuration
-  riscvassertions riscvassertions();
-
-  // pick tests based on modes supported
-  initial begin
-    $display("TEST is %s", TEST);
-    //tests = '{};
-    if (`XLEN == 64) begin // RV64
-      case (TEST)
-        "arch64i":                               tests = arch64i;
-        "arch64priv":                            tests = arch64priv;
-        "arch64c":      if (`C_SUPPORTED) 
-                          if (`ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
-                          else                   tests = {arch64c};
-        "arch64m":      if (`M_SUPPORTED)        tests = arch64m;
-        "arch64f":      if (`F_SUPPORTED)        tests = arch64f;
-        "arch64d":      if (`D_SUPPORTED)        tests = arch64d;  
-        "arch64f_fma":      if (`F_SUPPORTED)        tests = arch64f_fma;
-        "arch64d_fma":      if (`D_SUPPORTED)        tests = arch64d_fma;  
-        "arch64zi":     if (`ZIFENCEI_SUPPORTED) tests = arch64zi;
-        "imperas64i":                            tests = imperas64i;
-        "imperas64f":   if (`F_SUPPORTED)        tests = imperas64f;
-        "imperas64d":   if (`D_SUPPORTED)        tests = imperas64d;
-        "imperas64m":   if (`M_SUPPORTED)        tests = imperas64m;
-        "wally64a":     if (`A_SUPPORTED)        tests = wally64a;
-        "imperas64c":   if (`C_SUPPORTED)        tests = imperas64c;
-                        else                     tests = imperas64iNOc;
-        "custom":                                tests = custom;
-        "wally64i":                              tests = wally64i; 
-        "wally64priv":                           tests = wally64priv;
-        "wally64periph":                         tests = wally64periph;
-        "coremark":                              tests = coremark;
-        "fpga":                                  tests = fpga;
-        "ahb" :                                  tests = ahb;
-        "coverage64gc" :                         tests = coverage64gc;
-        "arch64zba":     if (`ZBA_SUPPORTED)     tests = arch64zba;
-        "arch64zbb":     if (`ZBB_SUPPORTED)     tests = arch64zbb;
-        "arch64zbc":     if (`ZBC_SUPPORTED)     tests = arch64zbc;
-        "arch64zbs":     if (`ZBS_SUPPORTED)     tests = arch64zbs;
-      endcase 
-    end else begin // RV32
-      case (TEST)
-        "arch32i":                               tests = arch32i;
-        "arch32priv":                            tests = arch32priv;
-        "arch32c":      if (`C_SUPPORTED) 
-                          if (`ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
-                          else                   tests = {arch32c};
-        "arch32m":      if (`M_SUPPORTED)        tests = arch32m;
-        "arch32f":      if (`F_SUPPORTED)        tests = arch32f;
-        "arch32d":      if (`D_SUPPORTED)        tests = arch32d;
-        "arch32f_fma":      if (`F_SUPPORTED)        tests = arch32f_fma;
-        "arch32d_fma":      if (`D_SUPPORTED)        tests = arch32d_fma;
-        "arch32zi":     if (`ZIFENCEI_SUPPORTED) tests = arch32zi;
-        "imperas32i":                            tests = imperas32i;
-        "imperas32f":   if (`F_SUPPORTED)        tests = imperas32f;
-        "imperas32m":   if (`M_SUPPORTED)        tests = imperas32m;
-        "wally32a":     if (`A_SUPPORTED)        tests = wally32a;
-        "imperas32c":   if (`C_SUPPORTED)        tests = imperas32c;
-                        else                     tests = imperas32iNOc;
-        "wally32i":                              tests = wally32i; 
-        "wally32e":                              tests = wally32e; 
-        "wally32priv":                           tests = wally32priv;
-        "wally32periph":                         tests = wally32periph;
-        "embench":                               tests = embench;
-        "coremark":                              tests = coremark;
-        "arch32zba":     if (`ZBA_SUPPORTED)     tests = arch32zba;
-        "arch32zbb":     if (`ZBB_SUPPORTED)     tests = arch32zbb;
-        "arch32zbc":     if (`ZBC_SUPPORTED)     tests = arch32zbc;
-        "arch32zbs":     if (`ZBS_SUPPORTED)     tests = arch32zbs;
-      endcase
-    end
-    if (tests.size() == 0) begin
-      $display("TEST %s not supported in this configuration", TEST);
-      $stop;
-    end
-  end
-
-  string  signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
-  integer outputFilePointer;
+  // DUT signals
+  logic [P.AHBW-1:0]    HRDATAEXT;
+  logic                 HREADYEXT, HRESPEXT;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0]    HWDATA;
+  logic [P.XLEN/8-1:0]  HWSTRB;
+  logic                 HWRITE;
+  logic [2:0]           HSIZE;
+  logic [2:0]           HBURST;
+  logic [3:0]           HPROT;
+  logic [1:0]           HTRANS;
+  logic                 HMASTLOCK;
+  logic                 HCLK, HRESETn;
 
   logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
   logic        UARTSin, UARTSout;
@@ -169,28 +73,309 @@ module testbench;
 
   logic        HREADY;
   logic        HSELEXT;
+
   
-  logic        InitializingMemories;
-  integer      ResetCount, ResetThreshold;
-  logic        InReset;
-  logic        BeginSample;
+  string  ProgramAddrMapFile, ProgramLabelMapFile;
+  integer ProgramAddrLabelArray [string];
+
+  int test, i, errors, totalerrors;
+
+  string outputfile;
+  integer outputFilePointer;
+
+  string tests[];
+  logic DCacheFlushDone, DCacheFlushStart;
+  logic riscofTest; 
+  logic Validate;
+  logic SelectTest;
+
+
+  // pick tests based on modes supported
+  initial begin
+    $display("TEST is %s", TEST);
+    //tests = '{};
+    if (P.XLEN == 64) begin // RV64
+      case (TEST)
+        "arch64i":                               tests = arch64i;
+        "arch64priv":                            tests = arch64priv;
+        "arch64c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
+                          else                   tests = {arch64c};
+        "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
+        "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
+        "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
+        "arch64f_fma":      if (P.F_SUPPORTED)        tests = arch64f_fma;
+        "arch64d_fma":      if (P.D_SUPPORTED)        tests = arch64d_fma;  
+        "arch64zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
+        "imperas64i":                            tests = imperas64i;
+        "imperas64f":   if (P.F_SUPPORTED)        tests = imperas64f;
+        "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
+        "imperas64m":   if (P.M_SUPPORTED)        tests = imperas64m;
+        "wally64a":     if (P.A_SUPPORTED)        tests = wally64a;
+        "imperas64c":   if (P.C_SUPPORTED)        tests = imperas64c;
+                        else                     tests = imperas64iNOc;
+        "custom":                                tests = custom;
+        "wally64i":                              tests = wally64i; 
+        "wally64priv":                           tests = wally64priv;
+        "wally64periph":                         tests = wally64periph;
+        "coremark":                              tests = coremark;
+        "fpga":                                  tests = fpga;
+        "ahb" :                                  tests = ahb;
+        "coverage64gc" :                         tests = coverage64gc;
+        "arch64zba":     if (P.ZBA_SUPPORTED)     tests = arch64zba;
+        "arch64zbb":     if (P.ZBB_SUPPORTED)     tests = arch64zbb;
+        "arch64zbc":     if (P.ZBC_SUPPORTED)     tests = arch64zbc;
+        "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
+      endcase 
+    end else begin // RV32
+      case (TEST)
+        "arch32i":                               tests = arch32i;
+        "arch32priv":                            tests = arch32priv;
+        "arch32c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
+                          else                   tests = {arch32c};
+        "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
+        "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
+        "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
+        "arch32f_fma":      if (P.F_SUPPORTED)        tests = arch32f_fma;
+        "arch32d_fma":      if (P.D_SUPPORTED)        tests = arch32d_fma;
+        "arch32zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
+        "imperas32i":                            tests = imperas32i;
+        "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
+        "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
+        "wally32a":     if (P.A_SUPPORTED)        tests = wally32a;
+        "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
+                        else                     tests = imperas32iNOc;
+        "wally32i":                              tests = wally32i; 
+        "wally32e":                              tests = wally32e; 
+        "wally32priv":                           tests = wally32priv;
+        "wally32periph":                         tests = wally32periph;
+        "embench":                               tests = embench;
+        "coremark":                              tests = coremark;
+        "arch32zba":     if (P.ZBA_SUPPORTED)     tests = arch32zba;
+        "arch32zbb":     if (P.ZBB_SUPPORTED)     tests = arch32zbb;
+        "arch32zbc":     if (P.ZBC_SUPPORTED)     tests = arch32zbc;
+        "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
+      endcase
+    end
+    if (tests.size() == 0) begin
+      $display("TEST %s not supported in this configuration", TEST);
+      $stop;
+    end
+  end // initial begin
+
+  // Model the testbench as an fsm.
+  // Do this in parts so it easier to verify
+  // part 1: build a version which echos the same behavior as the below code, but does not drive anything
+  // part 2: drive some of the controls
+  // part 3: drive all logic and remove old inital and always @ negedge clk block
+
+  typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
+                           STATE_INIT_TEST,
+                           STATE_RESET_MEMORIES,
+                           STATE_RESET_MEMORIES2,
+                           STATE_LOAD_MEMORIES,
+                           STATE_RESET_TEST,
+                           STATE_RUN_TEST,
+                           STATE_CHECK_TEST,
+                           STATE_CHECK_TEST_WAIT,
+                           STATE_VALIDATE,
+                           STATE_INCR_TEST} statetype;
+  statetype CurrState, NextState;
+  logic        TestBenchReset;
+  logic [2:0]  ResetCount, ResetThreshold;
+  logic        LoadMem;
+  logic        ResetCntEn;
+  logic        ResetCntRst;
   
+
+  string  signame, memfilename, pathname;
+  integer begin_signature_addr;
+
+  assign ResetThreshold = 3'd5;
+
+  initial begin
+    TestBenchReset = 1;
+    # 100;
+    TestBenchReset = 0;
+  end
+
+  always_ff @(posedge clk)
+    if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
+    else CurrState <= #1 NextState;  
+
+  // fsm next state logic
+  always_comb begin
+    // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
+    // and tests[0] == "2" refers to WallyRiscvArchTests 
+    riscofTest = tests[0] == "1" | tests[0] == "2"; 
+    pathname = tvpaths[tests[0].atoi()];
+
+    case(CurrState)
+      STATE_TESTBENCH_RESET:                      NextState = STATE_INIT_TEST;
+      STATE_INIT_TEST:                            NextState = STATE_RESET_MEMORIES;
+      STATE_RESET_MEMORIES:                       NextState = STATE_RESET_MEMORIES2;
+      STATE_RESET_MEMORIES2:                      NextState = STATE_LOAD_MEMORIES;  // Give the reset enough time to ensure the bus is reset before loading the memories.
+      STATE_LOAD_MEMORIES:                        NextState = STATE_RESET_TEST;
+      STATE_RESET_TEST:      if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_RUN_TEST:        if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_CHECK_TEST:      if (DCacheFlushDone) NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_CHECK_TEST_WAIT: if(DCacheFlushDone)  NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_VALIDATE:                             NextState = STATE_INIT_TEST;
+      STATE_INCR_TEST:                            NextState = STATE_INIT_TEST;
+      default:                                    NextState = STATE_TESTBENCH_RESET;
+    endcase
+  end // always_comb
+  // fsm output control logic 
+  assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | 
+                     CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | 
+                     CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
+  // this initialization is very expensive, only do it for coremark.  
+  assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
+  assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
+  assign ResetCntRst = CurrState == STATE_INIT_TEST;
+  assign ResetCntEn = CurrState == STATE_RESET_TEST;
+  assign Validate = CurrState == STATE_VALIDATE;
+  assign SelectTest = CurrState == STATE_INIT_TEST;
+
+  // fsm reset counter
+  counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Find the test vector files and populate the PC to function label converter
+  ////////////////////////////////////////////////////////////////////////////////
+  assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
+  always @(posedge clk) begin
+    if(SelectTest) begin
+      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+      else            memfilename = {pathname, tests[test], ".elf.memfile"};
+      if (riscofTest) begin
+        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
+      end else begin
+        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
+      end
+      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
+      // the addr of each label and fill the array. To expand, add more elements to this array 
+      // and initialize them to zero (also initilaize them to zero at the start of the next test)
+      if(!P.FPGA) begin
+        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
+      end
+    end
+    
+  ////////////////////////////////////////////////////////////////////////////////
+  // Verify the test ran correctly by checking the memory against a known signature.
+  ////////////////////////////////////////////////////////////////////////////////
+    if(TestBenchReset) test = 1;
+    if (TEST == "coremark")
+      if (dut.core.EcallFaultM) begin
+        $display("Benchmark: coremark is done.");
+        $stop;
+      end
+    if(Validate) begin
+      if (TEST == "embench") begin
+        // Writes contents of begin_signature to .sim.output file
+        // this contains instret and cycles for start and end of test run, used by embench 
+        // python speed script to calculate embench speed score. 
+        // also, begin_signature contains the results of the self checking mechanism, 
+        // which will be read by the python script for error checking
+        $display("Embench Benchmark: %s is done.", tests[test]);
+        if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
+        else outputfile = {pathname, tests[test], ".sim.output"};
+        outputFilePointer = $fopen(outputfile, "w");
+        i = 0;
+        $fclose(outputFilePointer);
+        $display("Embench Benchmark: created output file: %s", outputfile);
+      end else if (TEST == "coverage64gc") begin
+        $display("Coverage tests don't get checked");
+      end else begin 
+        // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+        // clear signature to prevent contamination from previous tests
+      end
+
+      if (!begin_signature_addr)
+        $display("begin_signature addr not found in %s", ProgramLabelMapFile);
+      else begin
+        CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
+      end
+      if(errors > 0) totalerrors = totalerrors + 1;
+      test = test + 1;
+      if (test == tests.size()) begin
+        if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
+        else $display("FAIL: %d test programs had errors", totalerrors);
+        $stop;
+      end
+    end
+  end
+
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Some memories are not reset, but should be zeros or set to some initial value for simulation
+  ////////////////////////////////////////////////////////////////////////////////
+  integer adrindex;
+  always @(posedge clk) begin
+    if (ResetMem)  // program memory is sometimes reset
+      if (P.UNCORE_RAM_SUPPORTED)
+        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
+    if(reset) begin  // branch predictor must always be reset
+      if (P.BPRED_SUPPORTED) begin
+        // local history only
+        if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR)
+          for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
+            dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
+        for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+      end
+    end
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // load memories with program image
+  ////////////////////////////////////////////////////////////////////////////////
+  always @(posedge clk) begin
+    if (LoadMem) begin
+      if (P.FPGA) begin
+        string romfilename, sdcfilename;
+        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
+        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
+        // shorten sdc timers for simulation
+        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+      end 
+      else if (P.IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+      else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      if (P.DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+      $display("Read memfile %s", memfilename);
+    end
+  end  
+ 
+  ////////////////////////////////////////////////////////////////////////////////
+  // Actual hardware
+  ////////////////////////////////////////////////////////////////////////////////
+
   // instantiate device to be tested
   assign GPIOIN = 0;
   assign UARTSin = 1;
 
-  if(`EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) 
+  if(P.EXT_MEM_SUPPORTED) begin
+    ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
     ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
-         .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
-         .HWSTRB);
+      .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
   end else begin 
     assign HREADYEXT = 1;
-    assign HRESPEXT = 0;
-    assign HRDATAEXT = 0;
+    assign {HRESPEXT, HRDATAEXT} = '0;
   end
 
-  if(`FPGA) begin : sdcard
+  if(P.FPGA) begin : sdcard
     sdModel sdcard
       (.sdClk(SDCCLK),
        .cmd(SDCCmd), 
@@ -204,319 +389,48 @@ module testbench;
     assign SDCDat = '0;
   end
 
-  wallypipelinedsoc  dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
-                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+  // generate clock to sequence tests
+  always begin
+    clk = 1; # 5; clk = 0; # 5;
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Support logic
+  ////////////////////////////////////////////////////////////////////////////////
+
+  watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);  // check if PCW is stuck
+  riscvassertions #(P) riscvassertions();  // check assertions for a legal configuration
+  loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
+  loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
+
+  // track the current function or global label
+  if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName
+    FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
+			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
+  end
 
   // Track names of instructions
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
   instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
                 dut.core.ifu.InstrRawF[31:0],
                 dut.core.ifu.InstrD, dut.core.ifu.InstrE,
                 dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
-  // initialize tests
-  localparam 	   MemStartAddr = 0;
-  localparam 	   MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
-
-  initial
-    begin
-      ResetCount = 0;
-      ResetThreshold = 2;
-      InReset = 1;
-      test = 1;
-      totalerrors = 0;
-      testadr = 0;
-      testadrNoBase = 0;
-      // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
-      // and tests[0] == "2" refers to WallyRiscvArchTests 
-      riscofTest = tests[0] == "1" | tests[0] == "2"; 
-      // fill memory with defined values to reduce Xs in simulation
-      // Quick note the memory will need to be initialized.  The C library does not
-      // guarantee the  initialized reads.  For example a strcmp can read 6 byte
-      // strings, but uses a load double to read them in.  If the last 2 bytes are
-      // not initialized the compare results in an 'x' which propagates through 
-      // the design.
-      if (TEST == "coremark") 
-        for (i=MemStartAddr; i<MemEndAddr; i = i+1) 
-          dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0; 
-
-      // read test vectors into memory
-      pathname = tvpaths[tests[0].atoi()];
-      /* if (tests[0] == `IMPERASTEST)
-       pathname = tvpaths[0];
-       else pathname = tvpaths[1]; */
-      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-      else            memfilename = {pathname, tests[test], ".elf.memfile"};
-      if (`FPGA) begin
-        string romfilename, sdcfilename;
-        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
-        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
-        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
-        // force sdc timers
-        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
-      end else begin
-        if (`IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-        else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-        if (`DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
-      end
-
-      if (riscofTest) begin
-        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
-      end else begin
-        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
-      end
-      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
-      // the addr of each label and fill the array. To expand, add more elements to this array 
-      // and initialize them to zero (also initilaize them to zero at the start of the next test)
-      if(!`FPGA) begin
-        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
-        $display("Read memfile %s", memfilename);
-      end
-    end
-
-  // generate clock to sequence tests
-  always
-    begin
-      clk = 1; # 5; clk = 0; # 5;
-      // if ($time % 100000 == 0) $display("Time is %0t", $time);
-    end
-   
-  // check results
-  assign reset_ext = InReset;
-  
-  always @(negedge clk)
-    begin    
-      InitializingMemories = 0;
-      if(InReset == 1) begin
-        // once the test inidicates it's done we need to immediately hold reset for a number of cycles.
-        if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1;
-        else begin // hit reset threshold so we remove reset.
-          InReset = 0; 
-          ResetCount = 0;
-        end
-      end else begin
-        if (TEST == "coremark")
-          if (dut.core.priv.priv.EcallFaultM) begin
-            $display("Benchmark: coremark is done.");
-            $stop;
-          end
-        // Termination condition (i.e. we finished running current test) 
-        if (DCacheFlushDone) begin
-          integer begin_signature_addr;
-          InReset = 1;
-          begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
-          if (!begin_signature_addr)
-            $display("begin_signature addr not found in %s", ProgramLabelMapFile);
-          testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
-          testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
-          #600; // give time for instructions in pipeline to finish
-          if (TEST == "embench") begin
-            // Writes contents of begin_signature to .sim.output file
-            // this contains instret and cycles for start and end of test run, used by embench 
-            // python speed script to calculate embench speed score. 
-            // also, begin_signature contains the results of the self checking mechanism, 
-            // which will be read by the python script for error checking
-            $display("Embench Benchmark: %s is done.", tests[test]);
-            if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
-            else outputfile = {pathname, tests[test], ".sim.output"};
-            outputFilePointer = $fopen(outputfile, "w");
-            i = 0;
-            $fclose(outputFilePointer);
-            $display("Embench Benchmark: created output file: %s", outputfile);
-          end else if (TEST == "coverage64gc") begin
-            $display("Coverage tests don't get checked");
-          end else begin 
-            // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
-            // clear signature to prevent contamination from previous tests
-            for(i=0; i<SIGNATURESIZE; i=i+1) begin
-              sig32[i] = 'bx;
-            end
-            if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
-            else signame = {pathname, tests[test], ".signature.output"};
-            // read signature, reformat in 64 bits if necessary
-            $readmemh(signame, sig32);
-            i = 0;
-            while (i < SIGNATURESIZE) begin
-              if (`XLEN == 32) begin
-                signature[i] = sig32[i];
-                i = i+1;
-              end else begin
-                signature[i/2] = {sig32[i+1], sig32[i]};
-                i = i + 2;
-              end
-              if (i >= 4 & sig32[i-4] === 'bx) begin
-                if (i == 4) begin
-                  i = SIGNATURESIZE+1; // flag empty file
-                  $display("  Error: empty test file");
-                end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
-              end
-            end
-
-            // Check errors
-            errors = (i == SIGNATURESIZE+1); // error if file is empty
-            i = 0;
-            /* verilator lint_off INFINITELOOP */
-            while (signature[i] !== 'bx) begin
-              logic [`XLEN-1:0] sig;
-              if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
-              else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-              //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
-              if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
-                errors = errors+1;
-                $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
-						    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
-                $stop; //***debug
-              end
-              i = i + 1;
-            end
-            /* verilator lint_on INFINITELOOP */
-            if (errors == 0) begin
-              $display("%s succeeded.  Brilliant!!!", tests[test]);
-            end else begin
-              $display("%s failed with %d errors. :(", tests[test], errors);
-              totalerrors = totalerrors+1;
-            end
-          end
-          // move onto the next test, check to see if we're done
-          test = test + 1;
-          if (test == tests.size()) begin
-          if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
-          else $display("FAIL: %d test programs had errors", totalerrors);
-          $stop;
-          end else begin
-            InitializingMemories = 1;
-            // If there are still additional tests to run, read in information for the next test
-            //pathname = tvpaths[tests[0]];
-            if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-            else memfilename = {pathname, tests[test], ".elf.memfile"};
-            //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-            if (`IROM_SUPPORTED)               $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-            else if (`UNCORE_RAM_SUPPORTED)    $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-            if (`DTIM_SUPPORTED)               $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
-
-            if (riscofTest) begin
-              ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
-              ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
-            end else begin
-              ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
-              ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
-            end
-            ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
-            if(!`FPGA) begin
-              updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
-              $display("Read memfile %s", memfilename);
-            end
-          end
-        end // if (DCacheFlushDone)
-      end
-    end // always @ (negedge clk)
-
-
-  if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
-    integer           HPMCindex;
-    logic             StartSampleFirst;
-    logic             StartSampleDelayed, BeginDelayed;
-    logic             EndSampleFirst, EndSampleDelayed;
-    logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
-
-    string  HPMCnames[] = '{"Mcycle",
-                            "------",
-                            "InstRet",
-                            "Br Count",
-                            "Jump Not Return",
-                            "Return",
-                            "BP Wrong",
-                            "BP Dir Wrong",
-                            "BP Target Wrong",
-                            "RAS Wrong",
-                            "Instr Class Wrong",
-                            "Load Stall",
-                            "Store Stall",
-                            "D Cache Access",
-                            "D Cache Miss",
-                            "D Cache Cycles",
-                            "I Cache Access",
-                            "I Cache Miss",
-                            "I Cache Cycles",
-                            "CSR Write",
-                            "FenceI",
-                            "SFenceVMA",
-                            "Interrupt",
-                            "Exception",
-                            "Divide Cycles"
-                          };
-
-    if(TEST == "embench") begin
-      // embench runs warmup then runs start_trigger
-      // embench end with stop_trigger.
-      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
-      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-
-      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
-      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
-
-    end else if(TEST == "coremark") begin
-      // embench runs warmup then runs start_trigger
-	    // embench end with stop_trigger.
-      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
-      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-
-      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
-      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
-
-    end else begin
-      // default start condiction is reset
-      // default end condiction is end of test (DCacheFlushDone)
-      assign StartSampleFirst = InReset;
-      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-      assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
-
-      flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
-      assign BeginSample = StartSampleFirst & ~BeginDelayed;
-
-    end
-    always @(negedge clk) begin
-      if(StartSample) begin
-        for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
-          InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
-        end
-      end
-      if(EndSample) begin
-        for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
-          // unlikely to have more than 10M in any counter.
-          $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
-        end
-      end
-    end
-  end
-  
-
-
-  // track the current function or global label
-  if (DEBUG == 1 | (`PrintHPMCounters & `ZICOUNTERS_SUPPORTED)) begin : FunctionName
-    FunctionName FunctionName(.reset(reset),
-			      .clk(clk),
-			      .ProgramAddrMapFile(ProgramAddrMapFile),
-			      .ProgramLabelMapFile(ProgramLabelMapFile));
-  end
-
   // Termination condition
   // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
   // or sw	gp,-56(t0) for new Imperas tests
   // or sd gp, -56(t0) 
   // or on a jump to self infinite loop (6f) for RISC-V Arch tests
   logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
-  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
   else                  assign ecf = 0;
   assign DCacheFlushStart = ecf & 
 			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
@@ -526,287 +440,103 @@ module testbench;
            ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
            ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
 
-  DCacheFlushFSM DCacheFlushFSM(.clk(clk),
-    			.reset(reset),
-	    		.start(DCacheFlushStart),
-		    	.done(DCacheFlushDone));
+  DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
 
-
-  // initialize the branch predictor
-  if (`BPRED_SUPPORTED) begin
-    integer adrindex;
-
-    // local history only
-    if (`BPRED_TYPE == "BP_LOCAL_AHEAD" | `BPRED_TYPE == "BP_LOCAL_REPAIR") begin
-      always @(*) begin
-        if(reset) begin
-          for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin
-            dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
-          end
-        end
-      end
-    end
-
-    always @(*) begin
-      if(reset) begin
-        for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
-          dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
-        end
-        for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
-          dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
-        end
-      end
-    end
-  end
-
-
-  if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
-    int    file;
-    string LogFile;
-    logic  resetD, resetEdge;
-    logic  Enable;
-    logic  InvalDelayed, InvalEdge;
+  task automatic CheckSignature;
+    // This task must be declared inside this module as it needs access to parameter P.  There is
+    // no way to pass P to the task unless we convert it to a module.
     
-    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
-                    dut.core.ifu.immu.immu.pmachecker.Cacheable &
-                    ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
-                    ~reset;
-    flop #(1) ResetDReg(clk, reset, resetD);
-    assign resetEdge = ~reset & resetD;
+    input string  pathname;
+    input string  TestName;
+    input logic   riscofTest;
+    input integer begin_signature_addr;
+    output integer errors;
 
-    flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
-    assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
-
-    initial begin
-      LogFile = "ICache.log";
-      file = $fopen(LogFile, "w");
-      $fwrite(file, "BEGIN %s\n", memfilename);
-    end
-    string AccessTypeString, HitMissString;
-    assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
-                           dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
-    always @(posedge clk) begin
-    if(resetEdge) $fwrite(file, "TRAIN\n");
-    if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-    if(Enable) begin  // only log i cache reads
-      $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
-    end
-    if(InvalEdge) $fwrite(file, "0 I X\n");
-    if(EndSample) $fwrite(file, "END %s\n", memfilename);
-    end
-  end
-
-
-  if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger
-    int    file;
-    string LogFile;
-    logic  resetD, resetEdge;
-    logic  Enabled;
-    string AccessTypeString, HitMissString;
-
-    flop #(1) ResetDReg(clk, reset, resetD);
-    assign resetEdge = ~reset & resetD;
-    assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
-                           (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
-                           dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
-    assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
-                              dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
-                              dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
-                              dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
-                              "NULL";
+    localparam SIGNATURESIZE = 5000000;
+    integer        i;
+    logic [31:0]   sig32[0:SIGNATURESIZE];
+    logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
+    string            signame, pathname;
+    logic [P.XLEN-1:0] testadr, testadrNoBase;
     
-    assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
-                     ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
-                     dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
-                     (AccessTypeString != "NULL");
-
-    initial begin
-      LogFile = "DCache.log";
-      file = $fopen(LogFile, "w");
-      $fwrite(file, "BEGIN %s\n", memfilename);
+    // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+    // clear signature to prevent contamination from previous tests
+    for(i=0; i<SIGNATURESIZE; i=i+1) begin
+      sig32[i] = 'bx;
     end
-    always @(posedge clk) begin
-      if(resetEdge) $fwrite(file, "TRAIN\n");
-      if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-      if(Enabled) begin
-        $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
+    if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
+    else signame = {pathname, TestName, ".signature.output"};
+    // read signature, reformat in 64 bits if necessary
+    $readmemh(signame, sig32);
+    i = 0;
+    while (i < SIGNATURESIZE) begin
+      if (P.XLEN == 32) begin
+        signature[i] = sig32[i];
+        i = i+1;
+      end else begin
+        signature[i/2] = {sig32[i+1], sig32[i]};
+        i = i + 2;
       end
-      if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
-      if(EndSample) $fwrite(file, "END %s\n", memfilename);
-    end
-  end
-
-  if (`BPRED_SUPPORTED) begin : BranchLogger
-    if (`BPRED_LOGGER) begin
-      string direction;
-      int    file;
-      logic  PCSrcM;
-      string LogFile;
-      logic  resetD, resetEdge;
-      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
-      flop #(1) ResetDReg(clk, reset, resetD);
-      assign resetEdge = ~reset & resetD;
-      initial begin
-        LogFile = "branch.log"; // will break some of Ross's research analysis scripts
-        //LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
-        file = $fopen(LogFile, "w");
-      end
-      always @(posedge clk) begin
-        if(resetEdge) $fwrite(file, "TRAIN\n");
-        if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
-        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
-          direction = PCSrcM ? "t" : "n";
-          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
-        end
-        if(EndSample) $fwrite(file, "END %s\n", memfilename);
+      if (i >= 4 & sig32[i-4] === 'bx) begin
+        if (i == 4) begin
+          i = SIGNATURESIZE+1; // flag empty file
+          $display("  Error: empty test file");
+        end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
       end
     end
-  end
 
-  // check for hang up.
-  logic [`XLEN-1:0] OldPCW;
-  integer           WatchDogTimerCount;
-  localparam        WatchDogTimerThreshold = 1000000;
-  logic             WatchDogTimeOut;
-  always_ff @(posedge clk) begin
-    OldPCW <= PCW;
-    if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
-    else WatchDogTimerCount = '0;
-  end
+    // Check errors
+    errors = (i == SIGNATURESIZE+1); // error if file is empty
+    i = 0;
+    testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
+    testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
+    /* verilator lint_off INFINITELOOP */
+    while (signature[i] !== 'bx) begin
+      logic [P.XLEN-1:0] sig;
+      if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
+      else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
+      if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
+        errors = errors+1;
+        $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
+			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+        $stop; //***debug
+      end
+      i = i + 1;
+    end
+    /* verilator lint_on INFINITELOOP */
+    if (errors == 0) begin
+      $display("%s succeeded.  Brilliant!!!", TestName);
+    end else begin
+      $display("%s failed with %d errors. :(", TestName, errors);
+      //totalerrors = totalerrors+1;
+    end
 
-  always_comb begin
-    WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
-    if(WatchDogTimeOut) begin
-      $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
-      $stop;
-	  end
-  end
+  endtask //
   
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
+
 endmodule
 
 /* verilator lint_on STMTDLY */
 /* verilator lint_on WIDTH */
 
-module DCacheFlushFSM
-  (input logic clk,
-   input logic reset,
-   input logic start,
-   output logic done);
-
-  genvar adr;
-
-  logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
-  
-  if(`DCACHE_SUPPORTED) begin
-    localparam numlines       = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
-    localparam numways        = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
-    localparam linebytelen    = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
-    localparam linelen        = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
-    localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
-    localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
-    localparam numwords       = sramlen/`XLEN;
-    localparam lognumlines    = $clog2(numlines);
-    localparam loglinebytelen = $clog2(linebytelen);
-    localparam lognumways     = $clog2(numways);
-    localparam tagstart       = lognumlines + loglinebytelen;
-
-
-
-    genvar               index, way, cacheWord;
-    logic [sramlen-1:0]  CacheData  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic [sramlen-1:0]  cacheline;
-    logic [`XLEN-1:0]    CacheTag   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic                CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic                CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic [`PA_BITS-1:0] CacheAdr   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    for(index = 0; index < numlines; index++) begin
-      for(way = 0; way < numways; way++) begin
-        for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
-          copyShadow #(.tagstart(tagstart),
-          .loglinebytelen(loglinebytelen), .sramlen(sramlen))
-          copyShadow(.clk,
-          .start,
-          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
-          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
-          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
-                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
-          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
-          .index(index),
-          .cacheWord(cacheWord),
-          .CacheData(CacheData[way][index][cacheWord]),
-          .CacheAdr(CacheAdr[way][index][cacheWord]),
-          .CacheTag(CacheTag[way][index][cacheWord]),
-          .CacheValid(CacheValid[way][index][cacheWord]),
-          .CacheDirty(CacheDirty[way][index][cacheWord]));
-        end
-      end
-    end
-
-    integer i, j, k, l;
-
-    always @(posedge clk) begin
-      if (start) begin 
-        for(i = 0; i < numlines; i++) begin
-          for(j = 0; j < numways; j++) begin
-            for(l = 0; l < cachesramwords; l++) begin
-              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
-                for(k = 0; k < numwords; k++) begin
-                  //cacheline = CacheData[j][i][0];
-                  // does not work with modelsim
-                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
-                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
-                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
-                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
-                end
-              end
-            end
-          end
-        end
-      end
-    end  
-  end
-  flop #(1) doneReg(.clk, .d(start), .q(done));
-endmodule
-
-module copyShadow
-  #(parameter tagstart, loglinebytelen, sramlen)
-  (input  logic                       clk,
-   input  logic                       start,
-   input  logic [`PA_BITS-1:tagstart] tag,
-   input  logic                       valid, dirty,
-   input  logic [sramlen-1:0]         data,
-   input  logic [32-1:0]              index,
-   input  logic [32-1:0]              cacheWord,
-   output logic [sramlen-1:0]         CacheData,
-   output logic [`PA_BITS-1:0]        CacheAdr,
-   output logic [`XLEN-1:0]           CacheTag,
-   output logic                       CacheValid,
-   output logic                       CacheDirty);
-  
-
-  always_ff @(posedge clk) begin
-    if(start) begin
-      CacheTag = tag;
-      CacheValid = valid;
-      CacheDirty = dirty;
-      CacheData = data;
-      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
-    end
-  end
-  
-endmodule
-
 task automatic updateProgramAddrLabelArray;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
   input string ProgramAddrMapFile, ProgramLabelMapFile;
   inout  integer ProgramAddrLabelArray [string];
   // Gets the memory location of begin_signature
   integer ProgramLabelMapFP, ProgramAddrMapFP;
   ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
   ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
-  
+
+
   if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
+    // *** RT: I'm a bit confused by the required initialization here.
+    ProgramAddrLabelArray["begin_signature"] = 0;
+    ProgramAddrLabelArray["tohost"] = 0;
     while (!$feof(ProgramLabelMapFP)) begin
       string label, adrstr;
       integer returncode;
@@ -817,5 +547,7 @@ task automatic updateProgramAddrLabelArray;
   end
   $fclose(ProgramLabelMapFP);
   $fclose(ProgramAddrMapFP);
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
 endtask
 
diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv
new file mode 100644
index 000000000..747b31806
--- /dev/null
+++ b/testbench/wallywrapper.sv
@@ -0,0 +1,102 @@
+///////////////////////////////////////////
+// testbench.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Wally Testbench and helper modules
+//          Applies test programs from the riscv-arch-test and Imperas suites
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "config.vh"
+`include "tests.vh"
+
+`define PrintHPMCounters 0
+`define BPRED_LOGGER 0
+`define I_CACHE_ADDR_LOGGER 0
+`define D_CACHE_ADDR_LOGGER 0
+
+import cvw::*;
+
+module wallywrapper;
+  parameter DEBUG=0;
+  parameter TEST="none";
+ 
+`include "parameter-defs.vh"
+
+  logic        clk;
+  logic        reset_ext, reset;
+
+  parameter SIGNATURESIZE = 5000000;
+
+  int test, i, errors, totalerrors;
+  logic [31:0] sig32[0:SIGNATURESIZE];
+  logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
+  logic [P.XLEN-1:0] testadr, testadrNoBase;
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+
+  string tests[];
+  logic [3:0] dummy;
+
+  logic [P.AHBW-1:0]    HRDATAEXT;
+  logic                HREADYEXT, HRESPEXT;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0]    HWDATA;
+  logic [P.XLEN/8-1:0]  HWSTRB;
+  logic                HWRITE;
+  logic [2:0]          HSIZE;
+  logic [2:0]          HBURST;
+  logic [3:0]          HPROT;
+  logic [1:0]          HTRANS;
+  logic                HMASTLOCK;
+  logic                HCLK, HRESETn;
+
+  logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
+  logic        UARTSin, UARTSout;
+
+  logic        SDCCLK;
+  logic        SDCCmdIn;
+  logic        SDCCmdOut;
+  logic        SDCCmdOE;
+  logic [3:0]  SDCDatIn;
+  tri1  [3:0]  SDCDat;
+  tri1         SDCCmd;
+
+  logic        HREADY;
+  logic        HSELEXT;
+  
+  // instantiate device to be tested
+  assign GPIOIN = 0;
+  assign UARTSin = 1;
+
+    assign HREADYEXT = 1;
+    assign HRESPEXT = 0;
+    assign HRDATAEXT = 0;
+
+    assign SDCCmd = '0;
+    assign SDCDat = '0;
+
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+endmodule