From 9ddfe52c9fd1d82945a6829887c20db4bdeed7cb Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Mon, 13 Mar 2023 11:07:19 +0000 Subject: [PATCH] Fix MISA RO and UART addresses It appears on inspection that the MISA register is read only in Wally In which case this has now also been set in the ImperasDV representation Also the Addresss for the UART R/W privileges are corrected --- sim/imperas.ic | 1 + testbench/testbench_imperas.sv | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index 6a34466f0..3744a4266 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -6,6 +6,7 @@ --override cpu/ignore_non_leaf_DAU=1 --override cpu/wfi_is_nop=T --override cpu/mimpid=0x100 +--override cpu/misa_Extensions_mask=0x0 # THIS NEEDS FIXING to 16 --override cpu/PMP_registers=0 diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 27bd12467..6ac11bc2d 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -178,8 +178,7 @@ module testbench; void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE))); end if (`UART_SUPPORTED) begin - //void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE))); - void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + 7))); // BUG + void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE))); end if (`PLIC_SUPPORTED) begin void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE)));