From 37fc45cd35ebe9df808b061c0dfc4cf34fe8c30c Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 6 May 2024 11:28:00 -0700 Subject: [PATCH 1/9] Updated Questa wally.do to terminate on a compile error --- sim/questa/wally.do | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 33832516b..154d51977 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -19,6 +19,7 @@ # (omit the "-c" to see the GUI while running from the shell) onbreak {resume} +onerror {quit -f} set CFG ${1} set TESTSUITE ${2} @@ -102,6 +103,7 @@ vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgsLst} -o testbenchopt ${CoverageVoptArg} + # *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg} From 9d4a3d7d05426beb659124a420734a8e88d84d70 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 7 May 2024 14:11:40 -0700 Subject: [PATCH 2/9] Started adding testbplan --- docs/testplans/testplan.md | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md index 37390a632..95ce72f8b 100644 --- a/docs/testplans/testplan.md +++ b/docs/testplans/testplan.md @@ -2,27 +2,22 @@ CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction. -| Functions | Coverage Method | Status | -| ----------- | ----------- |----| -| Instructions | riscv-arch-test | Pass | -| Privileged Unit | wally-riscv-arch-test | Pass | -| Virtual Memory | wally-riscv-arch-test | Pass | -| PMP | wally-riscv-arch-test | Pass -| Peripherals | wally-riscv-arch-test | Pass | -| Floating-Point | TestFloat | Pass | -| General | Code Coverage | 91% | -| General | Boot Linux in Sim | Pass | -| General | Boot Linux on FPGA | Pass | +| Tests | Section | TRL3 | TRL5 | Coverage Method | Status | Command | +| ------------------- | -------------- | ------------ | ------ | --------------------- | ------ | ------- | +| Verilator Lint | 5.3 | All configs | rv64gc | lint-wally | PASS | regression-wally --nightly | +| Instructions | 3.7 | All configs | rv64gc | riscv-arch-test | PASS | regression-wally --nightly | +| Privileged | 3.7 | All configs | rv64gc | wally-riscv-arch-test | PASS | regression-wally --nightly | +| Floating-point | 5.11.7, 16.5.3 | rv{32/64}gc + derived | rv64gc | TestFloat | FAIL | regression-wally --nightly | +| CoreMark | 21.1 | Many configs | rv64gc | CoreMark | | regression-wally --nightly | +| Embench | 21.2 | rv32* | n/a | Embench | | regression-wally --nightly | +| Cache PV | 21.3.1 | rv{32/64}gc | rv64gc | TBD | TBD | TBD | +| Cache PV | 21.3.2 | rv{32/64}gc | rv64gc | TBD | TBD | TBD | +| Linux Boot | 22.3.2 | rv64gc | rv64gc | TBD | TBD | TBD | +| FPGA Linux Boot | 23.2 | | rv64gc | TBD | TBD | TBD | +| Code Coverage | 5.11.10 | | rv64gc | TBD | TBD | TBD | +| Functional Coverage | 5.11.11 | | rv64gc | TBD | TBD | TBD | -The following performance validation is also run: -| Function | Method | Status | -| --- | --- | --- | -| Overall Performance | embench | Pass| -| Overall Performance | coremark | Pass | -| Branch Predictor | *** | Pass | -| Cache Miss Rate | *** | Pass | - * Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model. From fcd75fd6b6a61bd954e8745ff4ad14a96d850fbd Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 7 May 2024 14:27:44 -0700 Subject: [PATCH 3/9] Fixed shiftcorrection typo causing failure on testfloat fcvt tests --- src/fpu/postproc/shiftcorrection.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index 1027765e2..85e96c744 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -61,19 +61,20 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( // - a one has to propagate all the way through a sum. so we can leave the bottom statement alone assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1]; + // correct the shifting of the divsqrt caused by producing a result in (0.5, 2) range // condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm) assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); - + assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm; // one bit right shift for FMA or division mux2 #(P.NORMSHIFTSZ-2) corrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], RightShift, CorrShifted); - + // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits always_comb - if (FmaOp | DivOp & !DivResSubnorm) Mf = CorrShifted; - else Mf = Shifted[P.NORMSHIFTSZ-1:2]; + if (FmaOp | (DivOp & ~DivResSubnorm)) Mf = CorrShifted; + else Mf = Shifted[P.NORMSHIFTSZ-1:2]; // Determine sum's exponent // main exponent issues: @@ -92,3 +93,4 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( // if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? 0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1}; endmodule + From 77137f0f60db6881406675424e31aa533c2ae7ef Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 7 May 2024 16:45:49 -0700 Subject: [PATCH 4/9] ZAAMO and ZALRSC implemented but not tested --- config/rv32e/config.vh | 2 ++ config/rv32gc/config.vh | 2 ++ config/rv32i/config.vh | 2 ++ config/rv32imc/config.vh | 2 ++ config/rv64gc/config.vh | 2 ++ config/rv64i/config.vh | 2 ++ config/shared/parameter-defs.vh | 2 ++ src/cvw.sv | 2 ++ src/ieu/controller.sv | 8 ++++---- src/ieu/datapath.sv | 4 ++-- src/lsu/atomic.sv | 21 +++++++++++++++------ src/lsu/lsu.sv | 2 +- testbench/common/riscvassertions.sv | 1 + 13 files changed, 39 insertions(+), 13 deletions(-) diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 5e1f883d4..163ef316b 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index d6fb995b1..8c63d24ff 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -52,6 +52,8 @@ localparam ZICOND_SUPPORTED = 1; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 1; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 490937558..0629461d5 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 357eba840..40b46308f 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -50,6 +50,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 1d6c5e9f4..b82b3cd5d 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 1; localparam SVPBMT_SUPPORTED = 1; localparam SVNAPOT_SUPPORTED = 1; localparam SVINVAL_SUPPORTED = 1; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index a289003cc..4625d3718 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 0; diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 5635b286c..1aa6da5d3 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -31,6 +31,8 @@ localparam cvw_t P = '{ SVPBMT_SUPPORTED : SVPBMT_SUPPORTED, SVNAPOT_SUPPORTED : SVNAPOT_SUPPORTED, SVINVAL_SUPPORTED : SVINVAL_SUPPORTED, + ZAAMO_SUPPORTED : ZAAMO_SUPPORTED, + ZALRSC_SUPPORTED : ZALRSC_SUPPORTED, BUS_SUPPORTED : BUS_SUPPORTED, DCACHE_SUPPORTED : DCACHE_SUPPORTED, ICACHE_SUPPORTED : ICACHE_SUPPORTED, diff --git a/src/cvw.sv b/src/cvw.sv index 75ff3f7e7..cba95c0fa 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -66,6 +66,8 @@ typedef struct packed { logic SVPBMT_SUPPORTED; logic SVNAPOT_SUPPORTED; logic SVINVAL_SUPPORTED; + logic ZAAMO_SUPPORTED; + logic ZALRSC_SUPPORTED; // Microarchitectural Features logic BUS_SUPPORTED; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 45dd92e98..005baa56b 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -265,12 +265,12 @@ module controller import cvw::*; #(parameter cvw_t P) ( ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores 7'b0100111: if (FLSFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported - 7'b0101111: if (P.A_SUPPORTED & AFunctD) begin - if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) + 7'b0101111: if (AFunctD) begin + if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr - else if (InstrD[31:27] == 5'b00011) + else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011) ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc - else if (AMOFunctD) + else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD) ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo end 7'b0110011: if (RFunctD) diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index de3e46b03..30848ea6d 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -139,6 +139,6 @@ module datapath import cvw::*; #(parameter cvw_t P) ( mux5 #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); // handle Store Conditional result if atomic extension supported - if (P.A_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; - else assign SCResultW = '0; + if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; + else assign SCResultW = '0; endmodule diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 7dbd0c8a2..704eb4c62 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -48,11 +48,20 @@ module atomic import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AMOResultM; logic MemReadM; - amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); - - mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); - assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; - - lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); + // AMO ALU + if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin + amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); + mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); + end else + assign IMAWriteDataM = IHWriteDataM; + + // LRSC unit + if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin + assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; + lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); + end else begin + assign SquashSCW = 0; + assign LSURWM = PreLSURWM; + end endmodule diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index cb9cd0722..31441a095 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -397,7 +397,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// - if (P.A_SUPPORTED) begin:atomic + if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .IMAWriteDataM, .SquashSCW, .LSURWM); diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 3f50d3f7c..84b7531a8 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -67,6 +67,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F"); assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache"); + assert (P.A_SUPPORTED + P.ZAAMO_SUPPORTED + P.ZALRSC_SUPPORTED < 2) else $fatal(1, "At most one of A, Zaamo, or Zalrsc can be supported"); end endmodule From 3c86d3d8e0e3d72b00a06bf2938cc63ae3364b62 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 8 May 2024 08:08:58 -0700 Subject: [PATCH 5/9] Run testfloat during nightly regression --- bin/regression-wally | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 6c17d65e3..cacf98247 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -323,9 +323,9 @@ else: addTests(tests_buildrootshort, defaultsim) # testfloat tests -if (testfloat): +if (testfloat): # for testfloat alone, just run testfloat tests configs = [] - +if (testfloat or nightly): # for nightly, run testfloat along with othres testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"] for config in testfloatconfigs: tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"] From ce5390de9cc6b5f1d18d8d3da3555e0d8f21ab96 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 8 May 2024 19:29:36 -0700 Subject: [PATCH 6/9] Fixed UNCORE_RAM_RANGE for rv64i so VCS doesn't choke --- config/rv64i/config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 4625d3718..8bb5ff7f4 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -110,7 +110,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; localparam BOOTROM_PRELOAD = 1'b0; localparam UNCORE_RAM_SUPPORTED = 1'b0; localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; -localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; localparam UNCORE_RAM_PRELOAD = 1'b0; localparam EXT_MEM_SUPPORTED = 1'b0; localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; From 47af54b1315b95e74a64940fe6dd26c3621880c8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 9 May 2024 07:29:45 -0700 Subject: [PATCH 7/9] Fixed buildroot prematurely terminating in VCS --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9536f1cc9..87e517b63 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -633,7 +633,7 @@ module testbench; dut.core.ieu.dp.regf.a3 == 3 & dut.core.ieu.dp.regf.wd3 == 1)) | ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | - ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW" ); end DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone)); From bdd0043cd1564dcb866a47ff95622868dde01583 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 9 May 2024 07:58:53 -0700 Subject: [PATCH 8/9] Testbench terminates buildroot sim at instruction limit --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 87e517b63..084bf02c5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -644,7 +644,7 @@ module testbench; always @(negedge clk) begin if (INSTR_LIMIT > 0) begin if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); - if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end + if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end end end end From a89e064d1d88c7912d0f6596a275e03e8643955e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 9 May 2024 08:20:44 -0700 Subject: [PATCH 9/9] Run both Questa and VCS during nightly regression --- bin/regression-wally | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index cacf98247..8b778907e 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -273,6 +273,7 @@ regressionDir = WALLY + '/sim' os.chdir(regressionDir) coveragesim = "questa" # Questa is required for code/functional coverage +#defaultsim = "vcs" # Default simulator for all other tests; change to Verilator when flow is ready defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready #defaultsim = "verilator" # Default simulator for all other tests @@ -283,7 +284,8 @@ testfloat = '--testfloat' in sys.argv if (nightly): nightMode = "--nightly"; - sims = [defaultsim] +# sims = [defaultsim] + sims = ["questa", "vcs"] # sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators else: nightMode = ""