busybear: make imperas tests work again

wally-pipelined/regression/wally-busybear.do

@@ -37,8 +37,8 @@ mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -fillda
 mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/uncore/bootdtim/RAM
 mem load -startaddress 0 -endaddress 2047 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/bootram
 mem load -startaddress 512 -i "/courses/e190ax/busybear_boot/bootmem.txt" -format hex /testbench_busybear/dut/imem/bootram
-mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/maindtim/RAM
+mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/uncore/dtim/RAM
-mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/maindtim/RAM
+mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/uncore/dtim/RAM
 mem load -startaddress 268435456 -endaddress 285212671 -filltype value -fillradix hex -filldata 0 /testbench_busybear/dut/imem/RAM
 mem load -startaddress 268435456 -i "/courses/e190ax/busybear_boot/ram.txt" -format hex /testbench_busybear/dut/imem/RAM
 
@@ -63,7 +63,7 @@ add wave -divider
 add wave /testbench_busybear/dut/uncore/HSELBootTim
 add wave /testbench_busybear/dut/uncore/HSELTim
 add wave /testbench_busybear/dut/uncore/HREADTim
-add wave /testbench_busybear/dut/uncore/maindtim/HREADTim0
+add wave /testbench_busybear/dut/uncore/dtim/HREADTim0
 add wave /testbench_busybear/dut/uncore/HREADYTim
 add wave -divider
 add wave /testbench_busybear/dut/uncore/HREADBootTim

wally-pipelined/src/uncore/dtim.sv

@@ -35,7 +35,6 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   output logic             HRESPTim, HREADYTim
 );
 
-  //logic [`XLEN-1:0] RAM[0:65535];
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
   logic [31:0] HWADDR;
   logic [`XLEN-1:0] HREADTim0;

wally-pipelined/src/uncore/imem.sv

@@ -33,7 +33,9 @@ module imem (
 
  /* verilator lint_off UNDRIVEN */
   logic [`XLEN-1:0] RAM[`TIMBASE>>(1+`XLEN/32):(`TIMRANGE+`TIMBASE)>>(1+`XLEN/32)];
+  `ifdef BOOTTIMBASE
   logic [`XLEN-1:0] bootram[`BOOTTIMBASE>>(1+`XLEN/32):(`BOOTTIMRANGE+`BOOTTIMBASE)>>(1+`XLEN/32)];
+  `endif
  /* verilator lint_on UNDRIVEN */
   logic [28:0] adrbits;
   logic [`XLEN-1:0] rd;
@@ -44,15 +46,21 @@ module imem (
     else          assign adrbits = AdrF[31:3];
   endgenerate
 
-  //assign #2 rd = RAM[adrbits]; // word aligned
+  `ifndef BOOTTIMBASE
+  assign #2 rd = RAM[adrbits]; // word aligned
+  `else
   assign #2 rd = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options
+  `endif
 
   // hack right now for unaligned 32-bit instructions
   // eventually this will need to cause a stall like a cache miss
   // when the instruction wraps around a cache line
   // could be optimized to only stall when the instruction wrapping is 32 bits
-  //assign #2 rd2 = RAM[adrbits+1][15:0];
+  `ifndef BOOTTIMBASE
+  assign #2 rd2 = RAM[adrbits+1][15:0];
+  `else
   assign #2 rd2 = (AdrF < (`TIMBASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options
+  `endif
   generate 
     if (`XLEN==32) begin
       assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
@@ -60,8 +68,11 @@ module imem (
     end else begin
       assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
                           : (AdrF[1] ? rd[47:16] : rd[31:0]);
+      `ifndef BOOTTIMBASE
+      assign InstrAccessFaultF = |AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE);
+      `else
       assign InstrAccessFaultF = 0; //busybear: for now, i know we're not doing this
-      //assign InstrAccessFaultF = |AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIMBASE | `TIMRANGE);
+      `endif
     end
   endgenerate
 endmodule

wally-pipelined/src/uncore/uncore.sv

@@ -58,30 +58,42 @@ module uncore (
   );
   
   logic [`XLEN-1:0] HWDATA;
-  logic [`XLEN-1:0] HREADBootTim, HREADTim, HREADCLINT, HREADGPIO, HREADUART;
+  logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADGPIO, HREADUART;
-  logic            HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, PreHSELUART, HSELUART;
+  logic            HSELTim, HSELCLINT, HSELGPIO, PreHSELUART, HSELUART;
-  logic            HRESPBootTim, HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
+  logic            HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
-  logic            HREADYBootTim, HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;  
+  logic            HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;  
   logic [1:0]      MemRW;
-  logic [1:0]      MemRWboottim, MemRWtim, MemRWclint, MemRWgpio, MemRWuart;
+  logic [1:0]      MemRWtim, MemRWclint, MemRWgpio, MemRWuart;
+  `ifdef BOOTTIMBASE
+  logic [`XLEN-1:0] HREADBootTim; 
+  logic            HSELBootTim, HRESPBootTim, HREADYBootTim;
+  logic [1:0]      MemRWboottim;
+  `endif
   logic            UARTIntr;// *** will need to tie INTR to an interrupt handler
   
 
   // AHB Address decoder
   adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim);
+  `ifdef BOOTTIMBASE
   adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim);
+  `endif
   adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT);
-  // Busybear: for now, leaving out gpio since OVPsim doesn't seem to have it
+  `ifdef GPIOBASE
-  //adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO); 
+  adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO); 
+  `endif
   adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART);
   assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported
   
   // Enable read or write based on decoded address
   assign MemRW = {~HWRITE, HWRITED};
+  `ifdef BOOTTIMBASE
   assign MemRWboottim = MemRW & {2{HSELBootTim}};
+  `endif
   assign MemRWtim = MemRW & {2{HSELTim}};
   assign MemRWclint = MemRW & {2{HSELCLINT}};
-  //assign MemRWgpio = MemRW & {2{HSELGPIO}};
+  `ifdef GPIOBASE
+  assign MemRWgpio = MemRW & {2{HSELGPIO}};
+  `endif
   assign MemRWuart = MemRW & {2{HSELUART}};
 /*  always_ff @(posedge HCLK) begin
     HADDRD <= HADDR;
@@ -95,13 +107,17 @@ module uncore (
   subwordwrite sww(.*);
 
   // tightly integrated memory
-  dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) maindtim (.*);
+  dtim #(.BASE(`TIMBASE), .RANGE(`TIMRANGE)) dtim (.*);
+  `ifdef BOOTTIMBASE
   dtim #(.BASE(`BOOTTIMBASE), .RANGE(`BOOTTIMRANGE)) bootdtim (.MemRWtim(MemRWboottim), 
               .HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
+  `endif
 
   // memory-mapped I/O peripherals
   clint clint(.HADDR(HADDR[15:0]), .*);
-  //gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts
+  `ifdef GPIOBASE
+  gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts
+  `endif
   uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
             .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), 
             .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); 
@@ -109,12 +125,39 @@ module uncore (
   // mux could also include external memory  
   // AHB Read Multiplexer
   assign HRDATA = ({`XLEN{HSELTim}} & HREADTim) | ({`XLEN{HSELCLINT}} & HREADCLINT) | 
-                     ({`XLEN{HSELBootTim}} & HREADBootTim) | ({`XLEN{HSELUART}} & HREADUART);
+                    `ifdef GPIOBASE
-  assign HRESP = HSELBootTim & HRESPBootTim | HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | HSELUART & HRESPUART;
+                     ({`XLEN{HSELGPIO}} & HREADGPIO) |
-  assign HREADY = HSELBootTim & HREADYBootTim | HSELTim & HREADYTim | HSELCLINT & HREADYCLINT |  HSELUART & HREADYUART;
+                    `endif
+                    `ifdef BOOTTIMBASE
+                     ({`XLEN{HSELBootTim}} & HREADBootTim) |
+                    `endif
+                     ({`XLEN{HSELUART}} & HREADUART);
+  assign HRESP = HSELTim & HRESPTim | HSELCLINT & HRESPCLINT | 
+                 `ifdef GPIOBASE
+                 HSELGPIO & HRESPGPIO | 
+                 `endif
+                 `ifdef BOOTTIMBASE
+                 HSELBootTim & HRESPBootTim | 
+                 `endif
+                 HSELUART & HRESPUART;
+  assign HREADY = HSELTim & HREADYTim | HSELCLINT & HREADYCLINT | 
+                  `ifdef GPIOBASE
+                  HSELGPIO & HREADYGPIO | 
+                  `endif
+                  `ifdef BOOTTIMBASE
+                  HSELBootTim & HREADYBootTim | 
+                  `endif
+                  HSELUART & HREADYUART;
 
   // Faults
-  assign DataAccessFaultM = ~(HSELTim | HSELCLINT | HSELUART);
+  assign DataAccessFaultM = ~(HSELTim | HSELCLINT | 
+                            `ifdef GPIOBASE
+                            HSELGPIO |
+                            `endif
+                            `ifdef BOOTTIMBASE
+                            HSELBootTim |
+                            `endif
+                            HSELUART);
 
  
 endmodule

wally-pipelined/testbench/testbench-imperas.sv

@@ -407,9 +407,9 @@ string tests32i[] = {
         i = 0;
         errors = 0;
         if (`XLEN == 32)
-          testadr = tests[test+1].atohex()/4;
+          testadr = (`TIMBASE+tests[test+1].atohex())/4;
         else
-          testadr = tests[test+1].atohex()/8;
+          testadr = (`TIMBASE+tests[test+1].atohex())/8;
         /* verilator lint_off INFINITELOOP */
         while (signature[i] !== 'bx) begin
           //$display("signature[%h] = %h", i, signature[i]);

wally-pipelined/testbench/testbench-peripherals.sv

@@ -136,9 +136,9 @@ module testbench();
         i = 0;
         errors = 0;
         if (`XLEN == 32)
-          testadr = tests[test+1].atohex()/4;
+          testadr = (`TIMBASE+tests[test+1].atohex())/4;
         else
-          testadr = tests[test+1].atohex()/8;
+          testadr = (`TIMBASE+tests[test+1].atohex())/8;
         /* verilator lint_off INFINITELOOP */
         while (signature[i] !== 'bx) begin
           //$display("signature[%h] = %h", i, signature[i]);