diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 7fd36b054..24857837b 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -5,7 +5,7 @@ ## ## Written: lserafini@hmc.edu ## Created: 27 March 2023 -## Modified: 5 April 2023 +## Modified: 12 April 2023 ## ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 65ea0162e..1b7407a08 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -36,18 +36,17 @@ coverage exclude -srcfile lzc.sv coverage exclude -scope /core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY -###################### -# Toggle exclusions -# Not used because toggle coverage isn't measured -###################### +# Excluding peripherals as sources of instructions for the ifu +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec -# Exclude DivBusyE from all design units because rv64gc uses the fdivsqrt unit for integer division -#coverage exclude -togglenode DivBusyE -du * -# Exclude QuotM and RemM from MDU because rv64gc uses the fdivsqrt rather tha div unit for integer division -#coverage exclude -togglenode /dut/core/mdu/mdu/QuotM -#coverage exclude -togglenode /dut/core/mdu/mdu/RemM - -# StallFCause is hardwired to 0 -#coverage exclude -togglenode /dut/core/hzu/StallFCause +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec +#Excluding the bootrom, uncoreran, and clint as sources for the lsu +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec +#set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] +#coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 299281d5f..56a76c9ac 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ########################################### -## CacheSimTest.py +## rv64gc_CacheSim.py ## ## Written: lserafini@hmc.edu ## Created: 11 April 2023 diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index d1d54097e..2a5cb8235 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback) // performance counter outputs output logic CacheMiss, // Cache miss - output logic CacheAccess, // Cache access + output logic CacheAccess, // Cache access // cache internals input logic CacheHit, // Exactly 1 way hits @@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic FlushAdrFlag, // On last set of a cache flush input logic FlushWayFlag, // On the last way for any set of a cache flush output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr - output logic SetValid, // Set the dirty bit in the selected way and set + output logic SetValid, // Set the valid bit in the selected way and set output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic SetDirty, // Set the dirty bit in the selected way and set output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 174b82c59..e727662d6 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -35,7 +35,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant - input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr + input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [`PA_BITS-1:0] PAdr, // Physical address input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only) input logic SetValid, // Set the valid bit in the selected way and set @@ -45,14 +45,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic VictimWay, // LRU selected this way as victim to evict input logic FlushWay, // This way is selected for flush and possible writeback if dirty - input logic InvalidateCache,//Clear all valid bits + input logic InvalidateCache,// Clear all valid bits input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only) output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid output logic HitWay, // This way hits output logic ValidWay, // This way is valid output logic DirtyWay, // This way is dirty - output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid + output logic [TAGLEN-1:0] TagWay); // This way's tag if valid localparam WORDSPERLINE = LINELEN/`XLEN; localparam BYTESPERLINE = LINELEN/8; diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 3be33d997..63c234328 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -71,11 +71,11 @@ module fcmp ( // EQ - quiet - sets invalid if signaling NaN input always_comb begin case (OpCtrl[2:0]) - 3'b110: CmpNV = EitherSNaN;//min - 3'b101: CmpNV = EitherSNaN;//max - 3'b010: CmpNV = EitherSNaN;//equal - 3'b001: CmpNV = EitherNaN;//less than - 3'b011: CmpNV = EitherNaN;//less than or equal + 3'b110: CmpNV = EitherSNaN; //min + 3'b101: CmpNV = EitherSNaN; //max + 3'b010: CmpNV = EitherSNaN; //equal + 3'b001: CmpNV = EitherNaN; //less than + 3'b011: CmpNV = EitherNaN; //less than or equal default: CmpNV = 1'bx; endcase end @@ -137,19 +137,19 @@ module fcmp ( if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN else CmpFpRes = Y; // X = NaN Y != NaN else - if(YNaN) CmpFpRes = X; // X != NaN Y = NaN + if(YNaN) CmpFpRes = X; // X != NaN Y = NaN else // X,Y != NaN - if(LT) CmpFpRes = Y; // X < Y - else CmpFpRes = X; // X > Y + if(LT) CmpFpRes = Y; // X < Y + else CmpFpRes = X; // X > Y else // MIN if(XNaN) if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN else CmpFpRes = Y; // X = NaN Y != NaN else - if(YNaN) CmpFpRes = X; // X != NaN Y = NaN + if(YNaN) CmpFpRes = X; // X != NaN Y = NaN else // X,Y != NaN - if(LT) CmpFpRes = X; // X < Y - else CmpFpRes = Y; // X > Y + if(LT) CmpFpRes = X; // X < Y + else CmpFpRes = Y; // X > Y // LT/LE/EQ // - -0 = 0 diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index b34001077..f0d8ca85a 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -93,24 +93,24 @@ module fctrl ( // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled - ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; + ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) - ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format + ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format else begin - ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // default: non-implemented instruction + ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed case(OpD) 7'b0000111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw - 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld - 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq - 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh + 3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw + 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld + 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq + 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh endcase 7'b0100111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw - 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd - 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq - 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh + 3'b010: ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw + 3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd + 3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq + 3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh endcase 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub @@ -123,25 +123,25 @@ module fctrl ( 7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv 7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt 7'b00100??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj - 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn - 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx + 3'b000: ControlsD = `FCTRLW'b1_0_00_00_000_0_0_0; // fsgnj + 3'b001: ControlsD = `FCTRLW'b1_0_00_00_001_0_0_0; // fsgnjn + 3'b010: ControlsD = `FCTRLW'b1_0_00_00_010_0_0_0; // fsgnjx endcase 7'b00101??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin - 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax + 3'b000: ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0; // fmin + 3'b001: ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0; // fmax endcase 7'b10100??: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq - 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt - 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle + 3'b010: ControlsD = `FCTRLW'b0_1_00_00_010_0_0_0; // feq + 3'b001: ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0; // flt + 3'b000: ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0; // fle endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass + ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass else if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w / fmv.x.d to int register 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg + ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) @@ -242,17 +242,20 @@ module fctrl ( // X - all except int->fp, store, load, mv int->fp assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store - ((FResSelD==2'b11)&FRegWriteD)| // mv int to float + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float - There was an issue here, this condition was not refering to mv int -> fp // ((FResSelD==2'b11)&FRegWriteD)| ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float // Y - all except cvt, mv, load, class, sqrt - assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class - (FResSelD==2'b11)| // mv both ways + assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class + ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))| // mv int to float as above // previously mv both ways - Another issue here, previously (FResSelD==2'b11)| does not cover mv both way int-> fp and fp-> int + ((FResSelD==2'b11)&(PostProcSelD==2'b00))| // mv float to int // mv both ways ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt + // Removed (FResSelD==2'b11)| removed to avoid redundancy + // Z - fma ops only - assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub - + assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub // Removed &(FResSelD==2'b01) because it' redundant, Changed all the xx PostProcSelD to 00 to avoid unnecessary contention errors. + // Final Res Sel: // fp int diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index 9ce938709..f85206b41 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -48,7 +48,7 @@ module fsgninj ( // format final result based on precision // - uses NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s + // - if there are any unused bits the most significant bits are filled with 1s if (`FPSIZES == 1) assign SgnRes = {ResSgn, X[`FLEN-2:0]}; diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 77c4b6158..8732f29f2 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -27,7 +27,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module popcnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] num, // number to count total ones + input logic [WIDTH-1:0] num, // number to count total ones output logic [$clog2(WIDTH):0] PopCnt // the total number of ones ); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d18e20ecc..25395825b 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -300,7 +300,7 @@ module controller( assign FlushDCacheD = 0; end - // Decocde stage pipeline control register + // Decode stage pipeline control register flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index d6fe92a2a..df9216761 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -138,7 +138,8 @@ module datapath ( assign MulDivResultW = MDUResultW; end end else begin:fpmux - assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW; + assign IFResultM = IEUResultM; + assign IFCvtResultW = IFResultW; assign MulDivResultW = MDUResultW; end mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index a4ee1cc3e..967a2101e 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -32,7 +32,7 @@ module regfile ( input logic clk, reset, input logic we3, // Write enable - input logic [ 4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3) + input logic [4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3) input logic [`XLEN-1:0] wd3, // Write data for port 3 output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2 diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 132ec590f..5227ee3bd 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -32,7 +32,7 @@ module shifter ( input logic [`XLEN-1:0] A, // shift Source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift + input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index f0882ddf7..bc9ae0abe 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -44,7 +44,7 @@ module decompress ( logic [5:0] immSH; logic [1:0] op; - // Extrac op and register source/destination fields + // Extract op and register source/destination fields assign instr16 = InstrRawD[15:0]; // instruction is already aligned assign op = instr16[1:0]; assign rds1 = instr16[11:7]; diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 75b2bc9e8..82e8a33b9 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -4,7 +4,7 @@ // Written: David_Harris@hmc.edu 9 January 2021 // Modified: // -// Purpose: Instrunction Fetch Unit +// Purpose: Instruction Fetch Unit // PC, branch prediction, instruction cache // // A component of the CORE-V-WALLY configurable RISC-V project. @@ -362,7 +362,7 @@ module ifu ( assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD; // Misaligned PC logic - // Instruction address misalignement only from br/jal(r) instructions. + // Instruction address misalignment only from br/jal(r) instructions. // instruction address misalignment is generated by the target of control flow instructions, not // the fetch itself. // xret and Traps both cannot produce instruction misaligned. @@ -372,7 +372,7 @@ module ifu ( // Spec 3.1.14 // Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec. assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE; - flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); + flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); // Instruction and PC/PCLink pipeline registers // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0. diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 29ae36966..64fdc2891 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -69,8 +69,8 @@ module mdu( 3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulh 3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhsu 3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhu - 3'b100: PrelimResultM = QuotM; // div - 3'b101: PrelimResultM = QuotM; // divu + 3'b100: PrelimResultM = QuotM; // div + 3'b101: PrelimResultM = QuotM; // divu 3'b110: PrelimResultM = RemM; // rem 3'b111: PrelimResultM = RemM; // remu endcase diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index ffd01c440..ccbbfaf78 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -49,14 +49,14 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( output logic Idempotent, // PMA indicates memory address is idempotent output logic SelTIM, // Select a tightly integrated memory // Faults - output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources - output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources - output logic UpdateDA, // page fault due to setting dirty or access bit - output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources + output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources + output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources + output logic UpdateDA, // page fault due to setting dirty or access bit + output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources // PMA checker signals - input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type - input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration - input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses + input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type + input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses ); logic [`PA_BITS-1:0] TLBPAdr; // physical address for TLB @@ -86,7 +86,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( .DisableTranslation, .PTE, .PageTypeWriteVal, .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, .Translate, .TLBPageFault, .UpdateDA); - end else begin:tlb// just pass address through as physical + end else begin:tlb // just pass address through as physical assign Translate = 0; assign TLBMiss = 0; assign TLBHit = 1; // *** is this necessary diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 92efebbf7..94c72a134 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -93,7 +93,7 @@ module csrsr ( // harwired STATUS bits assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported - assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported + assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported /* assign STATUS_UBE = 0; // little-endian diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 417956ed4..b3c0efeab 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -49,8 +49,8 @@ module testbench; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; -string tests[]; -logic [3:0] dummy; + string tests[]; + logic [3:0] dummy; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; @@ -559,11 +559,8 @@ end int file; string LogFile; logic resetD, resetEdge; - logic Enable; - // assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; + logic Enable, InvalDelayed; - // this version of Enable allows for accurate eviction logging. - // Likely needs further improvement. assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & dut.core.ifu.immu.immu.pmachecker.Cacheable & ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage & @@ -596,13 +593,13 @@ end if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger int file; - string LogFile; - logic resetD, resetEdge; + string LogFile; + logic resetD, resetEdge; logic Enabled; string AccessTypeString, HitMissString; - flop #(1) ResetDReg(clk, reset, resetD); - assign resetEdge = ~reset & resetD; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; @@ -611,12 +608,7 @@ end dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : "NULL"; - // assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) & - // ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & - // (AccessTypeString != "NULL"); - - // This version of enable allows for accurate eviction logging. - // Likely needs further improvement. + assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & diff --git a/testbench/tests.vh b/testbench/tests.vh index 55cf464fa..6a0f80276 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -52,7 +52,8 @@ string tvpaths[] = '{ "fpu", "lsu", "vm64check", - "pmp" + "pmp", + "tlbKP" }; string coremark[] = '{ diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 02b3f4a49..9c8f3d344 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -31,6 +31,11 @@ main: #bseti t0, zero, 14 # turn on FPU csrs mstatus, t0 + #Pull denormalized FP number from memory and pass it to fclass.S for coverage + la t0, TestData + flw ft0, 0(t0) + fclass.s t1, ft0 + # Test legal instructions not covered elsewhere flq ft0, 0(a0) flh ft0, 8(a0) @@ -98,3 +103,7 @@ main: j done +.section .data +.align 3 +TestData: +.int 0x00100000 #Denormalized FP number \ No newline at end of file diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S index 63fbda8da..c50b79eb7 100644 --- a/tests/coverage/lsu.S +++ b/tests/coverage/lsu.S @@ -30,4 +30,4 @@ main: sfence.vma x0, x0 // sfence.vma to assert TLBFlush - j done + j done \ No newline at end of file diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S new file mode 100644 index 000000000..5aaf5c195 --- /dev/null +++ b/tests/coverage/tlbKP.S @@ -0,0 +1,143 @@ +/////////////////////////////////////////// +// lsu_test.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + + li t0, 0x80015000 + + li t2, 0 # i = 0 + li t3, 33 # Max amount of Loops = 32 + +loop: bge t2, t3, finished # exit loop if i >= loops + lw t1, 0(t0) + li t4, 0x1000 + add t0, t0, t4 + addi t2, t2, 1 + j loop + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong + +.align 12 + .8byte 0x0000000000000000 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + + +.align 12 + .8byte 0x0000000020004CC1 + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + +.align 12 + #80000000 + .8byte 0x200000CF + .8byte 0x200004CF + .8byte 0x200008CF + .8byte 0x20000CCF + + .8byte 0x200010CF + .8byte 0x200014CF + .8byte 0x200018CF + .8byte 0x20001CCF + + .8byte 0x200020CF + .8byte 0x200024CF + .8byte 0x200028CF + .8byte 0x20002CCF + + .8byte 0x200030CF + .8byte 0x200034CF + .8byte 0x200038CF + .8byte 0x20003CCF + + .8byte 0x200040CF + .8byte 0x200044CF + .8byte 0x200048CF + .8byte 0x20004CCF + + .8byte 0x200050CF + .8byte 0x200054CF + .8byte 0x200058CF + .8byte 0x20005CCF + + .8byte 0x200060CF + .8byte 0x200064CF + .8byte 0x200068CF + .8byte 0x20006CCF + + .8byte 0x200070CF + .8byte 0x200074CF + .8byte 0x200078CF + .8byte 0x20007CCF + + .8byte 0x200080CF + .8byte 0x200084CF + .8byte 0x200088CF + .8byte 0x20008CCF + + .8byte 0x200090CF + .8byte 0x200094CF + .8byte 0x200098CF + .8byte 0x20009CCF + + .8byte 0x200100CF + .8byte 0x200104CF + .8byte 0x200108CF + .8byte 0x20010CCF + + .8byte 0x200110CF + .8byte 0x200114CF + .8byte 0x200118CF + .8byte 0x20011CCF + + .8byte 0x200120CF + .8byte 0x200124CF + .8byte 0x200128CF + .8byte 0x20012CCF + + .8byte 0x200130CF + .8byte 0x200134CF