diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c
index b5438590f..6642afe28 100644
--- a/fpga/rvvidaemon/rvvidaemon.c
+++ b/fpga/rvvidaemon/rvvidaemon.c
@@ -176,19 +176,32 @@ int main(int argc, char **argv){
 
   /* Construct the Ethernet header */
   memset(sendbuf, 0, BUF_SIZ);
+  sendbuf[0] = DEST_MAC0;
+  sendbuf[1] = DEST_MAC1;
+  sendbuf[2] = DEST_MAC2;
+  sendbuf[3] = DEST_MAC3;
+  sendbuf[4] = DEST_MAC4;
+  sendbuf[5] = DEST_MAC5;
+  sendbuf[6] = SRC_MAC0;
+  sendbuf[7] = SRC_MAC1;
+  sendbuf[8] = SRC_MAC2;
+  sendbuf[9] = SRC_MAC3;
+  sendbuf[10] = SRC_MAC4;
+  sendbuf[11] = SRC_MAC5;
+
   /* Ethernet header */
-  sendeh->ether_shost[0] = SRC_MAC0;
-  sendeh->ether_shost[1] = SRC_MAC1;
-  sendeh->ether_shost[2] = SRC_MAC2;
-  sendeh->ether_shost[3] = SRC_MAC3;
-  sendeh->ether_shost[4] = SRC_MAC4;
-  sendeh->ether_shost[5] = SRC_MAC5;
-  sendeh->ether_dhost[0] = DEST_MAC0;
-  sendeh->ether_dhost[1] = DEST_MAC1;
-  sendeh->ether_dhost[2] = DEST_MAC2;
-  sendeh->ether_dhost[3] = DEST_MAC3;
-  sendeh->ether_dhost[4] = DEST_MAC4;
-  sendeh->ether_dhost[5] = DEST_MAC5;
+  /* sendeh->ether_shost[0] = SRC_MAC0; */
+  /* sendeh->ether_shost[1] = SRC_MAC1; */
+  /* sendeh->ether_shost[2] = SRC_MAC2; */
+  /* sendeh->ether_shost[3] = SRC_MAC3; */
+  /* sendeh->ether_shost[4] = SRC_MAC4; */
+  /* sendeh->ether_shost[5] = SRC_MAC5; */
+  /* sendeh->ether_dhost[0] = DEST_MAC0; */
+  /* sendeh->ether_dhost[1] = DEST_MAC1; */
+  /* sendeh->ether_dhost[2] = DEST_MAC2; */
+  /* sendeh->ether_dhost[3] = DEST_MAC3; */
+  /* sendeh->ether_dhost[4] = DEST_MAC4; */
+  /* sendeh->ether_dhost[5] = DEST_MAC5; */
   /* Ethertype field */
   //eh->ether_type = htons(ETH_P_IP);
   sendeh->ether_type = htons(ETHER_TYPE);
diff --git a/src/rvvi/triggergen.sv b/src/rvvi/triggergen.sv
index f8dc4ba8d..76d166380 100644
--- a/src/rvvi/triggergen.sv
+++ b/src/rvvi/triggergen.sv
@@ -46,9 +46,9 @@ module triggergen import cvw::*; (
   logic 	    RvviAxiRvalidDelay;
   logic 	    Match, Overflow, Mismatch, Threshold;
    
-  assign mem[0] = 32'h0000_1654; // src mac [31:0]
-  assign mem[1] = 32'h6843_8F54; // dst mac [15:0], src mac [47:32]
-  assign mem[2] = 32'h4502_1111; // dst mac [47:16]
+  assign mem[0] = 32'h1111_6843; // dst mac [31:0]
+  assign mem[1] = 32'h1654_4502; // src mac [15:0], dst mac [47:32]
+  assign mem[2] = 32'h8f54_0000; // src mac [47:16]
   assign mem[3] = 32'h7274_005c; // "rt", ether type 005c
   assign mem[4] = 32'h6e69_6769; // "igin" (trigin)