From cf39819bace39db8d1c186f5de888c567de5f3db Mon Sep 17 00:00:00 2001
From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com>
Date: Sun, 11 Jun 2023 16:49:20 -0700
Subject: [PATCH] Update fregfile.sv

Program clean up
---
 src/fpu/fregfile.sv | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv
index 74d4d84e1..6ab14df20 100644
--- a/src/fpu/fregfile.sv
+++ b/src/fpu/fregfile.sv
@@ -30,8 +30,8 @@ module fregfile #(parameter FLEN) (
   input logic              clk, reset,
   input logic              we4,             // write enable
   input logic [4:0]        a1, a2, a3, a4,  // adresses
-  input logic [FLEN-1:0]  wd4,             // write data
-  output logic [FLEN-1:0] rd1, rd2, rd3    // read data
+  input logic [FLEN-1:0]   wd4,             // write data
+  output logic [FLEN-1:0]  rd1, rd2, rd3    // read data
 );
    
    logic [FLEN-1:0] rf[31:0];
@@ -51,4 +51,3 @@ module fregfile #(parameter FLEN) (
    assign #2 rd3 = rf[a3];
    
 endmodule // regfile
-