diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index ddf0f77dc..c9ceb455e 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -161,7 +161,7 @@ module lsu (
       .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(),
       .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAmoAccessFaultM,
       .InstrPageFaultF(),.LoadPageFaultM, .StoreAmoPageFaultM,
-      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,  
+      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,   // *** these faults need to be supressed during hptw.
       .DAPageFault(DataDAPageFaultM),
          // *** should use LSURWM as this is includes the lr/sc squash. However this introduces a combo loop
          // from squash, depends on LSUPAdrM, depends on TLBHit, depends on these *AccessM inputs.