From ceb7df356135acad8905af57c3338601d8c58533 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Tue, 23 Feb 2021 18:59:06 +0000 Subject: [PATCH] busybear: instantiate soc instead of hart --- wally-pipelined/regression/wally-busybear.do | 116 +++++++++--------- .../src/wally/wallypipelinedsocbusybear.sv | 81 ++++++++++++ .../testbench/testbench-busybear.sv | 92 +++++++------- 3 files changed, 186 insertions(+), 103 deletions(-) create mode 100644 wally-pipelined/src/wally/wallypipelinedsocbusybear.sv diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 2eb67e6ba..a6b50c23f 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -42,84 +42,84 @@ add wave /testbench_busybear/reset add wave -divider add wave -hex /testbench_busybear/PCtext add wave -hex /testbench_busybear/pcExpected -add wave -hex /testbench_busybear/dut/ifu/PCF -add wave -hex /testbench_busybear/dut/ifu/InstrF +add wave -hex /testbench_busybear/dut/hart/ifu/PCF +add wave -hex /testbench_busybear/dut/hart/ifu/InstrF add wave /testbench_busybear/lastInstrF add wave /testbench_busybear/speculative add wave /testbench_busybear/lastPC2 add wave -divider -#add wave -hex /testbench_busybear/dut/priv/csr/MTVEC_REG -#add wave -hex /testbench_busybear/dut/priv/csr/MSTATUS_REG -#add wave -hex /testbench_busybear/dut/priv/csr/SCOUNTEREN_REG -#add wave -hex /testbench_busybear/dut/priv/csr/MIE_REG -#add wave -hex /testbench_busybear/dut/priv/csr/MIDELEG_REG -#add wave -hex /testbench_busybear/dut/priv/csr/MEDELEG_REG +#add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG +#add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG +#add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG +#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIE_REG +#add wave -hex /testbench_busybear/dut/hart/priv/csr/MIDELEG_REG +#add wave -hex /testbench_busybear/dut/hart/priv/csr/MEDELEG_REG add wave -divider # registers! add wave -hex /testbench_busybear/regExpected add wave -hex /testbench_busybear/regNumExpected add wave -hex /testbench_busybear/HWRITE -add wave -hex /testbench_busybear/dut/MemRWM[1] +add wave -hex /testbench_busybear/dut/hart/MemRWM[1] add wave -hex /testbench_busybear/HWDATA add wave -hex /testbench_busybear/HRDATA add wave -hex /testbench_busybear/HADDR -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[3] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[4] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[5] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[6] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[7] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[8] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[9] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[10] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[11] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[12] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[13] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[14] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[15] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[16] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[17] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[18] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[19] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[20] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[21] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[22] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[23] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[24] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[25] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[26] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[27] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[28] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[29] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[30] -add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[31] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[1] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[2] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[3] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[4] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[5] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[6] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[7] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[8] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[9] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[10] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[11] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[12] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[13] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[14] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[15] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[16] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[17] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[18] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[19] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[20] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[21] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[22] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[23] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[24] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[25] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[26] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[27] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[28] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[29] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[30] +add wave -hex /testbench_busybear/dut/hart/ieu/dp/regf/rf[31] add wave /testbench_busybear/InstrFName -add wave -hex /testbench_busybear/dut/ifu/PCD -#add wave -hex /testbench_busybear/dut/ifu/InstrD +add wave -hex /testbench_busybear/dut/hart/ifu/PCD +#add wave -hex /testbench_busybear/dut/hart/ifu/InstrD add wave /testbench_busybear/InstrDName #add wave -divider -add wave -hex /testbench_busybear/dut/ifu/PCE -##add wave -hex /testbench_busybear/dut/ifu/InstrE +add wave -hex /testbench_busybear/dut/hart/ifu/PCE +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrE add wave /testbench_busybear/InstrEName -#add wave -hex /testbench_busybear/dut/ieu/dp/SrcAE -#add wave -hex /testbench_busybear/dut/ieu/dp/SrcBE -add wave -hex /testbench_busybear/dut/ieu/dp/ALUResultE -#add wave /testbench_busybear/dut/ieu/dp/PCSrcE +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcAE +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/SrcBE +add wave -hex /testbench_busybear/dut/hart/ieu/dp/ALUResultE +#add wave /testbench_busybear/dut/hart/ieu/dp/PCSrcE #add wave -divider -add wave -hex /testbench_busybear/dut/ifu/PCM -##add wave -hex /testbench_busybear/dut/ifu/InstrM +add wave -hex /testbench_busybear/dut/hart/ifu/PCM +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrM add wave /testbench_busybear/InstrMName -#add wave /testbench_busybear/dut/dmem/dtim/memwrite -#add wave -hex /testbench_busybear/dut/dmem/AdrM -#add wave -hex /testbench_busybear/dut/dmem/WriteDataM +#add wave /testbench_busybear/dut/hart/dmem/dtim/memwrite +#add wave -hex /testbench_busybear/dut/hart/dmem/AdrM +#add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM #add wave -divider -add wave -hex /testbench_busybear/dut/ifu/PCW -##add wave -hex /testbench_busybear/dut/ifu/InstrW +add wave -hex /testbench_busybear/dut/hart/ifu/PCW +##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW add wave /testbench_busybear/InstrWName -#add wave /testbench_busybear/dut/ieu/dp/RegWriteW -#add wave -hex /testbench_busybear/dut/ieu/dp/ResultW -#add wave -hex /testbench_busybear/dut/ieu/dp/RdW +#add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/ResultW +#add wave -hex /testbench_busybear/dut/hart/ieu/dp/RdW #add wave -divider ##add ww #add wave -hex -r /testbench_busybear/* diff --git a/wally-pipelined/src/wally/wallypipelinedsocbusybear.sv b/wally-pipelined/src/wally/wallypipelinedsocbusybear.sv new file mode 100644 index 000000000..26df7681a --- /dev/null +++ b/wally-pipelined/src/wally/wallypipelinedsocbusybear.sv @@ -0,0 +1,81 @@ +/////////////////////////////////////////// +// wally-pipelinedsoc.sv +// +// Written: David_Harris@hmc.edu 6 November 2020 +// Modified: +// +// Purpose: System on chip including pipelined processor and memories +// Full RV32/64IC instruction set +// +// Note: the CSRs do not support the following features +//- Disabling portions of the instruction set with bits of the MISA register +//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register +// As of January 2020, virtual memory is not yet supported +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module wallypipelinedsocbusybear ( + input logic clk, reset, + // AHB Lite Interface + // inputs from external memory + input logic [`AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + // outputs to external memory, shared with uncore memory + output logic HCLK, HRESETn, + output logic [31:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, + // I/O Interface + input logic [31:0] GPIOPinsIn, + output logic [31:0] GPIOPinsOut, GPIOPinsEn, + input logic UARTSin, + output logic UARTSout, + // to instruction memory *** remove later + output logic [`XLEN-1:0] PCF, + input logic [31:0] InstrF, + input logic [`AHBW-1:0] HRDATA // from AHB mux in uncore +); + + + // Uncore signals + logic HREADY, HRESP; + logic InstrAccessFaultF, DataAccessFaultM; + logic TimerIntM, SwIntM; // from CLINT + logic ExtIntM = 0; // not yet connected + + + // for now, seem to need these to be like this + // until we get a better idea + assign HREADY = 1; + assign HRESP = 0; + assign InstrAccessFaultF = 0; + assign DataAccessFaultM = 0; + + // instantiate processor and memories + wallypipelinedhart hart(.*); + + //imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished*** + //uncore uncore(.HWDATAIN(HWDATA), .*); +endmodule diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index fa9b64473..198d0b062 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -24,19 +24,15 @@ module testbench_busybear(); logic [1:0] HTRANS; logic HMASTLOCK; logic HCLK, HRESETn; + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic UARTSout; assign GPIOPinsIn = 0; assign UARTSin = 1; - assign HREADY = 1; - assign HRESP = 0; - assign HRDATA = 0; - - // for now, seem to need these to be zero until we get a better idea - assign InstrAccessFaultF = 0; - assign DataAccessFaultM = 0; // instantiate processor and memories - wallypipelinedhart dut(.*); + wallypipelinedsocbusybear dut(.*); // initialize test initial @@ -103,26 +99,32 @@ module testbench_busybear(); end end - logic[63:0] adrTranslation[4:0]; - string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"}; integer warningCount = 0; - initial begin - for(int i=0; i<5; i++) begin - adrTranslation[i] = 64'b0; - end - end + //logic[63:0] adrTranslation[4:0]; + //string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"}; + //initial begin + // for(int i=0; i<5; i++) begin + // adrTranslation[i] = 64'b0; + // end + //end + + //function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func); + // if (adr[11:0] !== adrExpected[11:0]) begin + // equal = 1'b0; + // end else begin + // equal = 1'b1; + // if ((adr+adrTranslation[func]) !== adrExpected) begin + // adrTranslation[func] = adrExpected - adr; + // $display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs); + // warningCount += 1; + // end + // end + //endfunction + + // pretty sure this isn't necessary anymore, but keeping this for now since its easier function logic equal(logic[63:0] adr, logic[63:0] adrExpected, integer func); - if (adr[11:0] !== adrExpected[11:0]) begin - equal = 1'b0; - end else begin - equal = 1'b1; - if ((adr+adrTranslation[func]) !== adrExpected) begin - adrTranslation[func] = adrExpected - adr; - $display("warning: probably new address translation %x for %s at instr %0d", adrTranslation[func], translationType[func], instrs); - warningCount += 1; - end - end + equal = adr === adrExpected; endfunction @@ -138,11 +140,11 @@ module testbench_busybear(); genvar i; generate for(i=1; i<32; i++) begin - always @(dut.ieu.dp.regf.rf[i]) begin + always @(dut.hart.ieu.dp.regf.rf[i]) begin if ($time == 0) begin scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); - if (dut.ieu.dp.regf.rf[i] != regExpected) begin - $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected); + if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin + $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); `ERROR end end else begin @@ -152,13 +154,13 @@ module testbench_busybear(); $display("%t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected); `ERROR end - if (~equal(dut.ieu.dp.regf.rf[i],regExpected, 0)) begin - $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.ieu.dp.regf.rf[i], regExpected); + if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin + $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); `ERROR end - if (dut.ieu.dp.regf.rf[i] !== regExpected) begin - force dut.ieu.dp.regf.rf[i] = regExpected; - release dut.ieu.dp.regf.rf[i]; + if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin + force dut.hart.ieu.dp.regf.rf[i] = regExpected; + release dut.hart.ieu.dp.regf.rf[i]; end end end @@ -167,8 +169,8 @@ module testbench_busybear(); logic [`XLEN-1:0] readAdrExpected; // this might need to change - always @(dut.MemRWM[1] or HADDR) begin - if (dut.MemRWM[1]) begin + always @(dut.hart.MemRWM[1] or HADDR) begin + if (dut.hart.MemRWM[1]) begin if($feof(data_file_memR)) begin $display("no more memR data to read"); `ERROR @@ -246,9 +248,9 @@ module testbench_busybear(); end \ end `define CHECK_CSR(CSR) \ - `CHECK_CSR2(CSR, dut.priv.csr) - `define CSRM dut.priv.csr.genblk1.csrm - `define CSRS dut.priv.csr.genblk1.csrs.genblk1 + `CHECK_CSR2(CSR, dut.hart.priv.csr) + `define CSRM dut.hart.priv.csr.genblk1.csrm + `define CSRS dut.hart.priv.csr.genblk1.csrs.genblk1 //`CHECK_CSR(FCSR) `CHECK_CSR2(MCAUSE, `CSRM) @@ -286,8 +288,8 @@ module testbench_busybear(); string PCtextW, PCtext2W; logic [31:0] InstrWExpected; logic [63:0] PCWExpected; - always @(dut.ifu.PCW or dut.ieu.InstrValidW) begin - if(dut.ieu.InstrValidW && dut.ifu.PCW != 0) begin + always @(dut.hart.ifu.PCW or dut.hart.ieu.InstrValidW) begin + if(dut.hart.ieu.InstrValidW && dut.hart.ifu.PCW != 0) begin if($feof(data_file_PCW)) begin $display("no more PC data to read"); `ERROR @@ -300,8 +302,8 @@ module testbench_busybear(); scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected); // then expected PC value scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected); - if(~equal(dut.ifu.PCW,PCWExpected,2)) begin - $display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.ifu.PCW, PCWExpected); + if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin + $display("%t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected); `ERROR end //if(it.InstrW != InstrWExpected) begin @@ -384,9 +386,9 @@ module testbench_busybear(); string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; instrNameDecTB dec(InstrF, InstrFName); - instrTrackerTB it(clk, reset, dut.ieu.dp.FlushE, - dut.ifu.InstrD, dut.ifu.InstrE, - dut.ifu.InstrM, InstrW, + instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, + dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, + dut.hart.ifu.InstrM, InstrW, InstrDName, InstrEName, InstrMName, InstrWName); // generate clock to sequence tests