Merge branch 'main' of https://github.com/openhwgroup/cvw

bin/regression-wally

@@ -28,9 +28,9 @@ tests = [
         ["rv32i", ["arch32i"]],
         ["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]],
         ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", 
-                    "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a", "arch32zifencei", "arch32zicond", 
+                    "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond", 
                     "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", 
-                    "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a", "wally32priv", "wally32periph", "arch32zcb",
+                    "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb",
                     "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], 
          ["rv64i", ["arch64i"]]
         ]
@@ -51,7 +51,7 @@ tests_buildrootboot = [
 # Separate out floating-point tests for RV64 to speed up coverage
 tests64gc_nofp = [
         ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zcb",
-                    "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", 
+                    "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv", 
                     "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
                     "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]] # add when working:  "arch64zicboz"
     ]
@@ -93,6 +93,12 @@ derivconfigtests = [
         ["nodcache_rv64gc", ["ahb64"]],
         ["nocache_rv64gc", ["ahb64"]],
 
+# Atomic variatnts
+        ["zaamo_rv64gc", ["arch64i", "arch64a_amo"]],
+        ["zalrsc_rv64gc", ["arch64i", "wally64a_lrsc"]],
+        ["zaamo_rv32gc", ["arch32i", "arch32a_amo"]],
+        ["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]],
+
         ### add misaligned tests
 
         # fp/int divider permutations

bin/wsim

@@ -54,10 +54,7 @@ for d in ["logs", "wkdir", "cov"]:
 cd = "cd $WALLY/sim/" +args.sim
 if (args.sim == "questa"):
     if (args.tb == "testbench_fp"):
-         args.args = " -GTEST=" + args.testsuite + " " + args.args
+            args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
-#         cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + " -GTEST=" + args.testsuite + " " + args.args
-#    else:
-#        cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
     cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
     if (args.coverage):
         cmd += " -coverage"
@@ -76,7 +73,7 @@ elif (args.sim == "verilator"):
     if (args.gui):
         print("GUI option not available for Verilator")
         exit(1)
-    os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} EXTRA_ARGS='{args.args}'")
+    os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} EXTRA_ARGS='{args.args}'")
 elif (args.sim == "vcs"):
     print(f"Running VCS on " + args.config + " " + args.testsuite)
     if (args.gui):  

config/derivlist.txt

@@ -511,6 +511,22 @@ BIGENDIAN_SUPPORTED 0
 deriv nobigendian_rv64gc rv64gc
 BIGENDIAN_SUPPORTED 0
 
+deriv zaamo_rv32gc rv32gc
+MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZAAMO_SUPPORTED 1
+
+deriv zalrsc_rv32gc rv32gc
+MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZALRSC_SUPPORTED 1
+
+deriv zaamo_rv64gc rv64gc
+MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZAAMO_SUPPORTED 1
+
+deriv zalrsc_rv64gc rv64gc
+MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZALRSC_SUPPORTED 1
+
 # Floating-point modes supported
 
 deriv f_rv32gc rv32gc

examples/link/link.ld

@@ -4,7 +4,7 @@ ENTRY(rvtest_entry_point)
 SECTIONS
 {
   . = 0x80000000;
-  .text : { *(.text.init) }
+  .text : { *(.text.init) *(.text) }
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }
   . = ALIGN(0x1000);

sim/questa/sim-testfloat-verilator

@@ -16,11 +16,7 @@
 # sqrt   - test square root
 # all    - test everything
 
-#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
+wsim fdqh_ieee_rv64gc add --tb testbench_fp --sim verilator
-
-verilator -GTEST="\"all\"" -GTEST_SIZE="\"all\"" --timescale "1ns/1ns" --timing --binary --top-module testbenchfp "-I../config/shared" "-I../config/deriv/fdqh_ieee_rv64gc" ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv --relative-includes
-
-#vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
 
 # Change TEST_SIZE to only test certain FP width
 # values are QP, DP, SP, HP or all for all tests

sim/verilator/Makefile

@@ -16,6 +16,7 @@ EXTRA_ARGS=
 
 WALLYCONF?=rv64gc
 TEST?=arch64i
+TESTBENCH?=testbench 	
 
 # constants
 # assume WALLY variable is correctly configured in the shell environment
@@ -24,47 +25,60 @@ TARGET=$(WORKING_DIR)/target
 # INCLUDE_PATH are pathes that Verilator should search for files it needs
 INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
 # SOURCES are source files
-SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
 # DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
 DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
 
+# regular testbench requires a wrapper defining getenvval
+ifeq ($(TESTBENCH), testbench)
+	WRAPPER=${WALLY}/sim/verilator/wrapper.c
+	GTEST=
+	ARGTEST=+TEST=$(TEST)
+else
+	WRAPPER=
+	GTEST=-GTEST="\"${TEST}\"" 
+	ARGTEST=
+endif
+
 default: run
 
-run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
+run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}
 	mkdir -p $(VERILATOR_DIR)/logs
-	wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
+	wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST} 
 	
-profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
+profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
-	$(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 
+	$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
 	mv gmon.out gmon_$(WALLYCONF).out
-	gprof $(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log
+	gprof $(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log
 	verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2
 	mkdir -p $(VERILATOR_DIR)/logs_profiling
 	mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
 	echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
 
-wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(DEPENDENCIES)
+wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}: $(DEPENDENCIES)
 	mkdir -p wkdir/$(WALLYCONF)_$(TEST)
 	verilator \
-	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \
+	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o V${TESTBENCH} \
 	--binary --trace \
 	$(OPT) $(PARAMS) $(NONPROF) \
 	$(EXTRA_ARGS) \
-	--top-module testbench  --relative-includes \
+	--top-module ${TESTBENCH}  --relative-includes \
 	$(INCLUDE_PATH) \
-	${WALLY}/sim/verilator/wrapper.c \
+	${WRAPPER} \
+	${GTEST} \
 	$(SOURCES)
 
-obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
+obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF): $(DEPENDENCIES)
 	mkdir -p obj_dir_profiling
 	verilator \
-	--Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \
+	--Mdir obj_dir_profiling -o V${TESTBENCH}_$(WALLYCONF) \
 	--binary \
 	--prof-cfuncs $(OPT) $(PARAMS) \
 	$(EXTRA_ARGS) \
-	--top-module testbench  --relative-includes \
+	--top-module ${TESTBENCH}  --relative-includes \
 	$(INCLUDE_PATH) \
-	${WALLY}/sim/verilator/wrapper.c \
+	${WRAPPER} \
+	${GTEST} \
 	$(SOURCES)
 
 clean:

testbench/testbench.sv

@@ -128,7 +128,7 @@ module testbench;
                           if (P.ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
                           else                    tests = {arch64c};
         "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
-        "arch64a":      if (P.A_SUPPORTED)        tests = arch64a;
+        "arch64a_amo":      if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED)        tests = arch64a_amo;
         "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
         "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
         "arch64f_fma":  if (P.F_SUPPORTED)        tests = arch64f_fma;
@@ -142,7 +142,7 @@ module testbench;
         "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
         "imperas64m":   if (P.M_SUPPORTED)        tests = imperas64m;
         "wally64q":     if (P.Q_SUPPORTED)        tests = wally64q;
-        "wally64a":     if (P.A_SUPPORTED)        tests = wally64a;
+        "wally64a_lrsc":     if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED)        tests = wally64a_lrsc;
         "imperas64c":   if (P.C_SUPPORTED)        tests = imperas64c;
                         else                      tests = imperas64iNOc;
         "custom":                                 tests = custom;
@@ -181,7 +181,7 @@ module testbench;
                           if (P.ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
                           else                    tests = {arch32c};
         "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
-        "arch32a":      if (P.A_SUPPORTED)        tests = arch32a;
+        "arch32a_amo":      if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED)  tests = arch32a_amo; 
         "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
         "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
         "arch32f_fma":  if (P.F_SUPPORTED)        tests = arch32f_fma;
@@ -193,7 +193,7 @@ module testbench;
         "imperas32i":                             tests = imperas32i;
         "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
         "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
-        "wally32a":     if (P.A_SUPPORTED)        tests = wally32a;
+        "wally32a_lrsc":     if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED)        tests = wally32a_lrsc; 
         "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
                         else                      tests = imperas32iNOc;
         "wally32i":                               tests = wally32i; 

testbench/testbench_fp.sv

@@ -51,16 +51,16 @@ module testbench_fp;
    logic [31:0] 		errors=0;                   // how many errors
    logic [31:0] 		VectorNum=0;                // index for test vector
    logic [31:0] 		FrmNum=0;                   // index for rounding mode
-   logic [P.FLEN*4+7:0] 	TestVectors[MAXVECTORS-1:0];     // list of test vectors
+   logic [P.Q_LEN*4+7:0] 	TestVectors[MAXVECTORS-1:0];     // list of test vectors
 
    logic [1:0] 			FmtVal;                     // value of the current Fmt
    logic [2:0] 			UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
    logic                        WriteIntVal;                // value of the current WriteInt
-   logic [P.FLEN-1:0] 		X, Y, Z;                    // inputs read from TestFloat
+   logic [P.Q_LEN-1:0] 		X, Y, Z;                    // inputs read from TestFloat
    logic [P.FLEN-1:0] 		XPostBox;                   // inputs read from TestFloat
    logic [P.XLEN-1:0] 		SrcA;                       // integer input
-   logic [P.FLEN-1:0] 		Ans;                        // correct answer from TestFloat
+   logic [P.Q_LEN-1:0] 		Ans;                        // correct answer from TestFloat
-   logic [P.FLEN-1:0] 		Res;                        // result from other units
+   logic [P.Q_LEN-1:0] 		Res;                        // result from other units
    logic [4:0] 			AnsFlg;                     // correct flags read from testfloat
    logic [4:0] 			ResFlg, Flg;                // Result flags
    logic [P.FMTBITS-1:0] 	ModFmt;                     // format - 10 = half, 00 = single, 01 = double, 11 = quad
@@ -733,7 +733,7 @@ module testbench_fp;
    if (TEST === "cmp" | TEST === "all") begin: fcmp
       fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Zfa(1'b0), .Xs, .Ys, .Xe, .Ye, 
                    .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
-                   .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
+                   .XNaN, .YNaN, .XSNaN, .YSNaN, .X(X[P.FLEN-1:0]), .Y(Y[P.FLEN-1:0]), .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
    end
    
    if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
@@ -975,7 +975,7 @@ module testbench_fp;
          errors += 1;
          $display("\nError in %s", Tests[TestNum]);
          $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);	 
-         $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
+         $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X[P.FLEN-1:0], Y[P.FLEN-1:0], Z[P.FLEN-1:0], SrcA, Res[P.FLEN-1:0], ResFlg, Ans[P.FLEN-1:0], AnsFlg);
          $stop;
       end
 
@@ -1012,14 +1012,14 @@ endmodule
 
 module readvectors import cvw::*; #(parameter cvw_t P) (
 		    input logic 		clk,
-		    input logic [P.FLEN*4+7:0] 	TestVector,
+		    input logic [P.Q_LEN*4+7:0] 	TestVector,
 		    input logic [P.FMTBITS-1:0] ModFmt,
 		    input logic [1:0] 		Fmt,
 		    input logic [2:0] 		Unit,
 		    input logic [31:0] 		VectorNum,
 		    input logic [31:0] 		TestNum,
 		    input logic [2:0] 		OpCtrl,
-		    output logic [P.FLEN-1:0] 	Ans,
+		    output logic [P.Q_LEN-1:0] 	Ans,
 		    output logic [P.XLEN-1:0] 	SrcA,
 		    output logic [4:0] 		AnsFlg,
 		    output logic 		Xs, Ys, Zs, // sign bits of XYZ
@@ -1031,7 +1031,8 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		    output logic 		XZero, YZero, ZZero, // is XYZ zero
 		    output logic 		XInf, YInf, ZInf, // is XYZ infinity
 		    output logic 		XExpMax,
-		    output logic [P.FLEN-1:0] 	X, Y, Z, XPostBox
+		    output logic [P.Q_LEN-1:0] 	X, Y, Z,
+          output logic [P.FLEN-1:0]  XPostBox
 		    );
 
    localparam Q_LEN = 32'd128;
@@ -1048,7 +1049,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
       case (Unit)
 	`FMAUNIT:
           case (Fmt)
-            2'b11: begin // quad
+            2'b11: if (P.Q_SUPPORTED) begin // quad
                if (OpCtrl === `FMA_OPCTRL) begin
 		  X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)];
 		  Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
@@ -1371,7 +1372,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
    assign ZEn = (Unit == `FMAUNIT);
    assign FPUActive = 1'b1;
    
-   unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
+   unpack #(P) unpack(.X(X[P.FLEN-1:0]), .Y(Y[P.FLEN-1:0]), .Z(Z[P.FLEN-1:0]), .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
                       .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
                       .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
                       .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);

testbench/tests.vh

@@ -927,12 +927,12 @@ string imperas32f[] = '{
     "rv64i_m/Q/src/WALLY-q-01.S"
   };
 
- string wally64a[] = '{
+ string wally64a_lrsc[] = '{
     `WALLYTEST,
     "rv64i_m/privilege/src/WALLY-lrsc-01.S"
   };
 
- string wally32a[] = '{
+ string wally32a_lrsc[] = '{
     `WALLYTEST,
     "rv32i_m/privilege/src/WALLY-lrsc-01.S"
  };
@@ -974,7 +974,7 @@ string imperas32f[] = '{
     "rv64i_m/Zicond/src/czero.nez-01.S"
     };
 
-  string arch32a[] = '{
+  string arch32a_amo[] = '{
     `RISCVARCHTEST,
     "rv32i_m/A/src/amoadd.w-01.S",
     "rv32i_m/A/src/amoand.w-01.S",
@@ -1136,7 +1136,7 @@ string imperas32f[] = '{
     "rv64i_m/M/src/remw-01.S"
    };
 
-  string arch64a[] = '{
+  string arch64a_amo[] = '{
     `RISCVARCHTEST,
     "rv64i_m/A/src/amoadd.w-01.S",
     "rv64i_m/A/src/amoand.w-01.S",