mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Removed postprocessing script from Coremark because percentages are already computed
This commit is contained in:
parent
09c8886f0d
commit
cea6f89ac8
@ -3,8 +3,8 @@
|
|||||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
|
|
||||||
PORT_DIR = $(CURDIR)/riscv64-baremetal
|
PORT_DIR = $(CURDIR)/riscv64-baremetal
|
||||||
cmbase=../../addins/coremark
|
cmbase= $(WALLY)/addins/coremark
|
||||||
work_dir= work
|
work_dir= $(WALLY)/benchmarks/coremark/work
|
||||||
XLEN ?=64
|
XLEN ?=64
|
||||||
sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
|
sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
|
||||||
$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
|
$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
|
||||||
@ -23,9 +23,6 @@ all: $(work_dir)/coremark.bare.riscv.elf.memfile
|
|||||||
|
|
||||||
run:
|
run:
|
||||||
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
|
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
|
||||||
# cd ../benchmarks/coremark/
|
|
||||||
# KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
|
|
||||||
python3 coremark-postprocess.py
|
|
||||||
|
|
||||||
$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
|
$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
|
||||||
riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
|
riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
|
||||||
|
@ -1,66 +0,0 @@
|
|||||||
#!/usr/bin/env python
|
|
||||||
#########################################################
|
|
||||||
#
|
|
||||||
# coremark postprocessing script
|
|
||||||
#
|
|
||||||
# Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
|
||||||
#
|
|
||||||
# Created 2022-09-25
|
|
||||||
#
|
|
||||||
# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
|
||||||
##################################################
|
|
||||||
|
|
||||||
logFile = "../../benchmarks/coremark/work/coremark.sim.log"
|
|
||||||
|
|
||||||
with open(logFile, "r") as logRead:
|
|
||||||
logLines = logRead.readlines()
|
|
||||||
|
|
||||||
for lineNum in range(len(logLines)):
|
|
||||||
contents = logLines[lineNum].lower().split()
|
|
||||||
if "branches" in contents and "miss" in contents:
|
|
||||||
branchMisses = int(contents[-1])
|
|
||||||
elif "branches" in contents:
|
|
||||||
branchesTot = int(contents[-1])
|
|
||||||
branchLineNum = lineNum + 2
|
|
||||||
|
|
||||||
if "d-cache" in contents and "misses" in contents:
|
|
||||||
dCacheMisses = int(contents[-1])
|
|
||||||
elif "d-cache" in contents:
|
|
||||||
dCacheAccess = int(contents[-1])
|
|
||||||
dCacheLineNum = lineNum + 2
|
|
||||||
|
|
||||||
if "i-cache" in contents and "misses" in contents:
|
|
||||||
ICacheMisses = int(contents[-1])
|
|
||||||
elif "i-cache" in contents:
|
|
||||||
ICacheAccess = int(contents[-1])
|
|
||||||
ICacheLineNum = lineNum + 2
|
|
||||||
|
|
||||||
# prevent division by zero
|
|
||||||
if (dCacheAccess == 0):
|
|
||||||
dCacheAccess = 1;
|
|
||||||
if (ICacheAccess == 0):
|
|
||||||
ICacheAccess = 1;
|
|
||||||
if (branchesTot == 0):
|
|
||||||
branchesTot = 1;
|
|
||||||
|
|
||||||
# need to add the number of previously added lines to the line number so that they stay in the intedned order.
|
|
||||||
logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n")
|
|
||||||
logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n")
|
|
||||||
logLines.insert(dCacheLineNum+2, "# D-cache Hit Rate " + str((dCacheAccess - dCacheMisses) / dCacheAccess) + "\n")
|
|
||||||
|
|
||||||
logLines.insert(ICacheLineNum+3, "# I-cache Hits " + str(ICacheAccess - ICacheMisses) + "\n")
|
|
||||||
logLines.insert(ICacheLineNum+4, "# I-cache Miss Rate " + str(ICacheMisses / ICacheAccess) + "\n")
|
|
||||||
logLines.insert(ICacheLineNum+5, "# I-cache Hit Rate " + str((ICacheAccess - ICacheMisses) / ICacheAccess) + "\n")
|
|
||||||
|
|
||||||
logLines.insert(branchLineNum+6, "# Branches Miss/Total ratio " + str(branchMisses / branchesTot) + "\n")
|
|
||||||
|
|
||||||
|
|
||||||
with open(logFile, "w") as logWrite:
|
|
||||||
logWrite.writelines(logLines)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue
Block a user