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renamed multimanager to multicontroller.

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This commit is contained in:
Ross Thompson 2022-09-14 14:03:37 -05:00
parent bf6468a24c
commit cea012a640
4 changed files with 26 additions and 26 deletions
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20
pipelined/regression/wave.do
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@ -169,16 +169,16 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group AHB -expand -group multimanager -color Gold /testbench/dut/core/ebu/ebu/CurrState add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/both add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/save add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/save
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/restore add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/restore
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/dis add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/dis
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/sel add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/sel
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/IFUActive add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUActive
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/LSUActive add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUActive
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/BeatCount add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount
add wave -noupdate -group AHB -expand -group multimanager /testbench/dut/core/ebu/ebu/BeatCountDelayed add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCountDelayed
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST

20
pipelined/src/ebu/ahbmultimanager.sv → pipelined/src/ebu/ahbmulticontroller.sv
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@ -1,11 +1,11 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// abhmultimanager // abhmulticontroller
// //
// Written: Ross Thompson August 29, 2022 // Written: Ross Thompson August 29, 2022
// ross1728@gmail.com // ross1728@gmail.com
// Modified: // Modified:
// //
// Purpose: AHB multi manager interface to merge LSU and IFU controls. // Purpose: AHB multi controller interface to merge LSU and IFU controls.
// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0 // See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
// Arbitrates requests from instruction and data streams // Arbitrates requests from instruction and data streams
// Connects core to peripherals and I/O pins on SOC // Connects core to peripherals and I/O pins on SOC
@ -36,7 +36,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbmultimanager module ahbmulticontroller
( (
input logic clk, reset, input logic clk, reset,
// Signals from IFU // Signals from IFU
@ -110,20 +110,20 @@ module ahbmultimanager
// inputs. Abritration scheme is LSU always goes first. // inputs. Abritration scheme is LSU always goes first.
// input stage IFU // input stage IFU
managerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]), controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
.Request(IFUReq), .Active(IFUActive), .Request(IFUReq), .Active(IFUActive),
.HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR), .HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY)); .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
// input stage LSU // input stage LSU
managerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]), controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
.Request(LSUReq), .Active(LSUActive), .Request(LSUReq), .Active(LSUActive),
.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY)); .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY));
// output mux //*** rewrite for general number of managers. // output mux //*** rewrite for general number of controllers.
assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0; assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0;
assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits
assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
@ -135,7 +135,7 @@ module ahbmultimanager
// data phase muxing. This would be a mux if IFU wrote data. // data phase muxing. This would be a mux if IFU wrote data.
assign HWDATA = LSUHWDATA; assign HWDATA = LSUHWDATA;
assign HWSTRB = LSUHWSTRB; assign HWSTRB = LSUHWSTRB;
// HRDATA is sent to all managers at the core level. // HRDATA is sent to all controllers at the core level.
// FSM decides if arbitration needed. Arbitration is held until the last beat of // FSM decides if arbitration needed. Arbitration is held until the last beat of
// a burst is completed. // a burst is completed.
@ -151,7 +151,7 @@ module ahbmultimanager
endcase endcase
// This part is only used when burst mode is supported. // This part is only used when burst mode is supported.
// Manager needs to count beats. // Controller needs to count beats.
flopenr #(4) flopenr #(4)
BeatCountReg(.clk(HCLK), BeatCountReg(.clk(HCLK),
.reset(~HRESETn | CntReset | FinalBeat), .reset(~HRESETn | CntReset | FinalBeat),
@ -190,12 +190,12 @@ module ahbmultimanager
// basic arb always selects LSU when both // basic arb always selects LSU when both
// replace this block for more sophisticated arbitration as needed. // replace this block for more sophisticated arbitration as needed.
// Manager 0 (IFU) // Controller 0 (IFU)
assign save[0] = CurrState == IDLE & both; assign save[0] = CurrState == IDLE & both;
assign restore[0] = CurrState == ARBITRATE; assign restore[0] = CurrState == ARBITRATE;
assign dis[0] = CurrState == ARBITRATE; assign dis[0] = CurrState == ARBITRATE;
assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq; assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
// Manager 1 (LSU) // Controller 1 (LSU)
assign save[1] = 1'b0; assign save[1] = 1'b0;
assign restore[1] = 1'b0; assign restore[1] = 1'b0;
assign dis[1] = 1'b0; assign dis[1] = 1'b0;

10
pipelined/src/ebu/managerinputstage.sv → pipelined/src/ebu/controllerinputstage.sv
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@ -1,11 +1,11 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// manager input stage // controller input stage
// //
// Written: Ross Thompson August 31, 2022 // Written: Ross Thompson August 31, 2022
// ross1728@gmail.com // ross1728@gmail.com
// Modified: // Modified:
// //
// Purpose: AHB multi manager interface to merge LSU and IFU controls. // Purpose: AHB multi controller interface to merge LSU and IFU controls.
// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0 // See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
// Arbitrates requests from instruction and data streams // Arbitrates requests from instruction and data streams
// Connects core to peripherals and I/O pins on SOC // Connects core to peripherals and I/O pins on SOC
@ -36,19 +36,19 @@
`include "wally-config.vh" `include "wally-config.vh"
module managerinputstage module controllerinputstage
(input logic HCLK, (input logic HCLK,
input logic HRESETn, input logic HRESETn,
input logic Save, Restore, Disable, input logic Save, Restore, Disable,
output logic Request, Active, output logic Request, Active,
// manager input // controller input
input logic HWRITEin, input logic HWRITEin,
input logic [2:0] HSIZEin, input logic [2:0] HSIZEin,
input logic [2:0] HBURSTin, input logic [2:0] HBURSTin,
input logic [1:0] HTRANSin, input logic [1:0] HTRANSin,
input logic [`PA_BITS-1:0] HADDRin, input logic [`PA_BITS-1:0] HADDRin,
output logic HREADYOut, output logic HREADYOut,
// manager output // controller output
output logic HWRITEOut, output logic HWRITEOut,
output logic [2:0] HSIZEOut, output logic [2:0] HSIZEOut,
output logic [2:0] HBURSTOut, output logic [2:0] HBURSTOut,

2
pipelined/src/wally/wallypipelinedcore.sv
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@ -288,7 +288,7 @@ module wallypipelinedcore (
// *** Ross: please make EBU conditional when only supporting internal memories // *** Ross: please make EBU conditional when only supporting internal memories
if(`BUS) begin : ebu if(`BUS) begin : ebu
ahbmultimanager ebu(// IFU connections ahbmulticontroller ebu(// IFU connections
.clk, .reset, .clk, .reset,
// IFU interface // IFU interface
.IFUHADDR, .IFUHADDR,