diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile new file mode 100644 index 000000000..4d0efe20e --- /dev/null +++ b/examples/fp/fpcalc/Makefile @@ -0,0 +1,23 @@ +# Makefile + +CC = gcc +CFLAGS = -O3 +LIBS = -lm +LFLAGS = -L. +# Link against the riscv-isa-sim version of SoftFloat rather than +# the regular version to get RISC-V NaN behavior +IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat +LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a +#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/ +#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a +SRCS = $(wildcard *.c) + +PROGS = $(patsubst %.c,%,$(SRCS)) + +all: $(PROGS) + +%: %.c + $(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS) + +clean: + rm -f $(PROGS) diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index 116cf8680..b8e180bf7 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -93,8 +93,13 @@ void printF32(char *msg, float32_t f) { else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-127); //printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); - printf ("%s: 0x%08x = %g = %s: Biased Exp %d Fract 0x%lx\n", - msg, conv.v, conv.f, sci, exp, fract); + printf("%s: ", msg); + printf("0x%04x", (conv.v >> 16)); + printf("_"); + printf("%04x", (conv.v & 0xFF)); + printf(" = %g = %s: Biased Exp %d Fract 0x%lx\n", conv.f, sci, exp, fract); + //printf ("%s: 0x%08x = %g = %s: Biased Exp %d Fract 0x%lx\n", + // msg, conv.v, conv.f, sci, exp, fract); } void printF64(char *msg, float64_t f) { @@ -118,8 +123,17 @@ void printF64(char *msg, float64_t f) { else sprintf(sci, "%c1.%s x 2^%d", sign, fractstr, exp-1023); //printf ("%s: 0x%016lx = %lg\n", msg, conv.v, conv.d); - printf ("%s: 0x%016lx = %lg = %s: Biased Exp %d Fract 0x%lx\n", - msg, conv.v, conv.d, sci, exp, fract); + printf("%s: ", msg); + printf("0x%04x", (conv.v >> 48)); + printf("_"); + printf("%04x", (conv.v >> 32) & 0xFFFF); + printf("_"); + printf("%04x", (conv.v >> 16)); + printf("_"); + printf("%04x", (conv.v & 0xFFFF)); + printf(" = %lg = %s: Biased Exp %d Fract 0x%lx\n", conv.d, sci, exp, fract); + //printf ("%s: 0x%016lx = %lg = %s: Biased Exp %d Fract 0x%lx\n", + // msg, conv.v, conv.d, sci, exp, fract); } void printFlags(void) { diff --git a/examples/fp/softfloat_demo/softfloat_demo.c b/examples/fp/softfloat_demo/softfloat_demo.c index 0f34ac255..111847a4f 100644 --- a/examples/fp/softfloat_demo/softfloat_demo.c +++ b/examples/fp/softfloat_demo/softfloat_demo.c @@ -12,10 +12,17 @@ typedef union sp { float f; } sp; -void printF32(char *msg, float32_t f) { +void printF32 (char *msg, float32_t f) { sp conv; + int i, j; conv.v = f.v; // use union to convert between hexadecimal and floating-point views - printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); + // Print out nicely + printf("%s: ", msg); + printf("0x%04x", (conv.v >> 16)); + printf("_"); + printf("%04x", (conv.v & 0xFFFF)); + printf(" = %g\n", conv.f); + //printf ("%s: 0x%08x = %g\n", msg, conv.v, conv.f); } void printFlags(void) { diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 834314262..0dd6ea1b2 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -173,10 +173,10 @@ module fpu ( mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); - // unpacking unit + // unpack unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpacking unpacking (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, + unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv index 78a4d7446..f503e47be 100644 --- a/pipelined/src/fpu/unpacking.sv +++ b/pipelined/src/fpu/unpacking.sv @@ -1,6 +1,6 @@ `include "wally-config.vh" -module unpacking ( +module unpack ( input logic [63:0] X, Y, Z, input logic FmtE, input logic [2:0] FOpCtrlE, diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index aa43a5b19..52c0dc208 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -86,17 +86,17 @@ module datapath ( logic [`XLEN-1:0] WriteDataE; // Memory stage signals logic [`XLEN-1:0] IEUResultM; - logic [`XLEN-1:0] ResultM; + logic [`XLEN-1:0] IFResultM; // Writeback stage signals logic [`XLEN-1:0] SCResultW; - logic [`XLEN-1:0] WriteDataW; logic [`XLEN-1:0] ResultW; + logic [`XLEN-1:0] IFResultW; // Decode stage assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; - regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, WriteDataW, R1D, R2D); + regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD); // Execute stage pipeline register and logic @@ -107,8 +107,8 @@ module datapath ( flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); - mux3 #(`XLEN) faemux(R1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE); - mux3 #(`XLEN) fbemux(R2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE); + mux3 #(`XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE); + mux3 #(`XLEN) fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE); comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE); @@ -123,17 +123,17 @@ module datapath ( flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); // Writeback stage pipeline register and logic - flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW); + flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW); flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW); flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW); - mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW); + mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); // floating point interactions: fcvt, fp stores if (`F_SUPPORTED) begin:fpmux - mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM); + mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); end else begin:fpmux - assign ResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE; + assign IFResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE; end // handle Store Conditional result if atomic extension supported diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 5cb96ba5e..5464f4ac6 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -37,6 +37,7 @@ module adrdecs ( input logic [1:0] Size, output logic [8:0] SelRegions ); + logic [3:0] clintaccesssize; // Determine which region of physical memory (if any) is being accessed // *** eventually uncomment Access signals @@ -44,11 +45,12 @@ module adrdecs ( adrdec boottimdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, /*1'b1*/AccessRX, Size, 4'b1111, SelRegions[6]); adrdec timdec(PhysicalAddress, `RAM_BASE, `RAM_RANGE, `RAM_SUPPORTED, /*1'b1*/AccessRWX, Size, 4'b1111, SelRegions[5]); - adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, 4'b1111, SelRegions[4]); + assign clintaccesssize = (`XLEN==64) ? 4'b1000 : 4'b0100; + adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, clintaccesssize, SelRegions[4]); adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]); adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[2]); adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[1]); - adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, 4'b1100, SelRegions[0]); + adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, 4'b1100, SelRegions[0]); // *** PMA chapter says xlen only like CLINT assign SelRegions[8] = ~|(SelRegions[7:0]); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index c9cf72bdd..8b3fec51d 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -83,7 +83,7 @@ module testbench; // Unpacker // Note: BiasE will probably get taken out eventually - unpacking unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), + unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), diff --git a/pipelined/testbench/testbench-f64.sv b/pipelined/testbench/testbench-f64.sv index e3cdc84d9..a0c7e6a31 100755 --- a/pipelined/testbench/testbench-f64.sv +++ b/pipelined/testbench/testbench-f64.sv @@ -51,7 +51,7 @@ module testbench (); integer desc3; // instantiate device under test - unpacking unpacking(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE, + unpack unpack(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); diff --git a/synthDC/Makefile b/synthDC/Makefile index aa148802d..aafadb648 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -22,11 +22,10 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(has export SAIFPOWER ?= 0 CONFIGDIR ?= ~/riscv-wally/pipelined/config -#CONFIGS ?= $(shell find $(CONFIGDIR) -name "rv*") -CONFIGS ?= ("rv32e", "rv32ic") - +CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) +CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) print: - echo "files in $(CONFIGDIR) are $(CONFIGS)." + echo $(CONFIGFILESTRIM) default: @echo "Basic synthesis procedure for Wally:" @@ -38,22 +37,64 @@ test: rv% rv%.log: rv% echo $< -flavors: - rm -rf $(CONFIGDIR)/rv32em - cp -r $(CONFIGDIR)/rv32e $(CONFIGDIR)/rv32em - sed -i 's/h00000010/h00001010/' $(CONFIGDIR)/rv32em/wally-config.vh - # rv32e, 32ic, 32gc 64ic, 64gc - # 64gc - FPU - # PMP16 - # PMP0 - # No virtual memory - # Muldiv - -allsynth: - make flavors - make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky90 FREQ=500 MAXCORES=1 - make synth DESIGN=wallypipelinedcore CONFIG=rv32em TECH=sky90 FREQ=500 MAXCORES=1 +DIRS = rv32e rv32gc rv64ic rv64gc rv32ic +# DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic +# CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig + + +del: + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;) + @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;) + +configs: $(DIRS) +$(DIRS): + #turn off FPU + rm -rf $(CONFIGDIR)/$@_FPUoff + cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_FPUoff + sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh + sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh + + # PMP 16 + rm -rf $(CONFIGDIR)/$@_PMP16 + cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 + # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP16/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP16/wally-config.vh + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh + + # PMP 0 + rm -rf $(CONFIGDIR)/$@_PMP0 + cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 + # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_PMP0/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_PMP0/wally-config.vh + sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh + + # No Virtual Memory + rm -rf $(CONFIGDIR)/$@_noVirtMem + # cp -r $(CONFIGDIR)/$@ $(CONFIGDIR)/$@_noVirtMem + # sed -i 's/1 *<< *3/0 <_PMP0< 3/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + # sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh + + #no muldiv + rm -rf $(CONFIGDIR)/$@_noMulDiv + cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv + # sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + # sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + # sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + # sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + + +allsynth: $(CONFIGFILESTRIM) + +$(CONFIGFILESTRIM): + make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1 --jobs synth: @echo "DC Synthesis" diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py new file mode 100644 index 000000000..e9fa69772 --- /dev/null +++ b/synthDC/extractSummary.py @@ -0,0 +1,25 @@ +import glob +import re +import csv + +field_names = [ 'Name', 'Critical Path Length', 'Cell Area'] +data = [] +for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypipelinedcore_qor.rep"): + f = open(name, 'r') + # trimName = re.search("runs\/(.*?)\/reports", name).group(1) + trimName = re.search("wallypipelinedcore_(.*?)_sky9",name).group(1) + for line in f: + if "Critical Path Length" in line: + pathLen = re.search("Length: *(.*?)\\n", line).group(1) + if "Cell Area" in line: + area = re.search("Area: *(.*?)\\n", line).group(1) + data += [{'Name' : trimName, 'Critical Path Length': pathLen, 'Cell Area' : area}] + +with open('Summary.csv', 'w') as csvfile: + writer = csv.DictWriter(csvfile, fieldnames=field_names) + writer.writeheader() + writer.writerows(data) + + + + \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output index f62663131..38042cfc7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output @@ -1,6 +1,10 @@ beef00b5 -000000b6 -ffffffb7 +00000007 # write access fault with 16 bit write to CLINT +00000005 # read access fault with 16 bit write to CLINT +00000bad +00000007 # write access fault with 8 bit write to CLINT +00000005 # read access fault with 8 bit write to CLINT +00000bad 00000001 00000bad 00000002 @@ -1018,7 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S index 475a6dd83..f9dbe8d57 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S @@ -66,7 +66,7 @@ test_cases: # | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic | # | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO | -# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO | +# | CLINT | 0x2000000 | 32-bit | YES | YES | NO | NO | NO | NO | # | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO | # | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO | # | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO | @@ -82,10 +82,10 @@ test_cases: # Use timecmp register as readable and writable section of the CLINT .4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success .4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test# 16-bit write: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test# 16-bit read: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test# 08-bit write: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test# 08-bit read: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test# 16-bit write: failure *** Due to non-native access length in CLINT +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test# 16-bit read: failure +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test# 08-bit write: failure +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test# 08-bit read: failure .4byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output index c8a68e8e2..036b97aea 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output @@ -1,11 +1,23 @@ beef00b4 # Test 12.3.2.1: read 64 bits success in CLINT 0000dead # all of these read successes are also confirming successful writes -beef00b5 # read 32 bits success in CLINT (sign extended) -ffffffff -000000b6 # read 16 bits success in CLINT +00000007 # write 32 bits with access fault in CLINT +00000000 +00000005 # read 32 bits with access fault in CLINT +00000000 +00000bad +00000000 +00000007 # write 16 bits with access fault in CLINT +00000000 +00000005 # read 16 bits with access fault in CLINT +00000000 +00000bad +00000000 +00000007 # write 8 bits with access fault in CLINT +00000000 +00000005 # read 8 bits with access fault in CLINT +00000000 +00000bad 00000000 -ffffffb7 # read 8 bits success in CLINT (sign extended) -ffffffff 00000001 # execute test with access fault in CLINT 00000000 00000bad @@ -1010,15 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S index 7780e187f..3dd6a91c7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S @@ -69,7 +69,7 @@ test_cases: # | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic | # | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO | -# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO | +# | CLINT | 0x2000000 | 64-bit | YES | YES | NO | NO | NO | NO | # | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO | # | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO | # | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO | @@ -85,12 +85,12 @@ test_cases: # Use timecmp register as readable and writable section of the CLINT .8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, write64_test # 64-bit write: success .8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B4, read64_test # 64-bit read: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, write32_test # 32-bit write: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, read32_test # 32-bit read: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, write16_test # 16-bit write: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, read16_test # 16-bit read: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, write08_test # 08-bit write: success -.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, read08_test # 08-bit read: success +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, write32_test # 32-bit write: failure *** due to non-native length access +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B5, read32_test # 32-bit read: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, write16_test # 16-bit write: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B6, read16_test # 16-bit read: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, write08_test # 08-bit write: failure +.8byte CLINT_BASE + 0x4000, 0x0000DEADBEEF00B7, read08_test # 08-bit read: failure .8byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault