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soc/src: Fix small FIFO bugs, correct DDR paramaterization

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Marcus Mellor 2024-03-06 16:12:03 -06:00
parent 56b3192188
commit ce25816e44
3 changed files with 117 additions and 118 deletions
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96
soc/src/bsg_dmc_ahb.sv
View File

@ -32,41 +32,39 @@ module bsg_dmc_ahb
import bsg_tag_pkg::*; import bsg_tag_pkg::*;
import bsg_dmc_pkg::*; import bsg_dmc_pkg::*;
#( #(
parameter ADDR_SIZE = 28, parameter AHB_ADDR_SIZE = 28,
parameter DATA_SIZE = 64, parameter AHB_DATA_SIZE = 64,
parameter BURST_LENGTH = 8, parameter DDR_DATA_SIZE = 32,
parameter FIFO_DEPTH = 4, parameter BURST_LENGTH = 8,
parameter FIFO_DEPTH = 4
) ( ) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic HSEL, input logic HSEL,
input logic [ADDR_SIZE-1:0] HADDR, input logic [AHB_ADDR_SIZE-1:0] HADDR,
input logic [DATA_SIZE-1:0] HWDATA, input logic [AHB_DATA_SIZE-1:0] HWDATA,
input logic [DATA_SIZE/8-1:0] HWSTRB, input logic [AHB_DATA_SIZE/8-1:0] HWSTRB,
input logic HWRITE, input logic HWRITE,
input logic [1:0] HTRANS, input logic [1:0] HTRANS,
input logic HREADY, input logic HREADY,
output logic [DATA_SIZE-1:0] HRDATA, output logic [AHB_DATA_SIZE-1:0] HRDATA,
output logic HRESP, HREADYOUT, output logic HRESP, HREADYOUT,
//input logic ui_clk // Add this once PLL is integrated //input logic ui_clk, // Add this once PLL is integrated
output logic ddr_ck_p, ddr_ck_n, ddr_cke, output logic ddr_ck_p, ddr_ck_n, ddr_cke,
output logic [2:0] ddr_ba, output logic [2:0] ddr_ba,
output logic [15:0] ddr_addr, output logic [13:0] ddr_addr,
output logic ddr_cs, ddr_ras, ddr_cas, output logic ddr_cs, ddr_ras, ddr_cas,
output logic ddr_we, ddr_reset, ddr_odt, output logic ddr_we, ddr_reset, ddr_odt,
output logic [DATA_SIZE/16-1:0] ddr_dm_oen, ddr_dm, output logic [DDR_DATA_SIZE/8-1:0] ddr_dm_oen, ddr_dm,
output logic [DATA_SIZE/16-1:0] ddr_dqs_p_oen, ddr_dqs_p_ien, ddr_dqs_p_out, output logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_p_oen, ddr_dqs_p_ien, ddr_dqs_p_out,
input logic [DATA_SIZE/16-1:0] ddr_dqs_p_in, input logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_p_in,
output logic [DATA_SIZE/16-1:0] ddr_dqs_n_oen, ddr_dqs_n_ien, ddr_dqs_n_out, output logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_n_oen, ddr_dqs_n_ien, ddr_dqs_n_out,
input logic [DATA_SIZE/16-1:0] ddr_dqs_n_in, input logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_n_in,
output logic [DATA_SIZE/2-1:0] ddr_dq_oen, ddr_dq_out, output logic [DDR_DATA_SIZE-1:0] ddr_dq_oen, ddr_dq_out,
input logic [DATA_SIZE/2-1:0] ddr_dq_in, input logic [DDR_DATA_SIZE-1:0] ddr_dq_in,
input logic dfi_clk_2x, input logic dfi_clk_2x,
output logic dfi_clk_1x output logic dfi_clk_1x
); );
localparam BURST_DATA_SIZE = DATA_SIZE * BURST_LENGTH;
// localparam DQ_DATA_SIZE = DATA_SIZE >> 1;
// Global async reset // Global async reset
logic sys_reset; logic sys_reset;
@ -76,18 +74,18 @@ module bsg_dmc_ahb
bsg_dmc_s dmc_config; bsg_dmc_s dmc_config;
// UI signals // UI signals
logic ui_clk_sync_rst; logic ui_clk_sync_rst;
logic [ADDR_SIZE-1:0] app_addr; logic [AHB_ADDR_SIZE-1:0] app_addr;
logic [2:0] app_cmd; logic [2:0] app_cmd;
logic app_en, app_rdy, app_wdf_wren; logic app_en, app_rdy, app_wdf_wren;
logic [DATA_SIZE-1:0] app_wdf_data; logic [AHB_DATA_SIZE-1:0] app_wdf_data;
logic [DATA_SIZE/8-1:0] app_wdf_mask; logic [AHB_DATA_SIZE/8-1:0] app_wdf_mask;
logic app_wdf_end, app_wdf_rdy; logic app_wdf_end, app_wdf_rdy;
logic [DATA_SIZE-1:0] app_rd_data; logic [AHB_DATA_SIZE-1:0] app_rd_data;
logic app_rd_data_end, app_rd_data_valid; logic app_rd_data_end, app_rd_data_valid;
logic app_ref_ack, app_zq_ack, app_sr_active; // Sink unused UI signals logic app_ref_ack, app_zq_ack, app_sr_active; // Sink unused UI signals
logic init_calib_complete; logic init_calib_complete;
logic [11:0] device_temp; // Reserved logic [11:0] device_temp; // Reserved
// Use a /6 clock divider until PLL is integrated. TODO: Replace // Use a /6 clock divider until PLL is integrated. TODO: Replace
logic ui_clk; logic ui_clk;
@ -120,7 +118,7 @@ module bsg_dmc_ahb
dmc_config.bank_pos = 25; dmc_config.bank_pos = 25;
end end
ahbxuiconverter #(ADDR_SIZE, DATA_SIZE) bsg_dmc_ahb_ui_converter ( ahbxuiconverter #(AHB_ADDR_SIZE, AHB_DATA_SIZE) bsg_dmc_ahb_ui_converter (
.HCLK, .HRESETn, .HSEL, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, .HRDATA, .HRESP, .HREADYOUT, .HCLK, .HRESETn, .HSEL, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, .HRDATA, .HRESP, .HREADYOUT,
.sys_reset, .ui_clk, .ui_clk_sync_rst, .sys_reset, .ui_clk, .ui_clk_sync_rst,
.app_addr, .app_cmd, .app_en, .app_rdy, .app_addr, .app_cmd, .app_en, .app_rdy,
@ -131,10 +129,10 @@ module bsg_dmc_ahb
bsg_dmc #( bsg_dmc #(
.num_adgs_p(1), .num_adgs_p(1),
.ui_addr_width_p(ADDR_SIZE), .ui_addr_width_p(AHB_ADDR_SIZE),
.ui_data_width_p(DATA_SIZE), .ui_data_width_p(AHB_DATA_SIZE),
.burst_data_width_p(BURST_DATA_SIZE), .burst_data_width_p(AHB_DATA_SIZE * BURST_LENGTH),
.dq_data_width_p(DATA_SIZE/2), .dq_data_width_p(DDR_DATA_SIZE),
.cmd_afifo_depth_p(FIFO_DEPTH), .cmd_afifo_depth_p(FIFO_DEPTH),
.cmd_sfifo_depth_p(FIFO_DEPTH) .cmd_sfifo_depth_p(FIFO_DEPTH)
) dmc ( ) dmc (

67
soc/src/fifo/rptr_empty.sv
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@ -2,7 +2,7 @@
// rptr_empty.sv // rptr_empty.sv
// //
// Written: Clifford E Cummings 16 June 2005 // Written: Clifford E Cummings 16 June 2005
// Modified: james.stine@okstate.edu 19 February 2024 // Modified: infinitymdm@gmail.com 5 March 2024
// //
// Purpose: FIFO read pointer and empty generation logic // Purpose: FIFO read pointer and empty generation logic
// //
@ -27,39 +27,40 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module rptr_empty #(parameter ADDRSIZE = 4) module rptr_empty #(parameter ADDRSIZE = 4)
(rempty, raddr, rptr, rq2_wptr, rinc, rclk, rrst_n); (rempty, raddr, rptr, rq2_wptr, rinc, rclk, rrst_n);
input logic [ADDRSIZE:0] rq2_wptr; input logic [ADDRSIZE:0] rq2_wptr;
input logic rinc; input logic rinc;
input logic rclk; input logic rclk;
input logic rrst_n; input logic rrst_n;
output logic rempty; output logic rempty;
output logic [ADDRSIZE-1:0] raddr; output logic [ADDRSIZE-1:0] raddr;
output logic [ADDRSIZE :0] rptr; output logic [ADDRSIZE :0] rptr;
logic [ADDRSIZE:0] rbin; logic rempty_val;
logic [ADDRSIZE:0] rgraynext; logic [ADDRSIZE:0] rbin;
logic [ADDRSIZE:0] rbinnext; logic [ADDRSIZE:0] rgraynext;
logic [ADDRSIZE:0] rbinnext;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
assign rempty_val = (rgraynext == rq2_wptr);
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) rempty <= 1'b1;
else rempty <= rempty_val;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
assign rempty_val = (rgraynext == rq2_wptr);
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) rempty <= 1'b1;
else rempty <= rempty_val;
endmodule // rptr_empty endmodule // rptr_empty

72
soc/src/fifo/wptr_full.sv
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@ -2,7 +2,7 @@
// wptr_full.sv // wptr_full.sv
// //
// Written: Clifford E Cummings 16 June 2005 // Written: Clifford E Cummings 16 June 2005
// Modified: james.stine@okstate.edu 19 February 2024 // Modified: infinitymdm@gmail.com 5 March 2024
// //
// Purpose: FIFO write pointer and full generation logic // Purpose: FIFO write pointer and full generation logic
// //
@ -27,45 +27,45 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module wptr_full #(parameter ADDRSIZE = 4) module wptr_full #(parameter ADDRSIZE = 4)
(wfull, waddr, wptr, wq2_rptr, winc, wclk, wrst_n); (wfull, waddr, wptr, wq2_rptr, winc, wclk, wrst_n);
input logic [ADDRSIZE :0] wq2_rptr; input logic [ADDRSIZE:0] wq2_rptr;
input logic winc; input logic winc;
input logic wclk; input logic wclk;
input logic wrst_n; input logic wrst_n;
output logic wfull;
output logic wfull; output logic [ADDRSIZE-1:0] waddr;
output logic [ADDRSIZE-1:0] waddr; output logic [ADDRSIZE:0] wptr;
output logic [ADDRSIZE:0] wptr;
logic [ADDRSIZE:0] wbin;
logic [ADDRSIZE:0] wgraynext;
logic [ADDRSIZE:0] wbinnext;
// GRAYSTYLE2 pointer logic wfull_val;
always @(posedge wclk or negedge wrst_n) logic [ADDRSIZE:0] wbin;
if (!wrst_n) {wbin, wptr} <= 0; logic [ADDRSIZE:0] wgraynext;
else {wbin, wptr} <= {wbinnext, wgraynext}; logic [ADDRSIZE:0] wbinnext;
// Memory write-address pointer (okay to use binary to address memory) // GRAYSTYLE2 pointer
assign waddr = wbin[ADDRSIZE-1:0]; always @(posedge wclk or negedge wrst_n)
assign wbinnext = wbin + (winc & ~wfull); if (!wrst_n) {wbin, wptr} <= 0;
assign wgraynext = (wbinnext>>1) ^ wbinnext; else {wbin, wptr} <= {wbinnext, wgraynext};
//------------------------------------------------------------------ // Memory write-address pointer (okay to use binary to address memory)
// Simplified version of the three necessary full-tests: assign waddr = wbin[ADDRSIZE-1:0];
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && assign wbinnext = wbin + (winc & ~wfull);
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && assign wgraynext = (wbinnext>>1) ^ wbinnext;
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------ //------------------------------------------------------------------
assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1], // Simplified version of the three necessary full-tests:
wq2_rptr[ADDRSIZE-2:0]}); // assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
always @(posedge wclk or negedge wrst_n) // (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
if (!wrst_n) //------------------------------------------------------------------
wfull <= 1'b0; assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1],
else wq2_rptr[ADDRSIZE-2:0]});
wfull <= wfull_val;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n)
wfull <= 1'b0;
else
wfull <= wfull_val;
endmodule // wptr_full endmodule // wptr_full