Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401
+Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca

bin/lint-wally

@@ -30,7 +30,7 @@ for config in ${configs[@]}; do
     if !($verilator --lint-only --quiet --top-module wallywrapper \
          "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \
          $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \
-         -Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
+         -Wall -Wno-UNUSEDSIGNAL -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
         if [ "$1" == "-nightly" ]; then
             echo -e "${RED}$config failed lint${NC}"
             fails=$((fails+1))

bin/regression-wally

@@ -439,6 +439,7 @@ else:
 if (args.nightly):
     addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0)
     addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0)
+    addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0)
     addTests(derivconfigtests, defaultsim)
     # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.
 

config/rv32gc/coverage.svh

@@ -33,5 +33,6 @@
 // Privileged extensions
 `include "ZicsrM_coverage.svh"
 `include "ZicsrF_coverage.svh"
+`include "ZicsrU_coverage.svh"
 `include "RV32VM_coverage.svh"
 `include "RV32VM_PMP_coverage.svh"

config/rv64gc/coverage.svh

@@ -34,6 +34,7 @@
 `include "RV64VM_coverage.svh"
 `include "ZicsrM_coverage.svh"
 `include "ZicsrF_coverage.svh"
+`include "ZicsrU_coverage.svh"
 // `include "RV64VM_PMP_coverage.svh"
 // `include "RV64CBO_VM_coverage.svh"
 // `include "RV64CBO_PMP_coverage.svh"

config/shared/config-shared.vh

@@ -122,9 +122,3 @@ localparam FMALEN = 3*NF + 6;
 localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
 
 localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));                  // log_2(NORMSHIFTSZ)
-
-// Disable spurious Verilator warnings
-
-/* verilator lint_off STMTDLY */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */

config/shared/parameter-defs.vh

@@ -95,11 +95,7 @@ localparam cvw_t P = '{
   PLIC_SPI_ID :        PLIC_SPI_ID,
   PLIC_SDC_ID :        PLIC_SDC_ID,
   BPRED_SUPPORTED :        BPRED_SUPPORTED,
-                       /* verilator lint_off ENUMVALUE */
-                       // *** definitely need to fix this.
-                       // it thinks we are casting from the enum type to BPRED_TYPE.
   BPRED_TYPE :        BPRED_TYPE,
-                       /* verilator lint_on ENUMVALUE */
   BPRED_SIZE :        BPRED_SIZE,
   BPRED_NUM_LHR : BPRED_NUM_LHR,                       
   BTB_SIZE :        BTB_SIZE,

src/cache/cache.sv

@@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module cache import cvw::*; #(parameter cvw_t P,
-                              parameter PA_BITS, XLEN, LINELEN,  NUMSETS,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
+                              parameter PA_BITS, LINELEN,  NUMSETS,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
   input  logic                   clk,
   input  logic                   reset,
   input  logic                   Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
@@ -66,11 +66,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   localparam                     SETLEN = $clog2(NUMSETS);          // Number of set bits
   localparam                     SETTOP = SETLEN+OFFSETLEN;          // Number of set plus offset bits
   localparam                     TAGLEN = PA_BITS - SETTOP;          // Number of tag bits
-  localparam                     CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
-  localparam                     LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
   localparam                     FLUSHADRTHRESHOLD = NUMSETS - 1;   // Used to determine when flush is complete
-  localparam                     LOGLLENBYTES = $clog2(WORDLEN/8);   // Number of bits to address a word
-
 
   logic                          SelAdrData;
   logic                          SelAdrTag;
@@ -122,14 +118,14 @@ module cache import cvw::*; #(parameter cvw_t P,
     AdrSelMuxSelLRU, CacheSetLRU);
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
-  cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
+  cacheway #(P, PA_BITS, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim,
     .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
     .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
 
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
-    cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU(
+    cacheLRU #(NUMWAYS, SETLEN, NUMSETS) cacheLRU(
       .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn,
       .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
   end else 
@@ -173,10 +169,6 @@ module cache import cvw::*; #(parameter cvw_t P,
     logic [LINELEN/8-1:0]          DemuxedByteMask, FetchBufferByteSel;
 
     // Adjust byte mask from word to cache line    
-
-    localparam                     CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line
-    localparam                     LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^
-    
     logic [LINELEN/8-1:0]          BlankByteMask;
     assign BlankByteMask[WORDLEN/8-1:0] = ByteMask;
     assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0;
@@ -231,7 +223,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   // Cache FSM
   /////////////////////////////////////////////////////////////////////////////////////////////
   
-  cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
+  cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
     .FlushStage, .CacheRW, .Stall,
     .Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, 
     .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim,

src/cache/cacheLRU.sv

@@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module cacheLRU
-  #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMSETS = 128) (
+  #(parameter NUMWAYS = 4, SETLEN = 9, NUMSETS = 128) (
   input  logic                clk, 
   input  logic                reset,
   input  logic                FlushStage,

src/cache/cachefsm.sv

@@ -28,8 +28,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module cachefsm import cvw::*; #(parameter cvw_t P,
+module cachefsm #(parameter READ_ONLY_CACHE = 0) (
-                                 parameter READ_ONLY_CACHE = 0) (
   input  logic       clk,
   input  logic       reset,
   // hazard and privilege unit

src/cache/cacheway.sv

@@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module cacheway import cvw::*; #(parameter cvw_t P, 
-                  parameter PA_BITS, XLEN, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
+                  parameter PA_BITS, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
                   OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
   input  logic                        clk,
   input  logic                        reset,
@@ -57,12 +57,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   output logic                        DirtyWay   ,    // The selected way is dirty
   output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
 
-  localparam                          WORDSPERLINE = LINELEN/XLEN;
-  localparam                          BYTESPERLINE = LINELEN/8;
-  localparam                          LOGWPL = $clog2(WORDSPERLINE);
-  localparam                          LOGXLENBYTES = $clog2(XLEN/8);
-  localparam                          BYTESPERWORD = XLEN/8;
-
   logic [NUMSETS-1:0]                ValidBits;
   logic [NUMSETS-1:0]                DirtyBits;
   logic [LINELEN-1:0]                 ReadDataLine;
@@ -131,7 +125,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
 
   localparam           NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
   localparam           SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
-  localparam           LOGNUMSRAM = $clog2(NUMSRAM);
   
   for(words = 0; words < NUMSRAM; words++) begin: word
     if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$.

src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -38,7 +38,6 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   output logic [P.DIVb+3:0] FirstWS, FirstWC       // Q4.DIVb
 );
 
-  /* verilator lint_off UNOPTFLAT */
   logic [P.DIVb+3:0]      WSNext[P.DIVCOPIES-1:0]; // Q4.DIVb
   logic [P.DIVb+3:0]      WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb
   logic [P.DIVb+3:0]      WS[P.DIVCOPIES:0];       // Q4.DIVb
@@ -56,7 +55,6 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   logic [P.DIVb+1:0]      NextC;                   // Q2.DIVb
   logic [P.DIVb:0]        UMux, UMMux;             // U1.DIVb
   logic [P.DIVb:0]        initU, initUM;           // U1.DIVb
-  /* verilator lint_on UNOPTFLAT */
 
   // Top Muxes and Registers
   // When start is asserted, the inputs are loaded into the divider.

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -136,7 +136,7 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
     // calculate right shift amount RightShiftX to complete in discrete number of steps
     if (P.RK > 1) begin // more than 1 bit per cycle
       logic [$clog2(P.RK)-1:0] RightShiftX;
-      /* verilator lint_offf WIDTH */
+      /* verilator lint_off WIDTH */
       assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount
       assign DivXShifted = DivX >> RightShiftX;                     // shift X by up to R*K-1 to complete in n steps
       /* verilator lint_on WIDTH */

src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -28,7 +28,6 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 
-/* verilator lint_off UNOPTFLAT */
 module fdivsqrtstage2 import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.DIVb+3:0] D, DBar,        // Q4.DIVb
   input  logic [P.DIVb:0]   U, UM,          // U1.DIVb
@@ -40,7 +39,6 @@ module fdivsqrtstage2 import cvw::*;  #(parameter cvw_t P) (
   output logic [P.DIVb:0]   UNext, UMNext,  // U1.DIVb
   output logic [P.DIVb+3:0] WSNext, WCNext  // Q4.DIVb
 );
- /* verilator lint_on UNOPTFLAT */
 
   logic [P.DIVb+3:0]        Dsel;     // Q4.DIVb
   logic                     up, uz;

src/fpu/fround.sv

@@ -115,9 +115,9 @@ module fround import cvw::*;  #(parameter cvw_t P) (
   ///////////////////////////
 
   // Exact logic
-  // verilator lint_off WIDTHEXPAND
+  /* verilator lint_off WIDTHEXPAND */
   assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf.  Also check that Xe is positive to avoid wraparound problems
-  // verilator lint_on WIDTHEXPAND
+  /* verilator lint_on WIDTHEXPAND */
 
   // Rounding logic: determine whether to round up in magnitude
   always_comb begin

src/generic/prioritythermometer.sv

@@ -39,11 +39,9 @@ module prioritythermometer #(parameter N = 8) (
   //  Rather than linear.
 
   // create thermometer code mask
-  /* verilator lint_off UNOPTFLAT */
   genvar i;
   assign y[0] = ~a[0];
   for (i=1; i<N; i++) begin:therm
     assign y[i] = y[i-1] & ~a[i];
   end
-  /* verilator lint_on UNOPTFLAT */
 endmodule

src/hazard/hazard.sv

@@ -27,7 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module hazard import cvw::*;  #(parameter cvw_t P) ( 
+module hazard ( 
   input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
   input  logic  StructuralStallD,
   input  logic  LSUStallM, IFUStallF,

src/ifu/ifu.sv

@@ -236,7 +236,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
       
       assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
       assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
-      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.ICACHE_LINELENINBITS),
               .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
               .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
       icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),

src/lsu/lsu.sv

@@ -121,11 +121,9 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic                  DCacheCommittedM;                       // D$ memory operation started, delay interrupts
 
   logic [P.LLEN-1:0]     DTIMReadDataWordM;                      // DTIM read data
-  /* verilator lint_off WIDTHEXPAND */  
   logic [MLEN-1:0]       DCacheReadDataWordM;                    // D$ read data
   logic [MLEN-1:0]       LSUWriteDataSpillM;                     // Final write data
   logic [MLEN/8-1:0]     ByteMaskSpillM;                         // Selects which bytes within a word to write
-  /* verilator lint_on WIDTHEXPAND */
   logic [P.LLEN-1:0]     DCacheReadDataWordSpillM;               // D$ read data
   logic [P.LLEN-1:0]     ReadDataWordMuxM;                       // DTIM or D$ read data
   logic [P.LLEN-1:0]     LittleEndianReadDataWordM;              // Endian-swapped read data
@@ -326,7 +324,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0;
       assign FlushDCache = FlushDCacheM & ~(SelHPTW);
       
-      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
         .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW),
         .CacheRW(CacheRWM), 

src/mdu/divstep.sv

@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-/* verilator lint_off UNOPTFLAT */
-
 module divstep #(parameter XLEN) (
   input  logic [XLEN-1:0] W,     // Residual in
   input  logic [XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
@@ -46,5 +44,3 @@ module divstep #(parameter XLEN) (
   assign qi = ~qib;
   mux2 #(XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
 endmodule
-
-/* verilator lint_on UNOPTFLAT */

src/privileged/csrm.sv

@@ -88,6 +88,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   // .. up to 15 more at consecutive addresses
   localparam PMPADDR0      = 12'h3B0;
   // ... up to 63 more at consecutive addresses
+  /* verilator lint_off UNUSEDPARAM */
   localparam TSELECT       = 12'h7A0;
   localparam TDATA1        = 12'h7A1;
   localparam TDATA2        = 12'h7A2;
@@ -96,6 +97,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   localparam DPC           = 12'h7B1;
   localparam DSCRATCH0     = 12'h7B2;
   localparam DSCRATCH1     = 12'h7B3;
+  /* verilator lint_off UNUSEDPARAM */
   // Constants
   localparam ZERO = {(P.XLEN){1'b0}};
   // when compressed instructions are supported, there can't be misaligned instructions

src/privileged/csrs.sv

@@ -67,8 +67,6 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   localparam STIMECMPH  = 12'h15D;
   localparam SATP       = 12'h180;
   // Constants
-  localparam ZERO         = {(P.XLEN){1'b0}};
-  localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);
 
   logic                    WriteSTVECM;
   logic                    WriteSSCRATCHM, WriteSEPCM;

src/uncore/ram_ahb.sv

@@ -28,7 +28,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module ram_ahb import cvw::*;  #(parameter cvw_t P, 
-                                 parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
+                                 parameter RANGE = 65535, PRELOAD = 0) (
   input  logic                 HCLK, HRESETn, 
   input  logic                 HSELRam,
   input  logic [P.PA_BITS-1:0] HADDR,

src/uncore/rom_ahb.sv

@@ -28,7 +28,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module rom_ahb import cvw::*;  #(parameter cvw_t P, 
-                                 parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
+                                 parameter RANGE = 65535, PRELOAD = 0) (
   input  logic                 HCLK, HRESETn, 
   input  logic                 HSELRom,
   input  logic [P.PA_BITS-1:0] HADDR,

src/uncore/spi_apb.sv

@@ -114,7 +114,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
   
   /* verilator lint_off UNDRIVEN */
   logic [2:0]  TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
-  /* verilator lint_off UNDRIVEN */
+  /* verilator lint_on UNDRIVEN */
   logic [7:0]  ReceiveShiftRegEndian;              // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
 
   // Shift reg signals
@@ -184,7 +184,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
         case(Entry)
           SPI_TXDATA:  if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
         endcase
-      /* verilator lint_off CASEINCOMPLETE */
+      /* verilator lint_on CASEINCOMPLETE */
       
       // According to FU540 spec: Once interrupt is pending, it will remain set until number 
       // of entries in tx/rx fifo is strictly more/less than tx/rxmark

src/uncore/uartPC16550D.sv

@@ -335,10 +335,10 @@ module uartPC16550D #(parameter UART_PRESCALE) (
     end
 
   assign rxfifoempty = (rxfifohead == rxfifotail);
-  // verilator lint_off WIDTH
+  /* verilator lint_off WIDTH */
   assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) : 
                          (rxfifohead + 16 - rxfifotail);
-  // verilator lint_on WIDTH
+  /* verilator lint_on WIDTH */
   assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
   assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; probably not right yet
   //assign rxfifotimeout = 0; // disabled pending fix

src/uncore/uncore.sv

@@ -109,13 +109,13 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
                 
   // on-chip RAM
   if (P.UNCORE_RAM_SUPPORTED) begin : ram
-    ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
+    ram_ahb #(.P(P), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
       .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, 
       .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
   end else assign {HREADRam, HRESPRam, HREADYRam} = '0;
 
  if (P.BOOTROM_SUPPORTED) begin : bootrom
-    rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
+    rom_ahb #(.P(P), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
     bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, 
       .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
   end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0;

src/wally/wallypipelinedcore.sv

@@ -271,7 +271,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   end
 
   // global stall and flush control  
-  hazard #(P) hzu(
+  hazard hzu(
     .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
     .StructuralStallD,
     .LSUStallM, .IFUStallF,

testbench/testbench.sv

@@ -175,6 +175,7 @@ module testbench;
         "arch64zknd":    if (P.ZKND_SUPPORTED)    tests = arch64zknd;
         "arch64zkne":    if (P.ZKNE_SUPPORTED)    tests = arch64zkne;
         "arch64zknh":    if (P.ZKNH_SUPPORTED)    tests = arch64zknh;
+        "arch64pmp":     if (P.PMP_ENTRIES > 0)   tests = arch64pmp;
       endcase
     end else begin // RV32
       case (TEST)
@@ -217,6 +218,8 @@ module testbench;
         "arch32zknd":    if (P.ZKND_SUPPORTED)    tests = arch32zknd;
         "arch32zkne":    if (P.ZKNE_SUPPORTED)    tests = arch32zkne;
         "arch32zknh":    if (P.ZKNH_SUPPORTED)    tests = arch32zknh;
+        "arch32pmp":     if (P.PMP_ENTRIES > 0)   tests = arch32pmp;
+        "arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32;
       endcase
     end
     if (tests.size() == 0 & ElfFile == "none") begin
@@ -564,7 +567,7 @@ module testbench;
   assign SPIIn = 1'b0;
 
   if(P.EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
+    ram_ahb #(.P(P), .RANGE(P.EXT_MEM_RANGE))
     ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
       .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
   end else begin

testbench/tests.vh

@@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{
   "rv32i_m/privilege/src/WALLY-lrsc-01.S"
 };
 
+string arch32pmp[] = '{
+  `RISCVARCHTEST,
+  "rv32i_m/pmp32/src/pmp-CFG-reg.S",
+  "rv32i_m/pmp32/src/pmp-CSR-access.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-R.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RW.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RWX.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-RX.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-NA4-X.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-R.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RW.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RWX.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-RX.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-NAPOT-X.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-R.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RW.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RWX.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-RX.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X-priority.S",
+  "rv32i_m/pmp32/src/pmp-TOR-X.S"
+};
+
+string arch64pmp[] = '{
+  `RISCVARCHTEST,
+  "rv64i_m/pmp64/pmp64-CFG-reg.S",
+  "rv64i_m/pmp64/pmp64-CSR-access.S",
+  "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-R-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-R.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-RW.S",
+  "rv64i_m/pmp64/pmp64-NA4-RWX.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-RX.S",
+  "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NA4-X-priority.S",
+  "rv64i_m/pmp64/pmp64-NA4-X.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-R.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RW.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RWX.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-RX.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S",
+  "rv64i_m/pmp64/pmp64-NAPOT-X.S",
+  "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-R-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-R.S",
+  "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S",
+  "rv64i_m/pmp64/pmp64-TOR-RW-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-RW.S",
+  "rv64i_m/pmp64/pmp64-TOR-RWX.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-RX.S",
+  "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S",
+  "rv64i_m/pmp64/pmp64-TOR-X-priority.S",
+  "rv64i_m/pmp64/pmp64-TOR-X.S"
+};
+
+string arch32vm_sv32[] = '{
+  `RISCVARCHTEST,
+  "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S"
+};
+
 string arch64priv[] = '{
   `RISCVARCHTEST,
   "rv64i_m/privilege/src/ebreak.S",

tests/riscof/sail_cSim/riscof_sail_cSim.py

@@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate):
         ispec = utils.load_yaml(isa_yaml)['hart0']
         self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
         self.isa = 'rv' + self.xlen
-        self.sailargs = ' '
+        self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration
         self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
         if "I" in ispec["ISA"]:
             self.isa += 'i'
@@ -103,7 +103,6 @@ class sail_cSim(pluginTemplate):
 
             execute = "@cd "+testentry['work_dir']+";"
 
-#            cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
             cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
             compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
             execute+=compile_cmd+";"
@@ -117,8 +116,7 @@ class sail_cSim(pluginTemplate):
                 reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
                 execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
             else:
-                execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step  ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
-#                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
 
             cov_str = ' '
             for label in testentry['coverage_labels']:

tests/riscof/spike/spike_rv32gc_isa.yaml

@@ -26,4 +26,4 @@ hart0:
               legal:
                 - extensions[25:0] bitmask [0x000112D, 0x0000000]
               wr_illegal:
-                - Unchangedcd 
+                - Unchanged