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Merge branch 'main' of https://github.com/openhwgroup/cvw

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Jordan Carlin 2024-10-15 20:51:03 -07:00
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7
.gitmodules vendored
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@ -20,14 +20,11 @@
branch = dev
[submodule "addins/branch-predictor-simulator"]
path = addins/branch-predictor-simulator
url = https://github.com/ross144/branch-predictor-simulator
[submodule "addins/ahbsdc"]
path = addins/ahbsdc
url = https://github.com/JacobPease/ahbsdc.git
url = https://github.com/rosethompson/branch-predictor-simulator
[submodule "addins/verilog-ethernet"]
sparseCheckout = true
path = addins/verilog-ethernet
url = https://github.com/ross144/verilog-ethernet.git
url = https://github.com/rosethompson/verilog-ethernet.git
[submodule "cvw-arch-verif"]
path = addins/cvw-arch-verif
url = https://github.com/openhwgroup/cvw-arch-verif

1
addins/ahbsdc

@ -1 +0,0 @@
Subproject commit 33418c8dc11baf63e843b0d35f57d22c1e3182e3

2
bin/CModelBTBAccuracy.sh
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@ -1,7 +1,7 @@
#!/bin/bash
###########################################
## Written: ross1728@gmail.com
## Written: rose@rosethompson.net
## Created: 23 October 2023
## Modified:
##

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bin/CModelBranchAccuracy.sh
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@ -1,7 +1,7 @@
#!/bin/bash
###########################################
## Written: ross1728@gmail.com
## Written: rose@rosethompson.net
## Created: 12 March 2023
## Modified:
##

2
bin/SeparateBranch.sh
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@ -1,7 +1,7 @@
#!/bin/bash
###########################################
## Written: ross1728@gmail.com
## Written: rose@rosethompson.net
## Created: 12 March 2023
## Modified:
##

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bin/extractFunctionRadix.sh
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@ -4,7 +4,7 @@
## extractFunctionRadix.sh
##
## Written: Rose Thompson
## email: ross1728@gmail.com
## email: rose@rosethompson.net
## Created: March 1, 2021
## Modified: March 10, 2021
##

2
bin/parseHPMC.py
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@ -1,7 +1,7 @@
#!/usr/bin/env python3
###########################################
## Written: Rose Thompson ross1728@gmail.com
## Written: Rose Thompson rose@rosethompson.net
## Created: 20 September 2023
## Modified:
##

3
bin/regression-wally
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@ -233,6 +233,7 @@ bpredtests = [
# list of tests not supported by ImperasDV yet that should be waived during lockstep testing
lockstepwaivers = [
"WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV
"coverage_tlbMisaligned.elf", # Issue 976: ImperasDV bug disagrees with Wally related to misaligned pages when PBMT makes page uncachable
"WALLY-cbom-01.S_ref.elf" #, # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
]
@ -542,7 +543,7 @@ def main():
num_fail+=result.get(timeout=TIMEOUT_DUR)
except TimeoutError:
num_fail+=1
print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR))
# Coverage report
if args.ccov:

2
bin/wally-tool-chain-install.sh
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@ -2,7 +2,7 @@
###########################################
## Tool chain install script.
##
## Written: Rose Thompson ross1728@gmail.com
## Written: Rose Thompson rose@rosethompson.net
## Created: 18 January 2023
## Modified: 22 January 2023
## Modified: 23 March 2023

11
config/rv64gc/imperas.ic
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@ -57,6 +57,17 @@
#--override cpu/instret_undefined=T
#--override cpu/hpmcounter_undefined=T
--override cpu/scontext_undefined=T
--override cpu/mcontext_undefined=T
--override cpu/mnoise_undefined=T
# *** how to override other undefined registers: seed, mphmevent, mseccfg, debugger registers
#--override cpu/seed_undefined=T
#--override mhpmevent3_undefined=T
#--override cpu/mseccfg_undefined=T
#--override cpu/tselect_undefined=T
#--override cpu/tdata1_undefined=T
--override cpu/reset_address=0x80000000
--override cpu/unaligned=T # Zicclsm (should be true)

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fpga/README.md
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@ -1,46 +1,57 @@
The FPGA currently only targets the VCU118 board.
Wally supports the following boards
* Build Process
1. ArtyA7
2. vcu108
3. vcu118 (Do not recommend.)
cd generator
make
# Quick Start
* Description
## build FPGA
The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4,
axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks
and builds wally. fpga/src/fpgaTop.v is the top level which instanciates
wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic
analyzer) which provides the current instruction PCM, instrM, etc along with
a large number of debuging signals.
`cd generator
make <board name>`
* Programming the flash card
You'll need to write the linux image to the flash card. Use the convert2bin.py
script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt
file from QEMU's preload to generate the binary. Then to copy
sudo dd if=ram.bin of=<path to flash card>.
example
`make vcu108`
* Loading the FPGA
## Make flash card image
ls /dev/sd* or ls /dev/mmc* to see which flash card devices you have.
Insert the flash card into the reader and ls /dev/sd* or /dev/mmc* again. The new device is the one you want to use. Make sure you select the root device (i.e. /dev/sdb) not the partition (i.e. /dev/sdb1).
After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's
gui and open the WallyFPGA.xpr project file. Open the hardware manager under
program and debug. Open target and then program with the bit file.
`cd $WALLY/linux/sd-card`
* Test Run
This following script requires root.
Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide
status of the reset and ddr4 calibration. LED 7 should always be lit.
LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once
wally begins running.
`./flash-sd.sh -b <path to buildroot> -d <path to compiled device tree file> <flash card device>`
Next the bootloader program will copy the flash card into the DDR4 memory.
When this done the lower 5 LEDs will blink 5 times and then try to boot
the program loaded in the DDR4 memory at physical address 0x8000_0000.
example with vcu108, buildroot installed to /opt/riscv/buildroot, and the flash card is device /dev/sdc
* Connecting uart
You'll need to connect both usb cables. The first connects the FPGA programer
while the connect connects UART. UART is configured to use 57600 baud with
no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should
let you view the com port.
`./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc`
Wait until the the script completes then remove the car.
## FPGA setup
For the Arty A7 insert the PMOD daughter board into the right most slot and insert the sd card.
For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards.
Power on the boards. Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch.
The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board. Also the level sifters on the
VCU118 do not work correctly with the digilent sd PMOD board. We have a custom board which works instead.
`cd $WALLY/fpga/generator
vivado &`
open the design in the current directory WallyFPGA.xpr.
Then click "Open Target" under "PROGRAM AND DEBUG". Then Program the device.
## Connect to UART
In another terminal ls /dev/ttyUSB*. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times.
`screen /dev/ttyUSB1 115200`
Swap out the USB1 for USB0 or USB1 as needed.

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fpga/generator/wally.tcl
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@ -47,7 +47,7 @@ if {$board=="ArtyA7"} {
# read in all other rtl
add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared} [current_fileset]
# define top level

2
fpga/rvvidaemon/rvvidaemon.c
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// rvvi daemon
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: 31 May 2024
// Modified: 31 May 2024
//

2
fpga/src/fpgaTop.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fpgaTop.sv
//
// Written: ross1728@gmail.com November 17, 2021
// Written: rose@rosethompson.net November 17, 2021
// Modified:
//
// Purpose: This is a top level for the fpga's implementation of wally.

2
fpga/src/fpgaTopArtyA7.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fpgaTop.sv
//
// Written: ross1728@gmail.com November 17, 2021
// Written: rose@rosethompson.net November 17, 2021
// Modified:
//
// Purpose: This is a top level for the fpga's implementation of wally.

2
fpga/src/wallypipelinedsocwrapper.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// wallypipelinedsocwrapper.sv
//
// Written: Rose Thompson ross1728@gmail.com 16 June 2023
// Written: Rose Thompson rose@rosethompson.net 16 June 2023
// Modified:
//
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,

102
fpga/zsbl/bios.S Normal file
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@ -0,0 +1,102 @@
#include "system.h"
PERIOD = (SYSTEMCLOCK / 2)
.section .init
.global _start
.type _start, @function
_start:
# Initialize global pointer
.option push
.option norelax
1:auipc gp, %pcrel_hi(__global_pointer$)
addi gp, gp, %pcrel_lo(1b)
.option pop
li x1, 0
li x2, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
# set the stack pointer to the top of memory - 8 bytes (pointer size)
li sp, (EXT_MEM_END - 8)
li a0, 0x00000000
li a1, EXT_MEM_BASE
#li a2, 128*1024*1024/512 # copy 128MB
li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra)
#li a2, 800 # copy 400KB
jal ra, copyFlash
fence.i
# now toggle led so we know the copy completed.
# write to gpio
li t2, 0xFF
la t3, 0x1006000C
li t4, 5
loop:
# delay
li t0, PERIOD/2
delay1:
addi t0, t0, -1
bge t0, x0, delay1
sw t2, 0x0(t3)
li t0, PERIOD/2
delay2:
addi t0, t0, -1
bge t0, x0, delay2
sw x0, 0x0(t3)
addi t4, t4, -1
bgt t4, x0, loop
# now that the card is copied and the led toggled we
# jump to the copied contents of the sd card.
jumpToLinux:
csrrs a0, 0xF14, x0 # copy hart ID to a0
li a1, FDT_ADDRESS # This is the device tree address
la a2, end_of_bios
li t0, EXT_MEM_BASE # start of code
jalr x0, t0, 0
end_of_bios:

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src/cache/cache.sv vendored
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// cache.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 7 July 2021
// Modified: 20 January 2023
//

2
src/cache/cacheLRU.sv vendored
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// cacheLRU.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 20 July 2021
// Modified: 20 January 2023
//

2
src/cache/cachefsm.sv vendored
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// cachefsm.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 25 August 2021
// Modified: 20 January 2023
//

2
src/cache/cacheway.sv vendored
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// cacheway
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 7 July 2021
// Modified: 20 January 2023
//

2
src/cache/subcachelineread.sv vendored
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// subcachelineread.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 4 February 2022
// Modified: 20 January 2023
//

2
src/ebu/ahbcacheinterface.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// ahbcacheinterface.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/ahbinterface.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// ahbinterface.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/buscachefsm.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// busfsm.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: December 29, 2021
// Modified: 18 January 2023
//

2
src/ebu/busfsm.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// busfsm.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: December 29, 2021
// Modified: 18 January 2023
//

2
src/ebu/controllerinput.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// controllerinput.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 31, 2022
// Modified: 18 January 2023
//

2
src/ebu/ebu.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// abhmulticontroller
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: August 29, 2022
// Modified: 18 January 2023
//

2
src/ebu/ebufsmarb.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// ebufsmarb.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 23 January 2023
// Modified: 23 January 2023
//

2
src/generic/arrs.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// arrs.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: November 12, 2021
//
// Purpose: resets are typically asynchronous but need to be synchronized to

2
src/generic/binencoder.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// binencoder.sv
//
// Written: ross1728@gmail.com November 14, 2022
// Written: rose@rosethompson.net November 14, 2022
//
// Purpose: one-hot to binary encoding.
//

2
src/generic/mem/ram1p1rwbe.sv
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@ -2,7 +2,7 @@
// ram1p1r2be.sv
// 1 port sram with byte enables
//
// Written: ross1728@gmail.com
// Written: rose@rosethompson.net
// Created: 3 May 2021
// Modified: 20 January 2023
//

2
src/generic/mem/ram1p1rwe.sv
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@ -2,7 +2,7 @@
// ram1p1rwe.sv
// 1 port sram.
//
// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com)
// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by rose@rosethompson.net)
// Created: 04 April 2023
//
// Purpose: ram1p1wre, but without byte-enable. Used for icache data.

2
src/generic/mem/ram2p1r1wbe.sv
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@ -2,7 +2,7 @@
// ram2p1r1wbe.sv
// 2 port sram.
//
// Written: ross1728@gmail.com May 3, 2021
// Written: rose@rosethompson.net May 3, 2021
// Two port SRAM 1 read port and 1 write port.
// When clk rises Addr and LineWriteData are sampled.
// Following the clk edge read data is output from the sampled Addr.

2
src/generic/onehotdecoder.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// onehotdecoder.sv
//
// Written: ross1728@gmail.com July 09, 2021
// Written: rose@rosethompson.net July 09, 2021
// Modified:
//
// Purpose: Bin to one hot decoder. Power of 2 only.

2
src/ifu/bpred/RASPredictor.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// RASPredictor.sv
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: 15 February 2021
// Modified: 25 January 2023
//

2
src/ifu/bpred/bpred.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// bpred.sv
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: 12 February 2021
// Modified: 19 January 2023
//

2
src/ifu/bpred/btb.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// btb.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: February 15, 2021
// Modified: 24 January 2023
//

2
src/ifu/bpred/gshare.sv
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@ -2,7 +2,7 @@
// gshare.sv
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai)
// Modified: 20 February 2023

2
src/ifu/bpred/gsharebasic.sv
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@ -2,7 +2,7 @@
// gsharebasic.sv
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
// Modified: 20 February 2023

2
src/ifu/bpred/icpred.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// icpred.sv
//
// Written: Rose Thomposn ross1728@gmail.com
// Written: Rose Thomposn rose@rosethompson.net
// Created: February 26, 2023
// Modified: February 26, 2023
//

2
src/ifu/bpred/localaheadbp.sv
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@ -2,7 +2,7 @@
// localaheadbp
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
//
// Purpose: local history branch predictor with ahead pipelining and SRAM memories.

2
src/ifu/bpred/localbpbasic.sv
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@ -2,7 +2,7 @@
// localbpbasic
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 16 March 2021
//
// Purpose: Local history branch predictor. Basic implementation without any repair and flop memories.

2
src/ifu/bpred/localrepairbp.sv
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@ -2,7 +2,7 @@
// localrepairbp
//
// Written: Rose Thompson
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: 15 April 2023
//
// Purpose: Local history branch predictor with speculation and repair using CBH.

2
src/ifu/bpred/satCounter2.sv
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@ -2,7 +2,7 @@
// satCounter2.sv
//
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: February 13, 2021
// Modified:
//

2
src/ifu/bpred/twoBitPredictor.sv
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@ -2,7 +2,7 @@
// twoBitPredictor.sv
//
// Written: Rose Thomposn
// Email: ross1728@gmail.com
// Email: rose@rosethompson.net
// Created: February 14, 2021
// Modified:
//

2
src/ifu/irom.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// irom.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 30 January 2022
// Modified: 18 January 2023
//

2
src/ifu/spill.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// spill.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 28 January 2022
// Modified: 19 January 2023
//

2
src/lsu/align.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// spill.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 26 October 2023
// Modified: 26 October 2023
//

6
src/lsu/atomic.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// atomic.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 31 January 2022
// Modified: 18 January 2023
//
@ -39,7 +39,7 @@ module atomic import cvw::*; #(parameter cvw_t P) (
input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size
input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal
input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation
input logic LSUFlushW, // On FlushM or TLB miss ignore memory operation
output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data
output logic SquashSCW, // Store conditional failed disable write to GPR
output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC
@ -57,7 +57,7 @@ module atomic import cvw::*; #(parameter cvw_t P) (
// LRSC unit
if (P.ZALRSC_SUPPORTED) begin
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
assign MemReadM = PreLSURWM[1] & ~LSUFlushW;
lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
end else begin
assign SquashSCW = 0;

2
src/lsu/dtim.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// dtim.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 30 January 2022
// Modified: 18 January 2023
//

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src/lsu/lsu.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// lsu.sv
//
// Written: David_Harris@hmc.edu, ross1728@gmail.com
// Written: David_Harris@hmc.edu, rose@rosethompson.net
// Created: 9 January 2021
// Modified: 11 January 2023
//
@ -110,8 +110,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
logic BusStall; // Bus interface busy with multicycle operation
logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB
logic LSUBusStallM; // Bus interface busy with multicycle operation masked by HPTWFlushW
logic HPTWStall; // HPTW busy with multicycle operation
logic DCacheBusStallM; // Cache or bus stall
logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall
@ -146,8 +145,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic DTLBWriteM; // Writes PTE and PageType to DTLB
logic LSULoadAccessFaultM; // Load acces fault
logic LSUStoreAmoAccessFaultM; // Store access fault
logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
logic HPTWFlushW; // HPTW needs to flush operation
logic LSUFlushW; // HPTW or hazard unit flushes operation
logic SelDTIM; // Select DTIM rather than bus or D$
logic [P.XLEN-1:0] WriteDataZM;
logic LSULoadPageFaultM, LSUStoreAmoPageFaultM;
@ -200,7 +199,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
.WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
.IHAdrM, .HPTWStall, .SelHPTW,
.IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
.HPTWFlushW, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF,
.LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF
);
@ -215,7 +214,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
assign LoadPageFaultM = LSULoadPageFaultM;
assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM;
assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, HPTWFlushW} = '0;
assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0;
end
@ -274,7 +273,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// Pause IEU memory request if TLB miss. After TLB fill, replay request.
// Discard memory request on pipeline flush
assign IgnoreRequest = IgnoreRequestTLB | FlushW;
assign LSUFlushW = HPTWFlushW | FlushW;
if (P.DTIM_SUPPORTED) begin : dtim
logic [P.PA_BITS-1:0] DTIMAdr;
@ -285,7 +284,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign DTIMMemRWM = SelDTIM ? LSURWM : 0;
dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW),
.MemRWM(DTIMMemRWM),
.DTIMAdr, .FlushW(IgnoreRequest), .WriteDataM(LSUWriteDataM),
.DTIMAdr, .FlushW(LSUFlushW), .WriteDataM(LSUWriteDataM),
.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
end else
assign DTIMReadDataWordM = '0;
@ -309,8 +308,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
logic FlushDCache; // Suppress d cache flush if there is an ITLB miss.
logic CacheStall;
logic [1:0] CacheBusRWTemp;
logic BusCMOZero;
logic [3:0] CacheCMOpM;
logic BusAtomic;
@ -331,29 +328,26 @@ module lsu import cvw::*; #(parameter cvw_t P) (
cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(IgnoreRequest),
.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW),
.CacheRW(CacheRWM),
.FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM),
.ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
.WriteData(LSUWriteDataSpillM), .SelHPTW,
.CacheStall, .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM),
.FetchBuffer, .CacheBusRW(CacheBusRWTemp),
.FetchBuffer, .CacheBusRW(CacheBusRW),
.CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM));
assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
assign CacheBusRW = CacheBusRWTemp;
ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest),
.HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW),
.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
.HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
.BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM),
.Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .BusAtomic, .BusCMOZero, .CacheableOrFlushCacheM,
.CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
.Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
.BusStall, .BusCommitted(BusCommittedM));
.BusStall(LSUBusStallM), .BusCommitted(BusCommittedM));
mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
.d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
@ -366,10 +360,10 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign LSUHADDR = PAdrM;
assign LSUHSIZE = LSUFunct3M;
ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HREADY(LSUHREADY),
ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HREADY(LSUHREADY),
.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
.HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
.Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
@ -381,12 +375,10 @@ module lsu import cvw::*; #(parameter cvw_t P) (
assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0;
assign DCacheReadDataWordM = '0;
assign ReadDataWordMuxM = DTIMReadDataWordM;
assign {BusStall, BusCommittedM} = '0;
assign {LSUBusStallM, BusCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
assign {DCacheStallM, DCacheCommittedM} = '0;
end
assign LSUBusStallM = BusStall & ~IgnoreRequestTLB;
/////////////////////////////////////////////////////////////////////////////////////////////
// Atomic operations
@ -394,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic
atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .LSUFlushW,
.IMAWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc
assign SquashSCW = 1'b0;

34
src/mmu/hptw.sv
View File

@ -58,7 +58,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
output logic [1:0] LSUAtomicM,
output logic [2:0] LSUFunct3M,
output logic [6:0] LSUFunct7M,
output logic IgnoreRequestTLB,
output logic HPTWFlushW,
output logic SelHPTW,
output logic HPTWStall,
input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM,
@ -105,6 +105,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
logic TakeHPTWFault;
logic PBMTFaultM;
logic HPTWFaultM;
logic ResetPTE;
// map hptw access faults onto either the original LSU load/store fault or instruction access fault
assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
@ -143,7 +144,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
// State flops
flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE;
flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
flopenr #(P.XLEN) PTEReg(clk, ResetPTE, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
// Assign PTE descriptors common across all XLEN values
// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
@ -274,23 +275,26 @@ module hptw import cvw::*; #(parameter cvw_t P) (
IDLE: if (TLBMissOrUpdateDA) NextWalkerState = InitialWalkerState;
else NextWalkerState = IDLE;
L3_ADR: NextWalkerState = L3_RD; // First access in SV48
L3_RD: if (DCacheBusStallM) NextWalkerState = L3_RD;
else if (HPTWFaultM) NextWalkerState = FAULT;
L3_RD: if (HPTWFaultM) NextWalkerState = FAULT;
else if (DCacheBusStallM) NextWalkerState = L3_RD;
else NextWalkerState = L2_ADR;
L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39
L2_ADR: if (HPTWFaultM) NextWalkerState = FAULT;
else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39
else NextWalkerState = LEAF;
L2_RD: if (DCacheBusStallM) NextWalkerState = L2_RD;
else if (HPTWFaultM) NextWalkerState = FAULT;
L2_RD: if (HPTWFaultM) NextWalkerState = FAULT;
else if (DCacheBusStallM) NextWalkerState = L2_RD;
else NextWalkerState = L1_ADR;
L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32
L1_ADR: if (HPTWFaultM) NextWalkerState = FAULT;
else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32
else NextWalkerState = LEAF;
L1_RD: if (DCacheBusStallM) NextWalkerState = L1_RD;
else if (HPTWFaultM) NextWalkerState = FAULT;
L1_RD: if (HPTWFaultM) NextWalkerState = FAULT;
else if (DCacheBusStallM) NextWalkerState = L1_RD;
else NextWalkerState = L0_ADR;
L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD;
L0_ADR: if (HPTWFaultM) NextWalkerState = FAULT;
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
else NextWalkerState = LEAF;
L0_RD: if (DCacheBusStallM) NextWalkerState = L0_RD;
else if (HPTWFaultM) NextWalkerState = FAULT;
L0_RD: if (HPTWFaultM) NextWalkerState = FAULT;
else if (DCacheBusStallM) NextWalkerState = L0_RD;
else NextWalkerState = LEAF;
LEAF: if (P.SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE;
else NextWalkerState = IDLE;
@ -300,7 +304,9 @@ module hptw import cvw::*; #(parameter cvw_t P) (
default: NextWalkerState = IDLE; // Should never be reached
endcase // case (WalkerState)
assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // If hptw request has pmp/a fault suppress bus access.
assign HPTWFlushW = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM);
assign ResetPTE = reset | (NextWalkerState == IDLE);
assign SelHPTW = WalkerState != IDLE;
assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA);

7
src/privileged/csrm.sv
View File

@ -171,7 +171,7 @@ module csrm import cvw::*; #(parameter cvw_t P) (
flopenr #(P.XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
flopenr #(P.XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW);
flopenr #(P.XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, {CSRWriteValM[31:2], 1'b0, CSRWriteValM[0]}, MCOUNTINHIBIT_REGW);
if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
end else assign MCOUNTEREN_REGW = '0;
@ -180,7 +180,9 @@ module csrm import cvw::*; #(parameter cvw_t P) (
if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
logic WriteMENVCFGM;
logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
logic [1:0] LegalizedCBIE;
assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
assign LegalizedCBIE = MENVCFG_PreWriteValM[5:4] == 2'b10 ? MENVCFG_REGW[5:4] : MENVCFG_PreWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value
// MENVCFG is always 64 bits even for RV32
assign MENVCFG_WriteValM = {
MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED,
@ -188,7 +190,8 @@ module csrm import cvw::*; #(parameter cvw_t P) (
MENVCFG_PreWriteValM[61] & P.SVADU_SUPPORTED,
53'b0,
MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED,
MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
MENVCFG_PreWriteValM[6] & P.ZICBOM_SUPPORTED,
LegalizedCBIE & {2{P.ZICBOM_SUPPORTED}},
3'b0,
MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
};

3
src/privileged/csrsr.sv
View File

@ -106,7 +106,8 @@ module csrsr import cvw::*; #(parameter cvw_t P) (
always_comb
if (CSRWriteValM[12:11] == P.U_MODE & P.U_SUPPORTED) STATUS_MPP_NEXT = P.U_MODE;
else if (CSRWriteValM[12:11] == P.S_MODE & P.S_SUPPORTED) STATUS_MPP_NEXT = P.S_MODE;
else STATUS_MPP_NEXT = P.M_MODE;
else if (CSRWriteValM[12:11] == 2'b10) STATUS_MPP_NEXT = STATUS_MPP; // do not change MPP when trying to write reserved 10
else STATUS_MPP_NEXT = P.M_MODE;
///////////////////////////////////////////
// Endianness logic Privileged Spec 3.1.6.4

2
src/rvvi/csrindextoaddr.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// csrindextoaddr.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 24 January 2024
// Modified: 24 January 2024
//

2
src/rvvi/packetizer.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// packetizer.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 21 May 2024
// Modified: 21 May 2024
//

2
src/rvvi/priorityaomux.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// priorityaomux.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 24 January 2024
// Modified: 24 January 2024
//

2
src/rvvi/regchangedetect.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// regchangedetect.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 24 January 2024
// Modified: 24 January 2024
//

2
src/rvvi/rvvisynth.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// rvvisynth.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: 23 January 2024
// Modified: 23 January 2024
//

2
src/rvvi/triggergen.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// triggergen.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Created: June 26, 2024
// Modified: June 26, 2024
//

2
testbench/common/DCacheFlushFSM.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// DCacheFlushFSM.sv
//
// Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com
// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net
// Modified: 14 June 2023
//
// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty

2
testbench/common/functionName.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// functionName.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
//
// Purpose: decode name of function
//

2
testbench/common/loggers.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// loggers.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: 14 June 2023
//
// Purpose: Log branch instructions, log instruction fetches,

2
testbench/common/rvvitbwrapper.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// loggers.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: 24 July 2024
//
// Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench.

2
testbench/common/watchdog.sv
View File

@ -1,7 +1,7 @@
///////////////////////////////////////////
// watchdog.sv
//
// Written: Rose Thompson ross1728@gmail.com
// Written: Rose Thompson rose@rosethompson.net
// Modified: 14 June 2023
//
// Purpose: Detects if the processor is stuck and halts the simulation

1
testbench/tests.vh
View File

@ -60,6 +60,7 @@ string coverage64gc[] = '{
"tlbTP",
"tlbMisaligned",
"hptwAccessFault",
"nonleafpbmtfault",
"amoAccessFault",
"floatmisc",
"ifuCamlineWrite",

15
tests/coverage/WALLY-init-lib.h
View File

@ -127,6 +127,18 @@ write_tohost:
self_loop:
j self_loop # wait
// utility routines
# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64
setmsb:
li a0, 0x80000000 # 1 in bit 31
slli a1, a0, 1 # check if register is wider than 31 bits
beqz a1, setmsbdone # yes, a0 has 1 in bit 31
slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63
slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
setmsbdone:
ret # return to calller
.section .tohost
tohost: # write to HTIF
@ -139,6 +151,9 @@ begin_signature:
.fill 6*(XLEN/32),4,0xdeadbeef #
end_signature:
scratch:
.fill 4,4,0x0
# Initialize stack with room for 512 bytes
.bss
.space 512

27
tests/coverage/hptwAccessFault.S
View File

@ -48,7 +48,32 @@ main:
lw t1, 0(t0) # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault
li t1, 0x00008067 # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault
add t0, t0, t2
sw t1, 0(t0)
sw t1, 0(t0)
j jumppoint
jumppoint:
.align 6 # aligns to cache line size
sw t1, 0(t0)
sw t1, 4(t0)
sw t1, 8(t0)
sw t1, 12(t0)
sw t1, 16(t0)
sw t1, 20(t0)
sw t1, 24(t0)
sw t1, 28(t0)
sw t1, 32(t0)
sw t1, 36(t0)
sw t1, 40(t0)
sw t1, 44(t0)
sw t1, 48(t0)
sw t1, 52(t0) # this one causes a concurrent I$ miss with HPTW access exception (store access exception)
sw t1, 56(t0)
lw t3, 0(t0)
lw t3, 4(t0)
lw t3, 8(t0)
lw t3, 12(t0)
lw t3, 16(t0)
fence.I

143
tests/coverage/nonleafpbmtfault.S Normal file
View File

@ -0,0 +1,143 @@
///////////////////////////////////////////
// hptwAccessFault.S
//
// Written: Rose Thompson rose@rosethompson.net
//
// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits. This will generate
// a load or store/amo page fault based on the original access type.
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// load code to initalize stack, handle interrupts, terminate
#include "WALLY-init-lib.h"
# run-elf.bash find this in project description
main:
# Page table root address at 0x80010000
li t5, 0x9000000000080010
csrw satp, t5
# sfence.vma x0, x0
# switch to supervisor mode
li a0, 1
ecall
li t5, 0
li t2, 0x1000
li t0, 0x8000001000
lw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
li t1, 0x00008067
add t0, t0, t2
sw t1, 0(t0) # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
fence.I
finished:
j done
.data
.align 16
# Page table situated at 0x80010000
pagetable:
.8byte 0x200044C1
.8byte 0x200044C1
.align 12
.8byte 0x40000040200048C1
.8byte 0x00000000200048C1
.8byte 0x00000000200048C1
.align 12
.8byte 0x0000000020004CC1
.align 12
#80000000
.8byte 0x200000CF
.8byte 0x200004CF
.8byte 0x200008CF
.8byte 0x20000CCF
.8byte 0x200010CF
.8byte 0x200014CF
.8byte 0x200018CF
.8byte 0x20001CCF
.8byte 0x200020CF
.8byte 0x200024CF
.8byte 0x200028CF
.8byte 0x20002CCF
.8byte 0x200030CF
.8byte 0x200034CF
.8byte 0x200038CF
.8byte 0x20003CCF
.8byte 0x200040CF
.8byte 0x200044CF
.8byte 0x200048CF
.8byte 0x20004CCF
.8byte 0x200050CF
.8byte 0x200054CF
.8byte 0x200058CF
.8byte 0x20005CCF
.8byte 0x200060CF
.8byte 0x200064CF
.8byte 0x200068CF
.8byte 0x20006CCF
.8byte 0x200070CF
.8byte 0x200074CF
.8byte 0x200078CF
.8byte 0x20007CCF
.8byte 0x200080CF
.8byte 0x200084CF
.8byte 0x200088CF
.8byte 0x20008CCF
.8byte 0x200090CF
.8byte 0x200094CF
.8byte 0x200098CF
.8byte 0x20009CCF
.8byte 0x2000A0CF
.8byte 0x2000A4CF
.8byte 0x2000A8CF
.8byte 0x2000ACCF
.8byte 0x2000B0CF
.8byte 0x2000B4CF
.8byte 0x2000B8CF
.8byte 0x2000BCCF
.8byte 0x2000C0CF
.8byte 0x2000C4CF
.8byte 0x2000C8CF
.8byte 0x2000CCCF
.8byte 0x2000D0CF
.8byte 0x2000D4CF

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S
View File

@ -3,7 +3,7 @@
// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 18 August 2023
//

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S
View File

@ -3,7 +3,7 @@
// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 22 August 2023
//

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
View File

@ -3,7 +3,7 @@
// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 18 August 2023
//

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S
View File

@ -3,7 +3,7 @@
// WALLY-cache-management-tests
// invalidate, clean, and flush
//
// Author: Rose Thompson <ross1728@gmail.com>
// Author: Rose Thompson <rose@rosethompson.net>
//
// Created 22 August 2023
//