vclean working; started removing unused signals

bin/vclean.pl

@@ -5,7 +5,41 @@
 # Identifies unused signals in Verilog files
 #   verilator should do this, but it also reports partially used signals
 
+use strict;
+
 for (my $i=0; $i<=$#ARGV; $i++) {
     my $fname = $ARGV[$i];
-    printf ("$fname\n");
+    &clean($fname);
+}
+
+sub clean {
+    my $fname = shift;
+
+#    printf ("Cleaning $fname\n");
+    open(FILE, $fname) || die("Can't read $fname");
+#    my $incomment = 0;
+    my @allsigs;
+    while (<FILE>) {
+        if (/typedef/) { } # skip typedefs
+        elsif (/logic (.*)/) { # found signal declarations
+            my $siglist = $1;
+            $siglist =~ s/\/\/.*//; # trim off everything after //
+#            print ("Logic: $siglist\n");
+            $siglist =~ s/\[[^\]]*\]//g; # trim off everything in brackets
+            $siglist =~ s/\s//g; # trim off white space
+#            print ("Logic Trimmed: $siglist\n");
+            my @sigs = split(/[,;)]/, $siglist);
+#            print ("Logic parsed: @sigs\n");
+            push(@allsigs, @sigs);
+        }
+    }
+#    print("Signals: @allsigs\n");
+    foreach my $sig (@allsigs) {
+#        print("Searching for $sig\n");
+        my $hits = `grep -c $sig $fname`;
+#        print("  Signal $sig appears $hits times\n");
+        if ($hits < 2) {
+            printf("$sig not used in $fname\n");
+        }
+    }
 }

pipelined/src/cache/cache.sv

@@ -164,7 +164,6 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   end
 
   assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
-  logic [LINELEN/8-1:0]       LineByteMask2;
   assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
 
   for(index = 0; index < LINELEN/8; index++) begin

pipelined/src/ebu/ebu.sv

@@ -90,12 +90,10 @@ module ebu
   logic                       LSUHWRITEOut;
 
   logic                       IFUReq, LSUReq;
-  logic                       IFUActive, LSUActive;
 
   logic                       BeatCntEn;
-  logic [4-1:0]               NextBeatCount, BeatCount, BeatCountDelayed;
+  logic [4-1:0]               NextBeatCount, BeatCount;
   logic                       FinalBeat, FinalBeatD;
-  logic [2:0]                 LocalBurstType;
   logic                       CntReset;
   logic [3:0]                 Threshold;
   logic                       IFUReqD;
@@ -164,8 +162,6 @@ module ebu
   assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
   assign BeatCntEn = (NextState == ARBITRATE & HREADY);
 
-  logic [2:0]                 HBURSTD;
-  
   // Used to store data from data phase of AHB.
   flopenr #(1) 
   FinalBeatReg(.clk(HCLK),

pipelined/src/fpu/fcvt.sv

@@ -39,7 +39,6 @@ module fcvt (
     input logic [2:0]               OpCtrl,     // choose which opperation (look below for values)
     input logic                     ToInt,      // is fp->int (since it's writting to the integer register)
     input logic                     XZero,      // is the input zero
-    input logic                     XSubnorm,   // is the input Subnormalized
     input logic [`FMTBITS-1:0]      Fmt,        // the input's precision (11=quad 01=double 00=single 10=half)
     output logic [`NE:0]            Ce,         // the calculated expoent
 	output logic [`LOGCVTLEN-1:0]   ShiftAmt,   // how much to shift by

pipelined/src/fpu/fpu.sv

@@ -290,7 +290,7 @@ module fpu (
    // convert
    //    - fcvt.*.*
    fcvt fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE), 
-              .ToInt(FWriteIntE), .XZero(XZeroE), .XSubnorm(XSubnormE), .Fmt(FmtE), .Ce(CeE), 
+              .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), 
               .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), 
               .LzcIn(CvtLzcInE));