diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh
index ccc194a27..789f6ae70 100644
--- a/config/rv32gc/coverage.svh
+++ b/config/rv32gc/coverage.svh
@@ -26,6 +26,8 @@
 `include "ZfaZfh_coverage.svh"
 `include "Zfh_coverage.svh"
 `include "ZfhD_coverage.svh"
+// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used.  When Zfhmin and D are supported, ZfhD should also be enabled
+`include "Zfhmin_coverage.svh"
 `include "Zicond_coverage.svh"
 `include "Zca_coverage.svh"
 `include "Zcb_coverage.svh"
diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
index d0ec96fb8..f86f0882f 100644
--- a/config/rv64gc/coverage.svh
+++ b/config/rv64gc/coverage.svh
@@ -26,6 +26,8 @@
 `include "ZfaZfh_coverage.svh"
 `include "ZfhD_coverage.svh"
 `include "Zfh_coverage.svh"
+// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used.  When Zfhmin and D are supported, ZfhD should also be enabled
+`include "Zfhmin_coverage.svh"
 `include "Zicond_coverage.svh"
 `include "Zca_coverage.svh"
 `include "Zcb_coverage.svh"
diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv
index 3b329705d..a252bbd23 100644
--- a/src/mmu/tlb/tlbram.sv
+++ b/src/mmu/tlb/tlbram.sv
@@ -51,6 +51,6 @@ module tlbram import cvw::*;  #(parameter cvw_t P,
   or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry);
 
   // Rename the bits read from the TLB RAM
-  assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bitss
+  assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits
   assign PPN = PageTableEntry[P.PPN_BITS+9:10];
 endmodule