From cd5b8be78f9f3253c0c2dd3f852098cf0ea4db7c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 21 Sep 2022 18:23:56 -0500
Subject: [PATCH] Cleaned up the IFU and LSU around dtim and irom address
 calculation.

---
 pipelined/src/ifu/ifu.sv | 12 ++++--------
 pipelined/src/lsu/lsu.sv |  3 +--
 2 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 8d68d954a..81cf396b9 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -186,14 +186,8 @@ module ifu (
 
   // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
   if (`IROM_SUPPORTED) begin : irom 
-    logic [`PA_BITS-1:0] IROMAdr;
-    logic             IROMAccessRW;
-    /* verilator lint_off WIDTH */
-    assign IROMAdr = reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS
-    /* verilator lint_on WIDTH */
- 
     assign RWF = 2'b10;
-    irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(IROMAdr[`XLEN-1:0]), .ReadData(FinalInstrRawF));
+    irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(FinalInstrRawF));
  
   end else begin
     assign RWF = 2'b10;
@@ -322,8 +316,10 @@ module ifu (
   assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC
   // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
   // Speeds up critical path as compared to selecting adder input based on CompressedF
+  // *** consider gating PCPlusUpperF to provide the reset.
   always_comb
-    if (CompressedF) // add 2
+    if(reset) PCPlus2or4F = '0;
+    else if (CompressedF) // add 2
       if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00}; 
       else        PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
     else          PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 79c1fd21c..1c9ed7034 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -212,10 +212,9 @@ module lsu (
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
     // Don't perform size checking on DTIM
     /* verilator lint_off WIDTH */
-    assign MemStage = MemRWM[0] | reset; // 1 = M stage; 0 = E stage
+    assign MemStage = MemRWM[0]; // 1 = M stage; 0 = E stage // **** is reset needed.
     assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
     /* verilator lint_on WIDTH */
-    // *** add ce to bram1... to remove this extra mux control.
 
     dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM,
               .Adr(DTIMAdr),