From ccf4bb8ddc292fb9bbfe006452b3a3c5a8a38f2a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 26 Jun 2024 16:15:46 -0700 Subject: [PATCH] Maybe have the incircuit trigger working. --- fpga/constraints/small-debug.xdc | 31 ++++++++++++++----------------- fpga/src/fpgaTopArtyA7.sv | 8 ++++---- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc index c2daf9fe1..b244a1747 100644 --- a/fpga/constraints/small-debug.xdc +++ b/fpga/constraints/small-debug.xdc @@ -1,22 +1,20 @@ create_debug_core u_ila_0 ila - - - - set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN true [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] -startgroup set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] -endgroup +create_debug_port u_ila_0 trig_in +create_debug_port u_ila_0 trig_in_ack +#set_property port_width 1 [get_debug_ports u_ila_0/trig_in] +#set_property port_width 1 [get_debug_ports u_ila_0/trig_in_ack] +#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/trig_in] +connect_debug_port u_ila_0/trig_in [get_nets IlaTrigger] +#connect_debug_port u_ila_0/trig_in_ack [get_nets IlaTriggerAck] connect_debug_port u_ila_0/clk [get_nets CPUCLK] set_property port_width 32 [get_debug_ports u_ila_0/probe0] @@ -53,10 +51,15 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] +#create_debug_port u_ila_0 probe +#set_property port_width 1 [get_debug_ports u_ila_0/probe7] +#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +#connect_debug_port u_ila_0/probe7 [get_nets [list {IlaTrigger} ]] + create_debug_port u_ila_0 probe -set_property port_width 32 [get_debug_ports u_ila_0/probe7] +set_property port_width 1 [get_debug_ports u_ila_0/probe7] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {packetizer/FrameCount[0]} {packetizer/FrameCount[1]} {packetizer/FrameCount[2]} {packetizer/FrameCount[3]} {packetizer/FrameCount[4]} {packetizer/FrameCount[5]} {packetizer/FrameCount[6]} {packetizer/FrameCount[7]} {packetizer/FrameCount[8]} {packetizer/FrameCount[9]} {packetizer/FrameCount[10]} {packetizer/FrameCount[11]} {packetizer/FrameCount[12]} {packetizer/FrameCount[13]} {packetizer/FrameCount[14]} {packetizer/FrameCount[15]} {packetizer/FrameCount[16]} {packetizer/FrameCount[17]} {packetizer/FrameCount[18]} {packetizer/FrameCount[19]} {packetizer/FrameCount[20]} {packetizer/FrameCount[21]} {packetizer/FrameCount[22]} {packetizer/FrameCount[23]} {packetizer/FrameCount[24]} {packetizer/FrameCount[25]} {packetizer/FrameCount[26]} {packetizer/FrameCount[27]} {packetizer/FrameCount[28]} {packetizer/FrameCount[29]} {packetizer/FrameCount[30]} {packetizer/FrameCount[31]} ]] +connect_debug_port u_ila_0/probe7 [get_nets [list {RvviAxiWvalid}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe8] @@ -73,15 +76,9 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe10] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] connect_debug_port u_ila_0/probe10 [get_nets [list {RvviAxiWready}]] -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe11] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {RvviAxiWvalid}]] # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] connect_debug_port dbg_hub/clk [get_nets CPUCLK] -# connect the trig_in in of the ila to the -connect_debug_port u_ila_0/trig_in [get_nets [list {IlaTrigger}]] diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 811d32e4f..8202d735f 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -1128,8 +1128,8 @@ module fpgaTop (* mark_debug = "true" *) logic RvviAxiWvalid; (* mark_debug = "true" *) logic RvviAxiWready; - logic RvviAxiRdata [31:0]; - logic RvviAxiRstrb [3:0]; + logic [31:0] RvviAxiRdata; + logic [3:0] RvviAxiRstrb; logic RvviAxiRlast; logic RvviAxiRvalid; (* mark_debug = "true" *) logic IlaTrigger; @@ -1163,8 +1163,8 @@ module fpgaTop ); triggergen triggergen(.clk(CPUCLK), .reset(bus_struct_reset), .RvviAxiRdata, - .RvviAxiRstrb, .RvviAxiRlast, .RvviAxiRvalid, .IlaTrigger) - + .RvviAxiRstrb, .RvviAxiRlast, .RvviAxiRvalid, .IlaTrigger); + //assign phy_reset_n = ~bus_struct_reset; assign phy_reset_n = ~1'b0;