From cca60ed06d9212490a256079ca59fdb4c1ef2daa Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Sat, 30 Jan 2021 17:38:18 +0000 Subject: [PATCH] update busybear testbench to conform to new structure aaaaaaaaaaaaaaaaaahhhh so many changes also the testbench now uses another internal signal, which I don't like, but I can't think of a better option rn --- .../config/busybear/wally-config.vh | 14 +++++++- wally-pipelined/regression/wally-busybear.do | 13 ++++--- .../testbench/testbench-busybear.sv | 35 ++++++++----------- 3 files changed, 34 insertions(+), 28 deletions(-) diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index 92e11aacb..a3c5188f6 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -57,7 +57,19 @@ // Address space `define RESET_VECTOR 64'h0000000000001000 -// Bus Interface +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +`define TIMBASE 64'h0000000080000000 +`define TIMRANGE 64'h000000000007FFFF +`define CLINTBASE 64'h0000000002000000 +`define CLINTRANGE 64'h000000000000FFFF +`define GPIOBASE 64'h0000000010012000 +`define GPIORANGE 64'h00000000000000FF +`define UARTBASE 64'h0000000010000000 +`define UARTRANGE 64'h0000000000000007 +// Bus Interface width `define AHBW 64 // Test modes diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index f1ccea6ae..b5b7a7bee 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -26,7 +26,7 @@ vlib work # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog +incdir+../config/busybear ../testbench/*.sv ../src/*.sv -suppress 2583 +vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals @@ -50,12 +50,11 @@ add wave /testbench_busybear/lastPC2 add wave -divider # registers! add wave -hex /testbench_busybear/rfExpected -add wave -hex /testbench_busybear/MemRWM[0] -add wave -hex /testbench_busybear/MemRWM[1] -add wave -hex /testbench_busybear/ByteMaskM -add wave -hex /testbench_busybear/WriteDataM -add wave -hex /testbench_busybear/ReadDataM -add wave -hex /testbench_busybear/DataAdrM +add wave -hex /testbench_busybear/HWRITE +add wave -hex /testbench_busybear/dut/MemRWM[1] +add wave -hex /testbench_busybear/HWDATA +add wave -hex /testbench_busybear/HRDATA +add wave -hex /testbench_busybear/HADDR add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1] add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2] add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[3] diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index d47a32bf5..77aac8ce2 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -3,15 +3,12 @@ module testbench_busybear(); logic clk, reset; - logic [`XLEN-1:0] WriteDataM, DataAdrM; - logic [1:0] MemRWM; logic [31:0] GPIOPinsIn; logic [31:0] GPIOPinsOut, GPIOPinsEn; // instantiate device to be tested - logic [`XLEN-1:0] PCF, ReadDataM; + logic [`XLEN-1:0] PCF; logic [31:0] InstrF; - logic [7:0] ByteMaskM; logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM = 0, SwIntM = 0; // from CLINT logic ExtIntM = 0; // not yet connected @@ -26,6 +23,7 @@ module testbench_busybear(); logic [3:0] HPROT; logic [1:0] HTRANS; logic HMASTLOCK; + logic HCLK, HRESETn; assign GPIOPinsIn = 0; assign UARTSin = 1; @@ -115,40 +113,37 @@ module testbench_busybear(); logic [`XLEN-1:0] readAdrExpected; // this might need to change - always @(MemRWM[1] or DataAdrM) begin - if (MemRWM[1]) begin + always @(dut.MemRWM[1] or HADDR) begin + if (dut.MemRWM[1]) begin if($feof(data_file_memR)) begin $display("no more memR data to read"); $stop; end scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); - scan_file_memR = $fscanf(data_file_memR, "%x\n", ReadDataM); - if (DataAdrM != readAdrExpected) begin - $display("%t ps, instr %0d: DataAdrM does not equal readAdrExpected: %x, %x", $time, instrs, DataAdrM, readAdrExpected); + scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); + #1; + if (HADDR != readAdrExpected) begin + $display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); end end end - + logic [`XLEN-1:0] writeDataExpected, writeAdrExpected; // this might need to change - always @(WriteDataM or DataAdrM or ByteMaskM) begin + always @(HWDATA or HADDR or HSIZE) begin #1; - if (MemRWM[0]) begin + if (HWRITE) begin if($feof(data_file_memW)) begin $display("no more memW data to read"); $stop; end scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); - for(int i=0; i<8; i++) begin - if (ByteMaskM[i]) begin - if (writeDataExpected[i*8+7 -: 8] != WriteDataM[i*8+7 -: 8]) begin - $display("%t ps, instr %0d: WriteDataM does not equal writeDataExpected: %x, %x", $time, instrs, WriteDataM, writeDataExpected); - end - end + if (writeDataExpected != HWDATA) begin + $display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); end - if (writeAdrExpected != DataAdrM) begin - $display("%t ps, instr %0d: DataAdrM does not equal writeAdrExpected: %x, %x", $time, instrs, DataAdrM, writeAdrExpected); + if (writeAdrExpected != HADDR) begin + $display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected); end end end