From cc80f1f7b2114e54176aa129803d2a4d10022118 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 11 Nov 2022 15:33:03 -0600
Subject: [PATCH] Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200
 Mhz (2400 MT/s). Increased CPU clock speed from 30 Mhz to 35 Mhz.

---
 fpga/generator/xlnx_ddr4-vcu118.tcl | 13 +++++--------
 linux/devicetree/wally-vcu118.dts   |  6 +++---
 2 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/xlnx_ddr4-vcu118.tcl
index cc5b61b2d..9b515424d 100644
--- a/fpga/generator/xlnx_ddr4-vcu118.tcl
+++ b/fpga/generator/xlnx_ddr4-vcu118.tcl
@@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.No_Controller {1} \
 			CONFIG.Phy_Only {Complete_Memory_Controller} \
 			CONFIG.C0.DDR4_PhyClockRatio {4:1} \
-			CONFIG.C0.DDR4_TimePeriod {1200} \
+			CONFIG.C0.DDR4_TimePeriod {833} \
 			CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
 			CONFIG.C0.DDR4_BurstLength {8} \
 			CONFIG.C0.DDR4_BurstType {Sequential} \
-			CONFIG.C0.DDR4_CasLatency {13} \
-			CONFIG.C0.DDR4_CasWriteLatency {10} \
+			CONFIG.C0.DDR4_CasLatency {16} \
+			CONFIG.C0.DDR4_CasWriteLatency {12} \
 			CONFIG.C0.DDR4_Slot {Single} \
 			CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
 			CONFIG.C0.DDR4_DataWidth {64} \
@@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_AxiIDWidth {4} \
 			CONFIG.C0.DDR4_AxiAddressWidth {31} \
 			CONFIG.C0.DDR4_AxiNarrowBurst {false} \
-			CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
-			CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
-			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {30} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {35} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
+			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
 			CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
diff --git a/linux/devicetree/wally-vcu118.dts b/linux/devicetree/wally-vcu118.dts
index cc077360f..2f1a10f44 100644
--- a/linux/devicetree/wally-vcu118.dts
+++ b/linux/devicetree/wally-vcu118.dts
@@ -21,8 +21,8 @@
 	cpus {
 		#address-cells = <0x01>;
 		#size-cells = <0x00>;
-		clock-frequency = <0x1C9C380>;
-		timebase-frequency = <0x1C9C380>;
+		clock-frequency = <0x211D0D0>;
+		timebase-frequency = <0x211D0D0>;
 
 		cpu@0 {
 			phandle = <0x01>;
@@ -51,7 +51,7 @@
 		uart@10000000 {
 			interrupts = <0x0a>;
 			interrupt-parent = <0x03>;
-			clock-frequency = <0x1C9C380>;
+			clock-frequency = <0x211D0D0>;
 			reg = <0x00 0x10000000 0x00 0x100>;
 			compatible = "ns16550a";
 		};