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https://github.com/openhwgroup/cvw
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Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.
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@ -64,16 +64,16 @@ module fdivsqrt(
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logic [`DIVb+1:0] FirstC;
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logic [`DIVb+1:0] FirstC;
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logic Firstun;
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logic Firstun;
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logic WZeroM, AZeroM, BZeroM, AZeroE, BZeroE;
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logic WZeroM, AZeroM, BZeroM, AZeroE, BZeroE;
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logic SpecialCaseM;
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logic SpecialCaseM, MDUM;
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logic [`DIVBLEN:0] nE, nM, mM;
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logic [`DIVBLEN:0] nE, nM, mM;
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logic CalcOTFCSwapE, OTFCSwapE, ALTBM, As;
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logic CalcOTFCSwapE, OTFCSwapE, ALTBM, AsM;
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logic DivStartE;
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logic DivStartE;
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logic [`XLEN-1:0] ForwardedSrcAM;
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logic [`XLEN-1:0] ForwardedSrcAM;
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fdivsqrtpreproc fdivsqrtpreproc(
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fdivsqrtpreproc fdivsqrtpreproc(
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.clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
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.clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE),
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.Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM,
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.Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM, .MDUM,
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.nE, .nM, .mM, .CalcOTFCSwapE, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As,
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.nE, .nM, .mM, .CalcOTFCSwapE, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .AsM,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .MDUE, .W64E);
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .MDUE, .W64E);
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fdivsqrtfsm fdivsqrtfsm(
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fdivsqrtfsm fdivsqrtfsm(
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.clk, .reset, .FmtE, .XsE, .SqrtE, .nE,
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.clk, .reset, .FmtE, .XsE, .SqrtE, .nE,
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@ -87,8 +87,8 @@ module fdivsqrt(
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.IFDivStartE, .CalcOTFCSwapE, .OTFCSwapE,
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.IFDivStartE, .CalcOTFCSwapE, .OTFCSwapE,
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.FDivBusyE);
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.FDivBusyE);
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fdivsqrtpostproc fdivsqrtpostproc(
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fdivsqrtpostproc fdivsqrtpostproc(
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.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
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.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .MDUM,
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.SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAM,
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.SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAM,
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.nM, .ALTBM, .mM, .BZeroM, .As, .OTFCSwapEM(OTFCSwapE),
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.nM, .ALTBM, .mM, .BZeroM, .AsM, .OTFCSwapEM(OTFCSwapE),
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.QmM, .WZeroM, .DivSM, .FPIntDivResultM);
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.QmM, .WZeroM, .DivSM, .FPIntDivResultM);
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endmodule
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endmodule
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@ -37,7 +37,7 @@ module fdivsqrtpostproc(
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input logic [`DIVb+1:0] FirstC,
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input logic [`DIVb+1:0] FirstC,
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input logic Firstun, SqrtM, SpecialCaseM, OTFCSwapEM,
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input logic Firstun, SqrtM, SpecialCaseM, OTFCSwapEM,
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input logic [`XLEN-1:0] ForwardedSrcAM,
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input logic [`XLEN-1:0] ForwardedSrcAM,
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input logic RemOpM, ALTBM, BZeroM, As,
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input logic RemOpM, ALTBM, BZeroM, AsM, MDUM,
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input logic [`DIVBLEN:0] nM, mM,
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input logic [`DIVBLEN:0] nM, mM,
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output logic [`DIVb:0] QmM,
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output logic [`DIVb:0] QmM,
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output logic WZeroM,
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output logic WZeroM,
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@ -45,7 +45,7 @@ module fdivsqrtpostproc(
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output logic [`XLEN-1:0] FPIntDivResultM
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output logic [`XLEN-1:0] FPIntDivResultM
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);
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);
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logic [`DIVb+3:0] W, Sum, RemDM;
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logic [`DIVb+3:0] W, Sum, DM;
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logic [`DIVb:0] PreQmM;
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logic [`DIVb:0] PreQmM;
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logic NegStickyM, PostIncM;
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logic NegStickyM, PostIncM;
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logic weq0;
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logic weq0;
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@ -64,7 +64,7 @@ module fdivsqrtpostproc(
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logic [`DIVb+3:0] WCF, WSF;
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logic [`DIVb+3:0] WCF, WSF;
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assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
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assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
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assign FZero = SqrtM ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b001,D,1'b0};
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assign FZero = (SqrtM & ~MDUM) ? {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0} : {3'b001,D,1'b0};
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csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
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csa #(`DIVb+4) fadd(WS, WC, FZero, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
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aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0);
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aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0);
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assign WZeroM = weq0|(wfeq0 & Firstun);
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assign WZeroM = weq0|(wfeq0 & Firstun);
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@ -77,14 +77,14 @@ module fdivsqrtpostproc(
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assign Sum = WC + WS;
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assign Sum = WC + WS;
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assign W = $signed(Sum) >>> `LOGR;
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assign W = $signed(Sum) >>> `LOGR;
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assign NegStickyM = W[`DIVb+3];
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assign NegStickyM = W[`DIVb+3];
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assign RemDM = {4'b0000, D};
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assign DM = {4'b0001, D};
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// Integer division: sign handling for div and rem
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// Integer division: sign handling for div and rem
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always_comb
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always_comb
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if (~As)
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if (~AsM)
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if (NegStickyM) begin
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if (NegStickyM) begin
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NormQuotM = FirstUM;
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NormQuotM = FirstUM;
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NormRemM = W + RemDM;
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NormRemM = W + DM;
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PostIncM = 0;
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PostIncM = 0;
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end else begin
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end else begin
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NormQuotM = FirstU;
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NormQuotM = FirstU;
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@ -98,8 +98,8 @@ module fdivsqrtpostproc(
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PostIncM = 0;
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PostIncM = 0;
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end else begin
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end else begin
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NormQuotM = FirstU;
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NormQuotM = FirstU;
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NormRemM = W - RemDM;
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NormRemM = W - DM;
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PostIncM = 1;
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PostIncM = ~ALTBM;
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end
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end
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// Integer division: Special cases
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// Integer division: Special cases
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@ -42,7 +42,8 @@ module fdivsqrtpreproc (
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input logic [2:0] Funct3E,
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input logic [2:0] Funct3E,
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input logic MDUE, W64E,
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input logic MDUE, W64E,
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output logic [`DIVBLEN:0] nE, nM, mM,
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output logic [`DIVBLEN:0] nE, nM, mM,
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output logic CalcOTFCSwapE, OTFCSwapE, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE,
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output logic CalcOTFCSwapE, OTFCSwapE, ALTBM, MDUM,
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output logic AsM, AZeroM, BZeroM, AZeroE, BZeroE,
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output logic [`NE+1:0] QeM,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb+3:0] X,
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output logic [`DIVb+3:0] X,
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output logic [`DIVb-1:0] DPreproc,
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output logic [`DIVb-1:0] DPreproc,
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@ -56,7 +57,7 @@ module fdivsqrtpreproc (
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// Intdiv signals
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// Intdiv signals
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
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logic [`XLEN-1:0] PosA, PosB;
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logic [`XLEN-1:0] PosA, PosB;
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logic Bs, ALTBE;
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logic AsE, BsE, ALTBE;
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logic [`XLEN-1:0] A64, B64;
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logic [`XLEN-1:0] A64, B64;
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logic [`DIVBLEN:0] mE;
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logic [`DIVBLEN:0] mE;
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logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
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logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
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@ -68,15 +69,15 @@ module fdivsqrtpreproc (
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// ***can probably merge X LZC with conversion
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// ***can probably merge X LZC with conversion
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// cout the number of leading zeros
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// cout the number of leading zeros
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assign As = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0];
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assign AsE = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0];
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assign Bs = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0];
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assign BsE = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0];
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assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
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assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
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assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
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assign B64 = W64E ? {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
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assign CalcOTFCSwapE = (As ^ Bs) & MDUE;
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assign CalcOTFCSwapE = (AsE ^ BsE) & MDUE;
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assign PosA = As ? -A64 : A64;
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assign PosA = AsE ? -A64 : A64;
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assign PosB = Bs ? -B64 : B64;
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assign PosB = BsE ? -B64 : B64;
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assign AZeroE = ~(|ForwardedSrcAE);
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assign AZeroE = ~(|ForwardedSrcAE);
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assign BZeroE = ~(|ForwardedSrcBE);
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assign BZeroE = ~(|ForwardedSrcBE);
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@ -128,6 +129,8 @@ module fdivsqrtpreproc (
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flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
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flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
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flopen #(1) azeroreg(clk, IFDivStartE, AZeroE, AZeroM);
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flopen #(1) azeroreg(clk, IFDivStartE, AZeroE, AZeroM);
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
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flopen #(1) mdureg(clk, IFDivStartE, MDUE, MDUM);
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flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
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flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
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flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(`XLEN) srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM);
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flopen #(`XLEN) srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM);
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