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Bit width error.

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Ross Thompson 2022-10-24 13:48:47 -05:00
parent 857023f5de
commit cc605a1966
1 changed files with 1 additions and 1 deletions
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pipelined/src/uncore/uartPC16550D.sv
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@ -99,7 +99,7 @@ module uartPC16550D(
// receive data
(* mark_debug = "true" *) logic [10:0] RXBR;
(* mark_debug = "true" *) logic [6:0] rxtimeoutcnt;
(* mark_debug = "true" *) logic [9:0] rxtimeoutcnt;
logic rxcentered;
logic rxparity, rxparitybit, rxstopbit;
(* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;