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Divider cleaup

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This commit is contained in:
David Harris 2021-10-03 11:22:34 -04:00
parent 3398328bf1
commit cc41d40d61
2 changed files with 5 additions and 5 deletions
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6
wally-pipelined/src/muldiv/intdivrestoring.sv
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@ -33,7 +33,7 @@ module intdivrestoring (
input logic StallM, FlushM, input logic StallM, FlushM,
input logic SignedDivideE, W64E, input logic SignedDivideE, W64E,
input logic StartDivideE, input logic StartDivideE,
input logic [`XLEN-1:0] XE, DE, input logic [`XLEN-1:0] SrcAE, SrcBE,
output logic BusyE, DivDoneM, output logic BusyE, DivDoneM,
output logic [`XLEN-1:0] QuotM, RemM output logic [`XLEN-1:0] QuotM, RemM
); );
@ -50,8 +50,8 @@ module intdivrestoring (
// save inputs on the negative edge of the execute clock. // save inputs on the negative edge of the execute clock.
// This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic. // This is unusual practice, but the inputs are not guaranteed to be stable due to some hazard and forwarding logic.
// Saving the inputs is the most hardware-efficient way to fix the issue. // Saving the inputs is the most hardware-efficient way to fix the issue.
flopen #(`XLEN) dsavereg(~clk, StartDivideE, DE, DSavedE); flopen #(`XLEN) xsavereg(~clk, StartDivideE, SrcAE, XSavedE);
flopen #(`XLEN) xsavereg(~clk, StartDivideE, XE, XSavedE); flopen #(`XLEN) dsavereg(~clk, StartDivideE, SrcBE, DSavedE);
// Handle sign extension for W-type instructions // Handle sign extension for W-type instructions
generate generate

4
wally-pipelined/src/muldiv/muldiv.sv
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@ -62,7 +62,7 @@ module muldiv (
assign DivBusyE = StartDivideE | BusyE; assign DivBusyE = StartDivideE | BusyE;
assign SignedDivideE = ~Funct3E[0]; assign SignedDivideE = ~Funct3E[0];
intdivrestoring div(.clk, .reset, .StallM, .FlushM, intdivrestoring div(.clk, .reset, .StallM, .FlushM,
.SignedDivideE, .W64E, .StartDivideE, .XE(SrcAE), .DE(SrcBE), .BusyE, .DivDoneM, .QuotM, .RemM); .SignedDivideE, .W64E, .StartDivideE, .SrcAE, .SrcBE, .BusyE, .DivDoneM, .QuotM, .RemM);
// Result multiplexer // Result multiplexer
always_comb always_comb
@ -86,7 +86,7 @@ module muldiv (
end end
// Writeback stage pipeline register // Writeback stage pipeline register
flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW); flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);
end else begin // no M instructions supported end else begin // no M instructions supported