mirror of
https://github.com/openhwgroup/cvw
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Merge pull request #706 from davidharrishmc/dev
Verilator for TestFloat, fix issue 655 about multiplications failing on f-only configuration
This commit is contained in:
commit
cc287a037a
@ -19,6 +19,7 @@ clean() {
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# Clean and run simulation with VCS
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# Clean and run simulation with VCS
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clean
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clean
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vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
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#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
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vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
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./$OUTPUT | tee program.out
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./$OUTPUT | tee program.out
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27
sim/sim-testfloat-verilator
Executable file
27
sim/sim-testfloat-verilator
Executable file
@ -0,0 +1,27 @@
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#!/usr/bin/bash
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# sim-testfloat-verilator
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# David_Harris@hmc.edu 3 April 2024
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# Run Testfloat simulations with Verilator
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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# cvtint - test integer conversion unit (fcvtint)
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# cvtfp - test floating-point conversion unit (fcvtfp)
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# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
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# add - test addition
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# fma - test fma
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# mul - test mult with fma
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# sub - test subtraction
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# div - test division
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# sqrt - test square root
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# all - test everything
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#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
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verilator -GTEST="\"all\"" -GTEST_SIZE="\"all\"" --timescale "1ns/1ns" --timing --binary --top-module testbenchfp "-I../config/shared" "-I../config/deriv/fdqh_ieee_rv64gc" ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv --relative-includes
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#vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
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# Change TEST_SIZE to only test certain FP width
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# values are QP, DP, SP, HP or all for all tests
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#vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all"
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@ -12,11 +12,12 @@
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export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
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export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
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export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
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export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
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export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
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export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
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export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin
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export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
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export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin
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# Tools
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# Tools
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# Questa and Synopsys
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# Questa and Synopsys
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export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH
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export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
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# GCC
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# GCC
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export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
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export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
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@ -83,23 +83,23 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
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if (P.FPSIZES == 1) begin
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if (P.FPSIZES == 1) begin
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logic Sum0LEZ, Sum0GEFL;
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logic Sum0LEZ, Sum0GEFL;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
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assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
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assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
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end else if (P.FPSIZES == 2) begin
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end else if (P.FPSIZES == 2) begin
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logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
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logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
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assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
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assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
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assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
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assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
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assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
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assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
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end else if (P.FPSIZES == 3) begin
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end else if (P.FPSIZES == 3) begin
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logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
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logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
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assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
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assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
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assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
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assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
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assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS2));
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assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS2));
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assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-2+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
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assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
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always_comb begin
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always_comb begin
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case (Fmt)
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case (Fmt)
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P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary
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P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary
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@ -111,13 +111,13 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
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end else if (P.FPSIZES == 4) begin
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end else if (P.FPSIZES == 4) begin
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logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
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logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
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assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
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assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.D_BIAS));
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assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.D_BIAS));
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assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-2+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
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assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-1+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
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assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.S_BIAS));
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assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.S_BIAS));
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assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-2+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
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assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-1+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
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assign Sum3LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.H_BIAS));
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assign Sum3LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.H_BIAS));
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assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-2+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
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assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
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always_comb begin
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always_comb begin
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case (Fmt)
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case (Fmt)
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2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
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2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
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@ -150,6 +150,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
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endmodule
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endmodule
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/*
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module timeregsync import cvw::*; #(parameter cvw_t P) (
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module timeregsync import cvw::*; #(parameter cvw_t P) (
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input logic clk, resetn,
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input logic clk, resetn,
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input logic we0, we1,
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input logic we0, we1,
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@ -169,6 +170,7 @@ module timeregsync import cvw::*; #(parameter cvw_t P) (
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else q <= q + 1;
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else q <= q + 1;
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endmodule
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endmodule
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module timereg import cvw::*; #(parameter cvw_t P) (
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module timereg import cvw::*; #(parameter cvw_t P) (
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input logic PCLK, PRESETn, TIMECLK,
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input logic PCLK, PRESETn, TIMECLK,
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input logic we0, we1,
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input logic we0, we1,
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@ -245,3 +247,4 @@ module graytobinary #(parameter N) (
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assign b[i] = g[i] ^ b[i+1];
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assign b[i] = g[i] ^ b[i+1];
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end
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end
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endmodule
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endmodule
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*/
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@ -30,8 +30,8 @@ import cvw::*;
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module testbenchfp;
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module testbenchfp;
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// Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
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// Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
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// to run specific precisions (e.g., quad or all)
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// to run specific precisions (e.g., quad or all)
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parameter TEST="none";
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parameter string TEST="none";
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parameter TEST_SIZE="none";
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parameter string TEST_SIZE="none";
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`include "parameter-defs.vh"
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`include "parameter-defs.vh"
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@ -85,7 +85,7 @@ module testbenchfp;
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logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [P.DIVb:0] Quot;
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logic [P.DIVb:0] Quot;
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logic CvtResSubnormUfE;
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logic CvtResSubnormUfE;
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logic DivStart=0;
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logic DivStart;
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logic FDivBusyE;
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logic FDivBusyE;
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logic OldFDivBusyE;
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logic OldFDivBusyE;
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logic reset = 1'b0;
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logic reset = 1'b0;
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@ -653,7 +653,7 @@ module testbenchfp;
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static string pp = `PATH;
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static string pp = `PATH;
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string testname;
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string testname;
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string tt0;
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string tt0;
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tt0 = $psprintf("%s", Tests[TestNum]);
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tt0 = $sformatf("%s", Tests[TestNum]);
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testname = {pp, tt0};
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testname = {pp, tt0};
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//$display("Here you are %s", testname);
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//$display("Here you are %s", testname);
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$display("\n\nRunning %s vectors ", Tests[TestNum]);
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$display("\n\nRunning %s vectors ", Tests[TestNum]);
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@ -673,7 +673,7 @@ module testbenchfp;
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// - 1 for the larger precision
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// - 1 for the larger precision
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// - 0 for the smaller precision
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// - 0 for the smaller precision
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always_comb begin
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always_comb begin
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if (P.FMTBITS == 1) ModFmt = FmtVal == P.FMT;
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if (P.FMTBITS == 1) ModFmt = {1'b0, FmtVal == P.FMT};
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else ModFmt = FmtVal;
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else ModFmt = FmtVal;
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end
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end
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@ -819,8 +819,8 @@ module testbenchfp;
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case (UnitVal)
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case (UnitVal)
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`FMAUNIT: Res = FpRes;
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`FMAUNIT: Res = FpRes;
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`DIVUNIT: Res = FpRes;
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`DIVUNIT: Res = FpRes;
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`CMPUNIT: Res = CmpRes;
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`CMPUNIT: Res = {{(FLEN-XLEN){1'b0}}, CmpRes};
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`CVTINTUNIT: if (WriteIntVal) Res = IntRes; else Res = FpRes;
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`CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN-XLEN){1'b0}}, IntRes}; else Res = FpRes;
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`CVTFPUNIT: Res = FpRes;
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`CVTFPUNIT: Res = FpRes;
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endcase
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endcase
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@ -859,6 +859,10 @@ module testbenchfp;
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DivStart = 1'b0;
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DivStart = 1'b0;
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nextstate = S0;
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nextstate = S0;
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end
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end
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default: begin
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DivStart = 1'b0;
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nextstate = S0;
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|
end
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endcase // case (state)
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endcase // case (state)
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end
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end
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@ -1149,22 +1153,22 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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2'b11: begin // quad
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2'b11: begin // quad
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X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
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X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
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Y = TestVector[12+(P.Q_LEN)-1:12];
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Y = TestVector[12+(P.Q_LEN)-1:12];
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Ans = TestVector[8];
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Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
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end
|
end
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2'b01: if (P.D_SUPPORTED) begin // double
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2'b01: if (P.D_SUPPORTED) begin // double
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
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Ans = TestVector[8];
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Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
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end
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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2'b00: if (P.S_SUPPORTED) begin // single
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
|
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
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Ans = TestVector[8];
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Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
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end
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end
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2'b10: begin // half
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2'b10: begin // half
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
|
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
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Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
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Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
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Ans = TestVector[8];
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Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
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end
|
end
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endcase
|
endcase
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`CVTFPUNIT:
|
`CVTFPUNIT:
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@ -1254,7 +1258,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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case (Fmt)
|
case (Fmt)
|
||||||
2'b11: begin // quad
|
2'b11: begin // quad
|
||||||
// {is the integer a long, is the opperation to an integer}
|
// {is the integer a long, is the opperation to an integer}
|
||||||
casex ({OpCtrl[2:1]})
|
casez ({OpCtrl[2:1]})
|
||||||
2'b11: begin // long -> quad
|
2'b11: begin // long -> quad
|
||||||
X = {P.FLEN{1'bx}};
|
X = {P.FLEN{1'bx}};
|
||||||
SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
|
SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
|
||||||
@ -1269,18 +1273,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||||||
2'b01: begin // quad -> long
|
2'b01: begin // quad -> long
|
||||||
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
|
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||||
end
|
end
|
||||||
2'b00: begin // quad -> int
|
2'b00: begin // quad -> int
|
||||||
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
|
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
2'b01: if (P.D_SUPPORTED) begin // double
|
2'b01: if (P.D_SUPPORTED) begin // double
|
||||||
// {Int->Fp?, is the integer a long}
|
// {Int->Fp?, is the integer a long}
|
||||||
casex ({OpCtrl[2:1]})
|
casez ({OpCtrl[2:1]})
|
||||||
2'b11: begin // long -> double
|
2'b11: begin // long -> double
|
||||||
X = {P.FLEN{1'bx}};
|
X = {P.FLEN{1'bx}};
|
||||||
SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
|
SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
|
||||||
@ -1295,18 +1299,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||||||
2'b01: begin // double -> long
|
2'b01: begin // double -> long
|
||||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
|
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||||
end
|
end
|
||||||
2'b00: begin // double -> int
|
2'b00: begin // double -> int
|
||||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
|
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
2'b00: if (P.S_SUPPORTED) begin // single
|
2'b00: if (P.S_SUPPORTED) begin // single
|
||||||
// {is the integer a long, is the opperation to an integer}
|
// {is the integer a long, is the opperation to an integer}
|
||||||
casex ({OpCtrl[2:1]})
|
casez ({OpCtrl[2:1]})
|
||||||
2'b11: begin // long -> single
|
2'b11: begin // long -> single
|
||||||
X = {P.FLEN{1'bx}};
|
X = {P.FLEN{1'bx}};
|
||||||
SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
|
SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
|
||||||
@ -1321,18 +1325,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||||||
2'b01: begin // single -> long
|
2'b01: begin // single -> long
|
||||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
|
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||||
end
|
end
|
||||||
2'b00: begin // single -> int
|
2'b00: begin // single -> int
|
||||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
|
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
2'b10: begin // half
|
2'b10: begin // half
|
||||||
// {is the integer a long, is the opperation to an integer}
|
// {is the integer a long, is the opperation to an integer}
|
||||||
casex ({OpCtrl[2:1]})
|
casez ({OpCtrl[2:1]})
|
||||||
2'b11: begin // long -> half
|
2'b11: begin // long -> half
|
||||||
X = {P.FLEN{1'bx}};
|
X = {P.FLEN{1'bx}};
|
||||||
SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
|
SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
|
||||||
@ -1347,12 +1351,12 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||||||
2'b01: begin // half -> long
|
2'b01: begin // half -> long
|
||||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
|
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||||
end
|
end
|
||||||
2'b00: begin // half -> int
|
2'b00: begin // half -> int
|
||||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
|
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
|
||||||
SrcA = {P.XLEN{1'bx}};
|
SrcA = {P.XLEN{1'bx}};
|
||||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
Ans = {{P.FLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
Loading…
Reference in New Issue
Block a user